diff options
| author | Kumar Gala <kumar.gala@linaro.org> | 2017-01-18 11:24:32 -0600 |
|---|---|---|
| committer | Kumar Gala <kumar.gala@linaro.org> | 2017-01-23 15:15:55 -0600 |
| commit | 098f28983f53ba5f09fcecd6bc5ee4b46f709fcd (patch) | |
| tree | 996b7f8d5b3ebf3f4f12bf38b59fd6e2ccdf6146 /tests | |
| parent | 8d4c1787bf335ef01db60ba378c9b3778e5eaf3b (diff) | |
tests: arm_irq_vector_table: Use CMSIS NVIC APIs directly
Convert testcases to use the CMSIS NVIC APIs or direct NVIC register
access rather than the internal ones so we can remove them in the future.
Change-Id: I2a5a3eae713e66944cf105e7fffa603b88522681
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/kernel/arm_irq_vector_table/src/main.c | 5 | ||||
| -rw-r--r-- | tests/legacy/kernel/test_arm_irq_vector_table/src/main.c | 5 |
2 files changed, 6 insertions, 4 deletions
diff --git a/tests/kernel/arm_irq_vector_table/src/main.c b/tests/kernel/arm_irq_vector_table/src/main.c index 81e1db163..bc6d9fe1f 100644 --- a/tests/kernel/arm_irq_vector_table/src/main.c +++ b/tests/kernel/arm_irq_vector_table/src/main.c @@ -19,6 +19,7 @@ #include <ztest.h> #include <arch/cpu.h> +#include <arch/arm/cortex_m/cmsis.h> #include <sections.h> @@ -83,9 +84,9 @@ void test_irq_vector_table(void) for (int ii = 0; ii < 3; ii++) { #if defined(CONFIG_SOC_TI_LM3S6965_QEMU) /* the QEMU does not simulate the STIR register: this is a workaround */ - _NvicIrqPend(ii); + NVIC_SetPendingIRQ(ii); #else - __scs.stir = ii; + NVIC->STIR = ii; #endif } diff --git a/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c b/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c index f678c681f..0fb41f02e 100644 --- a/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c +++ b/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c @@ -20,6 +20,7 @@ The ISRs are installed at build time, directly in the vector table. #endif #include <arch/cpu.h> +#include <arch/arm/cortex_m/cmsis.h> #include <tc_util.h> #include <sections.h> @@ -96,9 +97,9 @@ void main(void) for (int ii = 0; ii < 3; ii++) { #if defined(CONFIG_SOC_TI_LM3S6965_QEMU) /* the QEMU does not simulate the STIR register: this is a workaround */ - _NvicIrqPend(ii); + NVIC_SetPendingIRQ(ii); #else - __scs.stir = ii; + NVIC->STIR = ii; #endif } |