ARM: ux500: clock: Updated SDMMC clock handling

The APE OPP 50% mode requires no client to request
"prcmu_request_ape_opp_100_voltage" which means 1.1 V.
This APE OPP requirement is then removed from SDMMC
clock handling. Due to that the voltage is decreased
the SDMMC clock rate must also be decreased from
100 MHz to 50 MHz.

ST-Ericsson ID: 326602

Change-Id: Ie3fe11d6d031b0ba3d9eff0e698ece099490afe0
Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com>
Signed-off-by: Stefan Nilsson XK <stefan.xk.nilsson@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/17400
Reviewed-by: Sebastian RASMUSSEN <sebastian.rasmussen@stericsson.com>
Tested-by: Sebastian RASMUSSEN <sebastian.rasmussen@stericsson.com>

1 files changed, 13 insertions, 134 deletions

diff --git a/arch/arm/mach-ux500/clock-db8500.c b/arch/arm/mach-ux500/clock-db8500.c
index 09aa8cd2b9f..227906c4add 100644
--- a/arch/arm/mach-ux500/clock-db8500.c
+++ b/arch/arm/mach-ux500/clock-db8500.c
@@ -36,7 +36,6 @@
 #define SD_CLK_DIV_MASK		0x1F
 #define SD_CLK_DIV_VAL		8
 
-static DEFINE_MUTEX(sdmmcclk_mutex);
 static DEFINE_MUTEX(sysclk_mutex);
 
 static struct delayed_work sysclk_disable_work;
@@ -59,35 +58,6 @@ static struct clkops pll_clk_ops = {
 	.disable = clk_pllsrc_disable,
 };
 
-/* SDMMCCLK operations. */
-
-static int clk_sdmmcclk_enable(struct clk *clk)
-{
-	int r;
-
-	r = prcmu_request_ape_opp_100_voltage(true);
-	if (r)
-		return r;
-	return prcmu_request_clock(clk->cg_sel, true);
-}
-
-static void clk_sdmmcclk_disable(struct clk *clk)
-{
-	if (prcmu_request_clock(clk->cg_sel, false))
-		goto out_error;
-	if (prcmu_request_ape_opp_100_voltage(false))
-		goto out_error;
-	return;
-
-out_error:
-	pr_err("clock: %s failed to disable %s.\n", __func__, clk->name);
-}
-
-static struct clkops sdmmcclk_ops = {
-	.enable = clk_sdmmcclk_enable,
-	.disable = clk_sdmmcclk_disable,
-};
-
 /* SysClk operations. */
 
 static int request_sysclk(bool enable)
@@ -313,14 +283,6 @@ static struct clk clkout1 = {
 	.mutex = &sysclk_mutex,
 };
 
-static struct clk sdmmcclk = {
-	.name = "sdmmcclk",
-	.ops = &sdmmcclk_ops,
-	.cg_sel = PRCMU_SDMMCCLK,
-	.rate = 100000000,
-	.mutex = &sdmmcclk_mutex,
-};
-
 static DEF_PRCMU_CLK(sgaclk, PRCMU_SGACLK, 320000000);
 static DEF_PRCMU_CLK(uartclk, PRCMU_UARTCLK, 38400000);
 static DEF_PRCMU_CLK(msp02clk, PRCMU_MSP02CLK, 19200000);
@@ -351,6 +313,7 @@ static DEF_PRCMU_CLK(sspclk, PRCMU_SSPCLK, 24000000);
 static DEF_PRCMU_CLK(rngclk, PRCMU_RNGCLK, 19200000);
 static DEF_PRCMU_CLK(uiccclk, PRCMU_UICCCLK, 48000000);
 static DEF_PRCMU_CLK(timclk, PRCMU_TIMCLK, 2400000);
+static DEF_PRCMU_CLK(sdmmcclk, PRCMU_SDMMCCLK, 50000000);
 
 /* PRCC PClocks */
 
@@ -433,21 +396,8 @@ static DEF_PER1_KCLK(4, p1_msp1_ed_kclk, &msp02clk);
 static DEF_PER_CLK(p1_msp1_ed_clk, &p1_pclk4, &p1_msp1_ed_kclk);
 
 /* SDI0 */
-static struct clk p1_sdi0_kclk = {
-	.name = "p1_sdi0_kclk",
-	.ops = &prcc_kclk_ops,
-	.io_base = U8500_CLKRST1_BASE,
-	.cg_sel = BIT(5),
-	.parent = &sdmmcclk,
-	.mutex = &sdmmcclk_mutex,
-};
-
-static struct clk p1_sdi0_clk = {
-	.name = "p1_sdi0_clk",
-	.parent = &p1_sdi0_kclk,
-	.bus_parent = &p1_pclk5,
-	.mutex = &sdmmcclk_mutex,
-};
+static DEF_PER1_KCLK(5, p1_sdi0_kclk, &sdmmcclk);
+static DEF_PER_CLK(p1_sdi0_clk, &p1_pclk5, &p1_sdi0_kclk);
 
 /* I2C2 */
 static DEF_PER1_KCLK(6, p1_i2c2_kclk, &i2cclk);
@@ -470,21 +420,8 @@ static DEF_PER2_KCLK(0, p2_i2c3_kclk, &i2cclk);
 static DEF_PER_CLK(p2_i2c3_clk, &p2_pclk0, &p2_i2c3_kclk);
 
 /* SDI4 */
-static struct clk p2_sdi4_kclk = {
-	.name = "p2_sdi4_kclk",
-	.ops = &prcc_kclk_ops,
-	.io_base = U8500_CLKRST2_BASE,
-	.cg_sel = BIT(2),
-	.parent = &sdmmcclk,
-	.mutex = &sdmmcclk_mutex,
-};
-
-static struct clk p2_sdi4_clk = {
-	.name = "p2_sdi4_clk",
-	.parent = &p2_sdi4_kclk,
-	.bus_parent = &p2_pclk4,
-	.mutex = &sdmmcclk_mutex,
-};
+static DEF_PER2_KCLK(2, p2_sdi4_kclk, &sdmmcclk);
+static DEF_PER_CLK(p2_sdi4_clk, &p2_pclk4, &p2_sdi4_kclk);
 
 /* MSP2 */
 static DEF_PER2_KCLK(3, p2_msp2_kclk, &msp02clk);
@@ -494,42 +431,16 @@ static DEF_PER2_KCLK(4, p2_msp2_ed_kclk, &msp02clk);
 static DEF_PER_CLK(p2_msp2_ed_clk, &p2_pclk6, &p2_msp2_ed_kclk);
 
 /* SDI1 */
-static struct clk p2_sdi1_kclk = {
-	.name = "p2_sdi1_kclk",
-	.ops = &prcc_kclk_ops,
-	.io_base = U8500_CLKRST2_BASE,
-	.cg_sel = BIT(4),
-	.parent = &sdmmcclk,
-	.mutex = &sdmmcclk_mutex,
-};
-
-static struct clk p2_sdi1_clk = {
-	.name = "p2_sdi1_clk",
-	.parent = &p2_sdi1_kclk,
-	.bus_parent = &p2_pclk6,
-	.mutex = &sdmmcclk_mutex,
-};
+static DEF_PER2_KCLK(4, p2_sdi1_kclk, &sdmmcclk);
+static DEF_PER_CLK(p2_sdi1_clk, &p2_pclk6, &p2_sdi1_kclk);
 
 /* These are probably broken now. */
 static DEF_PER2_KCLK(5, p2_sdi1_ed_kclk, &sdmmcclk);
 static DEF_PER_CLK(p2_sdi1_ed_clk, &p2_pclk7, &p2_sdi1_ed_kclk);
 
 /* SDI3 */
-static struct clk p2_sdi3_kclk = {
-	.name = "p2_sdi3_kclk",
-	.ops = &prcc_kclk_ops,
-	.io_base = U8500_CLKRST2_BASE,
-	.cg_sel = BIT(5),
-	.parent = &sdmmcclk,
-	.mutex = &sdmmcclk_mutex,
-};
-
-static struct clk p2_sdi3_clk = {
-	.name = "p2_sdi3_clk",
-	.parent = &p2_sdi3_kclk,
-	.bus_parent = &p2_pclk7,
-	.mutex = &sdmmcclk_mutex,
-};
+static DEF_PER2_KCLK(5, p2_sdi3_kclk, &sdmmcclk);
+static DEF_PER_CLK(p2_sdi3_clk, &p2_pclk7, &p2_sdi3_kclk);
 
 /* These are probably broken now. */
 static DEF_PER2_KCLK(6, p2_sdi3_ed_kclk, &sdmmcclk);
@@ -554,21 +465,8 @@ static DEF_PER3_KCLK(3, p3_i2c0_kclk, &i2cclk);
 static DEF_PER_CLK(p3_i2c0_clk, &p3_pclk3, &p3_i2c0_kclk);
 
 /* SDI2 */
-static struct clk p3_sdi2_kclk = {
-	.name = "p3_sdi2_kclk",
-	.ops = &prcc_kclk_ops,
-	.io_base = U8500_CLKRST3_BASE,
-	.cg_sel = BIT(4),
-	.parent = &sdmmcclk,
-	.mutex = &sdmmcclk_mutex,
-};
-
-static struct clk p3_sdi2_clk = {
-	.name = "p3_sdi2_clk",
-	.parent = &p3_sdi2_kclk,
-	.bus_parent = &p3_pclk4,
-	.mutex = &sdmmcclk_mutex,
-};
+static DEF_PER3_KCLK(4, p3_sdi2_kclk, &sdmmcclk);
+static DEF_PER_CLK(p3_sdi2_clk, &p3_pclk4, &p3_sdi2_kclk);
 
 /* SKE */
 static DEF_PER3_KCLK(5, p3_ske_kclk, &rtc32k);
@@ -579,21 +477,8 @@ static DEF_PER3_KCLK(6, p3_uart2_kclk, &uartclk);
 static DEF_PER_CLK(p3_uart2_clk, &p3_pclk6, &p3_uart2_kclk);
 
 /* SDI5 */
-static struct clk p3_sdi5_kclk = {
-	.name = "p3_sdi5_kclk",
-	.ops = &prcc_kclk_ops,
-	.io_base = U8500_CLKRST3_BASE,
-	.cg_sel = BIT(7),
-	.parent = &sdmmcclk,
-	.mutex = &sdmmcclk_mutex,
-};
-
-static struct clk p3_sdi5_clk = {
-	.name = "p3_sdi5_clk",
-	.parent = &p3_sdi5_kclk,
-	.bus_parent = &p3_pclk7,
-	.mutex = &sdmmcclk_mutex,
-};
+static DEF_PER3_KCLK(7, p3_sdi5_kclk, &sdmmcclk);
+static DEF_PER_CLK(p3_sdi5_clk, &p3_pclk7, &p3_sdi5_kclk);
 
 /* USB */
 static DEF_PER5_KCLK(0, p5_usb_ed_kclk, &i2cclk);
@@ -1239,12 +1124,6 @@ int __init db8500_clk_init(void)
 		clkout0_ops.disable = NULL;
 		clkout1_ops.enable = NULL;
 		clkout1_ops.disable = NULL;
-	} else if (cpu_is_u8500v2()) {
-		/*
-		 * Temporary fix. The MMC driver should use clk_set_rate
-		 * when it has been implemented.
-		 */
-		(void)prcmu_set_clock_divider(PRCMU_SDMMCCLK, 8);
 	}
 
 	clks_register(u8500_common_clock_sources,