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-rw-r--r--drivers/scsi/sym53c8xx_2/sym_fw2.h2
-rw-r--r--drivers/scsi/wd33c93.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/scsi/sym53c8xx_2/sym_fw2.h b/drivers/scsi/sym53c8xx_2/sym_fw2.h
index 6e5b952312e..ae1fb179b88 100644
--- a/drivers/scsi/sym53c8xx_2/sym_fw2.h
+++ b/drivers/scsi/sym53c8xx_2/sym_fw2.h
@@ -1781,7 +1781,7 @@ static struct SYM_FWB_SCR SYM_FWB_SCR = {
* While testing with bogus QUANTUM drives, the C1010
* sometimes raised a spurious phase mismatch with
* WSR and the CHMOV(1) triggered another PM.
- * Waiting explicitely for the PHASE seemed to avoid
+ * Waiting explicitly for the PHASE seemed to avoid
* the nested phase mismatch. Btw, this didn't happen
* using my IBM drives.
*/
diff --git a/drivers/scsi/wd33c93.h b/drivers/scsi/wd33c93.h
index 61ffb860dac..00123f2383d 100644
--- a/drivers/scsi/wd33c93.h
+++ b/drivers/scsi/wd33c93.h
@@ -155,7 +155,7 @@
#define WD33C93_FS_12_15 OWNID_FS_12
#define WD33C93_FS_16_20 OWNID_FS_16
- /* pass input-clock explicitely. accepted mhz values are 8-10,12-20 */
+ /* pass input-clock explicitly. accepted mhz values are 8-10,12-20 */
#define WD33C93_FS_MHZ(mhz) (mhz)
/* Control register */