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* tracking-qcomlt-wcnss: (23 commits)
wcn36xx: avoid alloc mem with GFP_KERNEL in smd callback.
wcn36xx: eliminate the warning for unsupported SMD_EVENT
wcn36xx: Update the smd client driver to use new smd channel match method.
Bluetooth: btqcomsmd: Qualcomm WCNSS HCI driver
Bluetooth: Add HCI device identifier for Qualcomm SMD
wcn36xx: add locking around ring buffer accesses
Migrate the wifi driver from old smd driver to new smd driver.
Update the initialization sequence to enable DB410c.
Set the dma mask for platform device which is not created from DT.
ARM64 has requirement that all the dma operations has assigned devices. Otherwise, following message shown and dma allocation fails:
Got workable wireless driver.
wcn36xx: add later fw capabilities
net wireless wcn36xx adapt wcnss platform to select module by DT
net wireless wcn36xx add wcnss platform code
wcn3620: use new response format for wcn3620 remove_bsskey
wcn3620: use new response format for wcn3620 trigger_ba
wcn36xx: handle new hal response format
wcn36xx: remove powersaving for wcn3620
wcn36xx: swallow two wcn3620 IND messages
wcn36xx: introduce WCN36XX_HAL_AVOID_FREQ_RANGE_IND
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* tracking-qcomlt-scm:
firmware: qcom: scm: Fixup arm64 asm
firmware: qcom: scm: add video (vidc) scm calls
firmware: qcom: scm: Support IOMMU scm calls
firmware: qcom: scm: Support PIL SCMs
firmware: qcom: scm: Split out 32-bit specific SCM code
firmware: qcom: scm: Fix NULL coherent device
firmware: qcom: scm: Add 64 bit PAS APIs
firmware: qcom: scm: Peripheral Authentication Service
firmware: qcom: scm: Add boot APIs
firmware: qcom: scm: Generalize shared error map
firmware: qcom: scm: Add support for ARM64 SoCs
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* tracking-qcomlt-power-regulator:
cpufreq-dt: Add L2 frequency scaling support
pwer:avs: cpr: fix with new reg_sequence structures
power: avs: cpr: Fix Duplicate OPPs warning
power: avs: Register CPR with cpufreq-dt
power: avs: cpr: Use raw mem access for qfprom
power: avs: Add support for CPR (Core Power Reduction)
cpufreq-dt: Handle OPP voltage adjust events
OPP: Allow notifiers to call dev_pm_opp_get_{voltage, freq} RCU-free
PM / OPP: Support adjusting OPP voltages at runtime
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integration-linux-qcomlt
* tracking-qcomlt-mainline-rpm-smd-pil: (50 commits)
soc: qcom: smd: Support opening additional channels
soc: qcom: smd: Support multiple channels per sdev
soc: qcom: smd: Refactor channel open and close handling
soc: qcom: smd: Split discovery and state change work
soc: qcom: smd: Introduce callback setter
soc: qcom: smd: Implement id_table driver matching
soc: qcom: smd-rpm: Correct the active vs sleep state flagging
soc: smd: Migrate the wifi driver from old smd driver to new smd driver.
qcom-smd-rpm: Add MSM8916 support
fixup! regulator: smd: Add floor and corner operations
gpio:smp2p:qcom: kill set_irq_flags and use genirq
qcom/smd: support transmit/receive the data not aligned to 32bit.
remoteproc: tz_pil: skip waiting ready irq if it not provided
remoteproc: tz_pil: take relocation flag into account
remoteproc: tz_pil: make irqs, smd edge & crash-reason optional properties
regulator: smd: remove left over debug statement
regulator: smd: Add correct ifdef flag for stubs
regulator: smd: Make set_{corner,floor} work with regulator struct
regulator: smd: Add floor and corner operations
HACK: soc: qcom: smd: Add debug to fix timing
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* tracking-qcomlt-usb:
usb: host: ehci-msm: Use posted data writes on AHB
usb: chipidea: msm: Use posted data writes on AHB
usb: phy: msm: Unregister VBUS and ID events notifiers
usb: phy: msm: Ensure that workers are initialized before use
usb: phy: msm: Disable driver runtime PM
usb: phy: msm: HACK: Make Vddc configuration optional
usb: chipidea: Use extcon framework for VBUS and ID detect
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* tracking-qcomlt-clk: (46 commits)
clk: qcom: msm8916: Use RPMCC if its enabled
clk: qcom: Add RPM clock controller driver
clk: qcom: Add support for RPM Clocks
clk: qcom: msm8916: Ignore sleep_clk_src register errors
clk: qcom: msm8916: Make xo a child of the onboard oscillator
clk: qcom: create virtual child device for TSENS
soc: qcom: Add support for SAW2 regulators
clk-a53: Remove unnecessary init hooks
clk: qcom: fixup for v4.3-rc1
clk: qcom: remove __clk* apis usage
clk: qcom: HFPLL remove __clk_get_rate() usage
clk: qcom: include clk.h
clk: qcom: Allow clk_set_parent() to work on display clocks
clk: Safe frequency fixup
clk: Add support for safe frequency
clk: qcom: Handle safe frequency for krait
clk: qcom: Add A53 clock driver
clk: qcom: Add support for regmap mux-div clocks
clk: qcom: Add MSM8916 audio clocks
clk: qcom: Add MSM8916 gpu clocks
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* tracking-qcomlt-adv7511:
drm/i2c: adv7511: fixup the dapm bias level access
drm/i2c: adv7511: move to use reg_sequence
HACK: drm/i2c: adv7511: Remove hotplug event handling
drm/i2c: adv7511: Enable the audio data and clock pads on adv7533
drm/i2c: adv7511: Add Audio support.
drm/i2c: adv7511: Move the common data structures to header file
drm/i2c: adv7511: Change DSI lanes dynamically
drm/i2c: adv7511: Use internal timing generator
drm/i2c: adv7511: setup CEC registers during power off-power-on sequence
drm/i2c: adv7511: Create mipi_dsi_device for ADV7533
drm/i2c: adv7511: Add drm_bridge/connector for ADV7533
drm/i2c: adv7511: Refactor encoder slave functions
drm/i2c: adv7511: Initial support for adv7533
drm/i2c: adv7511: Fix mutex deadlock when interrupts are disabled
drm/mipi_dsi: Get DSI host by DT device node
drm/mipi_dsi: Create dummy DSI devices
drm/mipi_dsi: check for used channels
drm/mipi_dsi: refactor device creation
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* tracking-qcomlt-arm64: (31 commits)
defconfig: bt: Disable old SMD TTY for BT and enable new HCI BT.
arm64: dma-mapping: map sg lists into the SMMU as virtually contiguous
arm64: dma-mapping: fix DMA_ATTR_STRONGLY_ORDERED in __get_dma_pgprot
arm64: mm: Fix a bug in iommu dma-mapping
arm64: dma-mapping: add support for IOMMU mapper
arm64: Add support for DMA_ATTR_STRONGLY_ORDERED
arm: Add option to skip buffer zeroing
common: DMA-mapping: Add strongly ordered memory attribute
arm64: defconfig: add missing QCOM specific configs
defconfig: add tsens and spmi regulator support
arm64: defconfig: Enable drivers for WCNSS
arm64: defconfig: qcom: enable iommu v1 in defconfig
arm64: defconfig: Enable CPU frequency scaling
arm64: defconfig: Enable CPR driver
arm64: defconfig: Enable SPMI regulator driver
arm64: defconfig: Enable A53 CPU clock
arm64: defconfig: Clean-up defconfig with savedefconfig
arm64: defconfig: remove 8064 rpm clock controller selection.
arm64: defconfig: Enable LED drivers
arm64: Enable Qualcomm SMEM, RPM, and SMD drivers
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* tracking-qcomlt-iommu: (24 commits)
iommu/msm: Fix "scheduling while atomic" bug
drm/msm: temp: Add a check to be compatible against both iommuv0/v1
iommu: of: Handle IOMMU lookup failure with deferred probing or error
iommu: of: Document the of_iommu_configure() function
drivers: platform: Configure dma operations at probe time
of: dma: Split of_configure_dma() into mask and ops configuration
of: dma: Make of_dma_deconfigure() public
of: dma: Move range size workaround to of_dma_get_range()
arm: dma-mapping: Don't override dma_ops in arch_setup_dma_ops()
temp: Add dummy msm_iommu_get_ctx and fix broken build
iommu/msm: Set cacheability attributes without tex remap
iommu/msm: Add support for generic master bindings
iommu/msm: Move the contents from msm_iommu_dev.c to msm_iommu.c
iommu/msm: Add DT adaptation
DOWNSTREAM: drm/msm: use downstream iommu
qcom: iommu: Make use of domain_alloc and domain_free
arm64: provide dma cache routines with same API as 32 bit
iommu: msm: Invalidate properly from iommu_unmap
iommu: qcom: v1: fix wrong sg interator
iommu: qcom: v1: rework secure part and build
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* tracking-qcomlt-apq8016-dt: (58 commits)
wcn36xx: Update DT to support wcn36xx wifi driver
arm64: dts: remove the #if 0 around bluetooth
arm64: dts: Fix the hypervisor and tz memory region size
dts: qcom: Add CoreSight components for MSM8916
arm64: dts: qcom: Add msm8916 CoreSight components
arm64: dts: qcom: 8x16: Add fixed rate on-board XO oscillator
arm64: dts: qcom: fix typo: user LED2 uses GPIO 120, not 10
arm64: dts: apq8016-sbc: enable spi buses on LS and HS
arm64: dts: apq8016-sbc: enable i2c buses on LS and HS
arm64: dts: qcom: Add msm8916 I2C nodes.
arm64: dts: fix i2c pinconf sleep state function
arm64: dts: add support to analog audio playback
arm64: dts: msm8916: add wcd codec support
arm64: dts: Fix memory region descriptions
ARM64: dts: Fix the missing usb otg regulators.
arm64: dts: qcom: apq8016-sbc: Fix LED's naming
dts: arm64: apq8016-sbc: enable LS 1.8v regulator by default
arm64: dts: qcom: 8x16: UART2 use DMA for RX and TX
arm64: dts: qcom: 8x16: Add UART1 configuration nodes
arm64: dt: Add WCNSS related nodes
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* tracking-qcomlt-panelpicker:
drm/msm: mdp4 lvds: Check the panel node in detect_panel()
drm/msm: mdp4 lvds: continue if the panel is not connected
drm/panel: simple-panel: Add panel picker support.
drm/edid: export edid_vendor()
drm/edid: Add support to get edid early
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With the qcom_smd_open_channel() API we allow SMD devices to open
additional SMD channels, to allow implementation of multi-channel SMD
devices - like Bluetooth.
Channels are opened from the same edge as the calling SMD device is tied
to.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
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Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Conflicts:
drivers/cpufreq/cpufreq-dt.c
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This patch allows chaining additional channels to a SMD device, enabling
implementation of multi-channel SMD devies - like Bluetooth.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
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Introduce a setter for the callback function pointer to clarify the
locking around the operation and to reduce some duplication.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
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Implement a id_table based driver maching mechanism for drivers that
binds to fixed channels and doesn't need any additional configuration,
e.g. IPCRTR and DIAG.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
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Signed-off-by: Yin, Fengwei <fengwei.yin@linaro.org>
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This patch assigns the next free HCI device identifier to Bluetooth
devices based on the Qualcomm Shared Memory channels.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
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Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Conflicts:
drivers/firmware/qcom_scm.c
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Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Conflicts:
drivers/firmware/qcom_scm-64.c
drivers/firmware/qcom_scm.c
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Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Conflicts:
drivers/firmware/qcom_scm-32.c
drivers/firmware/qcom_scm.c
drivers/firmware/qcom_scm.h
Conflicts:
drivers/firmware/qcom_scm-32.c
drivers/firmware/qcom_scm-64.c
drivers/firmware/qcom_scm.c
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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This adds the Peripheral Authentication Service (PAS) interface to the
Qualcomm SCM interface. The API is used to authenticate and boot a range
of external processors in various Qualcomm platforms.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
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On some SoCs the Adaptive Voltage Scaling (AVS) technique is
employed to optimize the operating voltage of a device. At a
given frequency, the hardware monitors dynamic factors and either
makes a suggestion for how much to adjust a voltage for the
current frequency, or it automatically adjusts the voltage
without software intervention. Add an API to the OPP library for
the former case, so that AVS type devices can update the voltages
for an OPP when the hardware determines the voltage should
change. The assumption is that drivers like CPUfreq or devfreq
will register for the OPP notifiers and adjust the voltage
according to suggestions that AVS makes.
Cc: Nishanth Menon <nm@ti.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
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If built as module would throw up with
drivers/regulator/qcom_smd-regulator.c:67:5: error: redefinition of 'qcom_rpm_set_floor'
drivers/regulator/qcom_smd-regulator.c:89:5: error: redefinition of 'qcom_rpm_set_corner'
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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This patch addes the Qualcomm specific functions for setting the floor and
corner voltages on the regulators.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Conflicts:
drivers/regulator/qcom_smd-regulator.c
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Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
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The top level qcom,msm-id and qcom,board-id are utilized by bootloaders
on Qualcomm MSM platforms to determine which device tree should be
utilized and passed to the kernel.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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On recent Qualcomm platforms VBUS and ID lines are not routed to
USB PHY LINK controller. Use extcon framework to receive connect
and disconnect ID and VBUS notification.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
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Add support for clocks that are controlled by the RPM processor
on Qualcomm msm8916 based platforms.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Conflicts:
drivers/clk/qcom/Makefile
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Some CPU clocks require a way to switch away from the current PLL
they are running on, switch to a "safe clock parent" with a "safe
frequency", while reprogramming the PLL with a new rate.
To do this, we expand the current "safe parent" support with
"safe frequency".
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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Add support for the msm8916 audio clocks. This includes core bus,
low-power audio and codec clocks. They are required for audio playback.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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Add support for the msm8916 bimc clocks that are needed for GPU.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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Add support for the msm8916 TCU clocks that are needed for IOMMU.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Sometimes clocks can't accept their parent source turning off
while the source is reprogrammed to a different rate. Most
notably CPU clocks require a way to switch away from the current
PLL they're running on, reprogram that PLL to a new rate, and
then switch back to the PLL with the new rate once they're done.
Add a hook that drivers can implement allowing them to return a
'safe parent' that they can switch their parent to while the
upstream source is reprogrammed to support this.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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We want to reuse the logic in clk-mux.c for other clock drivers
that don't use readl as register accessors. Fortunately, there
really isn't much to the mux code besides the table indirection
and quirk flags if you assume any bit shifting and masking has
been done already. Pull that logic out into reusable functions
that operate on an optional table and some flags so that other
drivers can use the same logic.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Add the GDSC instances that exist as part of apq8084 MMCC block.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
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Add the GDSC instances that exist as part of apq8084 GCC block
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
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Add the GDSC instances that exist as part of msm8974 MMCC block
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
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Theres just one GDSC as part of the msm8974 GCC block.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
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Add all data for the GDSCs which are part of msm8916 GCC block.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
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mipi_dsi_devices are inherently aware of their host because they
share a parent-child hierarchy in the device tree.
Non-dsi drivers that create a dummy dsi device don't have this data.
In order to get this information, they require to a phandle to the dsi
host in the device tree.
Maintain a list of all the hosts DSI that are currently registered.
This list will be used to find the mipi_dsi_host corresponding to the
device_node passed in of_find_mipi_dsi_host_by_node.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
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We can have devices where the data bus is MIPI DSI, but the control bus
is something else (i2c, spi etc). A typical example is i2c controlled
encoder bridge chips.
Such devices too require passing DSI specific parameters (number of data
lanes, DSI mode flags, color format etc) to their DSI host. For a device
that isn't 'mipi_dsi_device', there is no way of passing such parameters.
Provide the option of creating a dummy DSI device. The main purpose of
this would be to attach to a DSI host by calling mipi_dsi_attach, and
pass DSI params.
Create mipi_dsi_new_dummy for creating a dummy dsi device. The driver
calling this needs to be aware of the mipi_dsi_host it wants to attach
to, and also the DSI virtual channel the DSI device intends to use.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
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Create a helper function mipi_dsi_device_new which takes in struct
mipi_dsi_device_info and the mipi_dsi_host. This will be called by
of_mipi_dsi_device_add.
Instead of calling device_initialize and device_add separately, merge
it into a single device_register call. This will remove the need of
having two separate funcs mipi_dsi_device_alloc and mipi_dsi_device_add.
The reason for creating mipi_dsi_device_new is that it can also be used
as a standalone way for creating a dsi device that isn't available via
DT.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
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The DMA framework currently zeros all buffers because it (righfully so)
assumes that drivers will soon need to pass the memory to a device.
Some devices/use case may not require zeroed memory and there can
be an increase in performance if we skip the zeroing. Add a DMA_ATTR
to allow skipping of DMA zeroing.
Note: only the header file was modified to add the enum to allow the code to
compile, however the arm32 implementation was not pulled, and the arm64
implementation is missing as well
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Nicolas Dechesne <nicolas.dechesne@linaro.org>
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
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Strongly ordered memory is occasionally needed for some DMA
allocations for specialized use cases. Add the corresponding
DMA attribute.
Change-Id: Idd9e756c242ef57d6fa6700e51cc38d0863b760d
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
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The top level qcom,msm-id and qcom,board-id are utilized by bootloaders
on Qualcomm MSM platforms to determine which device tree should be
utilized and passed to the kernel.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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