CSS: Changes for SDS framework

This patch does the required changes to enable CSS platforms
to build and use the SDS framework. Since SDS is always coupled with
SCMI protocol, the preexisting SCMI build flag is now renamed to
`CSS_USE_SCMI_SDS_DRIVER` which will enable both SCMI and SDS on
CSS platforms. Also some of the workarounds applied for SCMI are
now removed with SDS in place.

Change-Id: I94e8b93f05e3fe95e475c5501c25bec052588a9c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

13 files changed, 210 insertions, 71 deletions

diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index b9ae92fc0..5a3b4f8cf 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -655,9 +655,10 @@ ARM CSS platform specific build options
    SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
    during boot. Default is 1.
 
--  ``CSS_USE_SCMI_DRIVER``: Boolean flag which selects SCMI driver instead of
-   SCPI driver for communicating with the SCP during power management operations.
-   If this option is set to 1, then SCMI driver will be used. Default is 0.
+-  ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
+   instead of SCPI/BOM driver for communicating with the SCP during power
+   management operations and for SCP RAM Firmware transfer. If this option
+   is set to 1, then SCMI/SDS drivers will be used. Default is 0.
 
 ARM FVP platform specific build options
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index 91f23c0a0..ee6836803 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -37,6 +37,9 @@
 #define CSS_IRQ_TZ_WDOG			86
 #define CSS_IRQ_SEC_SYS_TIMER		91
 
+/* MHU register offsets */
+#define MHU_CPU_INTR_S_SET_OFFSET	0x308
+
 /*
  * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a
  * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts.
@@ -47,17 +50,17 @@
 					CSS_IRQ_TZ_WDOG,	\
 					CSS_IRQ_SEC_SYS_TIMER
 
+#if CSS_USE_SCMI_SDS_DRIVER
+/* Memory region for shared data storage */
+#define PLAT_ARM_SDS_MEM_BASE		ARM_SHARED_RAM_BASE
+#define PLAT_ARM_SDS_MEM_SIZE_MAX	0xDC0 /* 3520 bytes */
 /*
- * The lower Non-secure MHU channel is being used for SCMI for ARM Trusted
- * Firmware.
- * TODO: Move SCMI to Secure channel once the migration to SCMI in SCP is
- * complete.
+ * The SCMI Channel is placed right after the SDS region
  */
-#define MHU_CPU_INTR_L_SET_OFFSET	0x108
-#define MHU_CPU_INTR_H_SET_OFFSET	0x128
-#define CSS_SCMI_PAYLOAD_BASE		(NSRAM_BASE + 0x500)
-#define CSS_SCMI_MHU_DB_REG_OFF		MHU_CPU_INTR_L_SET_OFFSET
+#define CSS_SCMI_PAYLOAD_BASE		PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX
+#define CSS_SCMI_MHU_DB_REG_OFF		MHU_CPU_INTR_S_SET_OFFSET
 
+#else
 /*
  * SCP <=> AP boot configuration
  *
@@ -68,6 +71,7 @@
  * the SCP_BL2 image is transferred to SCP.
  */
 #define SCP_BOOT_CFG_ADDR		PLAT_CSS_SCP_COM_SHARED_MEM_BASE
+#endif
 
 #define CSS_MAP_DEVICE			MAP_REGION_FLAT(		\
 						CSS_DEVICE_BASE,	\
@@ -153,7 +157,13 @@
 #define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT_ALL
 
 /* Trusted mailbox base address common to all CSS */
+#if !CSS_USE_SCMI_SDS_DRIVER
+/* If SDS is not present, then the mailbox is at the bottom of SRAM */
 #define PLAT_ARM_TRUSTED_MAILBOX_BASE	ARM_TRUSTED_SRAM_BASE
+#else
+/* If SDS is present, then mailbox is at top of SRAM */
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE	(ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8)
+#endif
 
 /*
  * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP
diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/common/board_css_common.c
index 42f754e25..1758a235a 100644
--- a/plat/arm/board/common/board_css_common.c
+++ b/plat/arm/board/common/board_css_common.c
@@ -49,15 +49,6 @@ const mmap_region_t plat_arm_mmap[] = {
 	ARM_MAP_SHARED_RAM,
 	V2M_MAP_IOFPGA,
 	CSS_MAP_DEVICE,
-#if CSS_USE_SCMI_DRIVER
-	/*
-	 * The SCMI payload area is currently in the Non Secure SRAM. This is
-	 * a potential security risk but this will be resolved once SCP
-	 * completely replaces SCPI with SCMI as the only communication
-	 * protocol.
-	 */
-	CSS_MAP_NSRAM,
-#endif
 	SOC_CSS_MAP_DEVICE,
 	{0}
 };
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index a2938162e..f32ab12ee 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -77,13 +77,8 @@
 #endif
 
 #ifdef IMAGE_BL31
-# if CSS_USE_SCMI_DRIVER
-#  define PLAT_ARM_MMAP_ENTRIES		6
-#  define MAX_XLAT_TABLES		3
-# else
 #  define PLAT_ARM_MMAP_ENTRIES		5
 #  define MAX_XLAT_TABLES		2
-# endif
 #endif
 
 #ifdef IMAGE_BL32
@@ -158,7 +153,9 @@
 /*
  * Base address of the first memory region used for communication between AP
  * and SCP. Used by the BOM and SCPI protocols.
- *
+ */
+#if !CSS_USE_SCMI_SDS_DRIVER
+/*
  * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which
  * means the SCP/AP configuration data gets overwritten when the AP initiates
  * communication with the SCP. The configuration data is expected to be a
@@ -168,6 +165,7 @@
 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE	(ARM_TRUSTED_SRAM_BASE + 0x80)
 #define PLAT_CSS_PRIMARY_CPU_SHIFT		8
 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH		4
+#endif
 
 /*
  * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
diff --git a/plat/arm/board/juno/juno_bl2_setup.c b/plat/arm/board/juno/juno_bl2_setup.c
index abceb0f5e..ba2a34138 100644
--- a/plat/arm/board/juno/juno_bl2_setup.c
+++ b/plat/arm/board/juno/juno_bl2_setup.c
@@ -30,6 +30,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
 	return err;
 }
 
+#if !CSS_USE_SCMI_SDS_DRIVER
 /*
  * We need to override some of the platform functions when booting SP_MIN
  * on Juno AArch32.
@@ -53,4 +54,6 @@ void bl2_platform_setup(void)
 	mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config);
 	VERBOSE("BL2: Restored SCP Boot config = 0x%x\n", scp_boot_config);
 }
+#endif
+
 #endif /* JUNO_AARCH32_EL3_RUNTIME */
diff --git a/plat/arm/css/common/aarch32/css_helpers.S b/plat/arm/css/common/aarch32/css_helpers.S
index f131e67a3..80aa24c62 100644
--- a/plat/arm/css/common/aarch32/css_helpers.S
+++ b/plat/arm/css/common/aarch32/css_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -68,6 +68,24 @@ endfunc css_calc_core_pos_swap_cluster
 	 * cpu (applicable ony after a cold boot)
 	 * -----------------------------------------------------
 	 */
+#if CSS_USE_SCMI_SDS_DRIVER
+func plat_is_my_cpu_primary
+	mov	r10, lr
+	bl	plat_my_core_pos
+	mov	r4, r0
+	bl	sds_get_primary_cpu_id
+	/* Check for error */
+	mov	r1, #0xffffffff
+	cmp	r0, r1
+	beq	1f
+	cmp	r0, r4
+	moveq	r0, #1
+	movne	r0, #0
+	bx	r10
+1:
+	no_ret	plat_panic_handler
+endfunc plat_is_my_cpu_primary
+#else
 func plat_is_my_cpu_primary
 	mov	r10, lr
 	bl	plat_my_core_pos
@@ -80,3 +98,4 @@ func plat_is_my_cpu_primary
 	movne	r0, #0
 	bx	r10
 endfunc plat_is_my_cpu_primary
+#endif
diff --git a/plat/arm/css/common/aarch64/css_helpers.S b/plat/arm/css/common/aarch64/css_helpers.S
index 0cf8f86bb..59d920650 100644
--- a/plat/arm/css/common/aarch64/css_helpers.S
+++ b/plat/arm/css/common/aarch64/css_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -88,6 +88,23 @@ endfunc css_calc_core_pos_swap_cluster
 	 * cpu (applicable ony after a cold boot)
 	 * -----------------------------------------------------
 	 */
+#if CSS_USE_SCMI_SDS_DRIVER
+func plat_is_my_cpu_primary
+	mov	x9, x30
+	bl	plat_my_core_pos
+	mov	x4, x0
+	bl	sds_get_primary_cpu_id
+	/* Check for error */
+	mov	x1, #0xffffffff
+	cmp	x0, x1
+	b.eq	1f
+	cmp	x0, x4
+	cset	w0, eq
+	ret	x9
+1:
+	no_ret	plat_panic_handler
+endfunc plat_is_my_cpu_primary
+#else
 func plat_is_my_cpu_primary
 	mov	x9, x30
 	bl	plat_my_core_pos
@@ -99,3 +116,4 @@ func plat_is_my_cpu_primary
 	cset	w0, eq
 	ret	x9
 endfunc plat_is_my_cpu_primary
+#endif
diff --git a/plat/arm/css/common/css_common.mk b/plat/arm/css/common/css_common.mk
index 9381e4cd2..63e305916 100644
--- a/plat/arm/css/common/css_common.mk
+++ b/plat/arm/css/common/css_common.mk
@@ -9,7 +9,7 @@
 CSS_LOAD_SCP_IMAGES	?=	1
 
 # By default, SCMI driver is disabled for CSS platforms
-CSS_USE_SCMI_DRIVER	?=	0
+CSS_USE_SCMI_SDS_DRIVER	?=	0
 
 PLAT_INCLUDES		+=	-Iinclude/plat/arm/css/common			\
 				-Iinclude/plat/arm/css/common/aarch64
@@ -19,18 +19,14 @@ PLAT_BL_COMMON_SOURCES	+=	plat/arm/css/common/${ARCH}/css_helpers.S
 
 BL1_SOURCES		+=	plat/arm/css/common/css_bl1_setup.c
 
-BL2_SOURCES		+=	plat/arm/css/common/css_bl2_setup.c		\
-				plat/arm/css/drivers/scpi/css_mhu.c		\
-				plat/arm/css/drivers/scpi/css_scpi.c
+BL2_SOURCES		+=	plat/arm/css/common/css_bl2_setup.c
 
-BL2U_SOURCES		+=	plat/arm/css/common/css_bl2u_setup.c		\
-				plat/arm/css/drivers/scpi/css_mhu.c		\
-				plat/arm/css/drivers/scpi/css_scpi.c
+BL2U_SOURCES		+=	plat/arm/css/common/css_bl2u_setup.c
 
 BL31_SOURCES		+=	plat/arm/css/common/css_pm.c			\
 				plat/arm/css/common/css_topology.c
 
-ifeq (${CSS_USE_SCMI_DRIVER},0)
+ifeq (${CSS_USE_SCMI_SDS_DRIVER},0)
 BL31_SOURCES		+=	plat/arm/css/drivers/scp/css_pm_scpi.c		\
 				plat/arm/css/drivers/scpi/css_mhu.c		\
 				plat/arm/css/drivers/scpi/css_scpi.c
@@ -56,19 +52,34 @@ ifeq (${CSS_LOAD_SCP_IMAGES},1)
     $(eval $(call FWU_FIP_ADD_IMG,SCP_BL2U,--scp-fwu-cfg))
   endif
 
-  BL2U_SOURCES		+=	plat/arm/css/drivers/scp/css_bom_bootloader.c
-  BL2_SOURCES		+=	plat/arm/css/drivers/scp/css_bom_bootloader.c
-endif
+  ifeq (${CSS_USE_SCMI_SDS_DRIVER},1)
+    BL2U_SOURCES	+=	plat/arm/css/drivers/scp/css_sds.c	\
+				plat/arm/css/drivers/sds/sds.c
 
-# Enable option to detect whether the SCP ROM firmware in use predates version
-# 1.7.0 and therefore, is incompatible.
-CSS_DETECT_PRE_1_7_0_SCP	:=	1
+    BL2_SOURCES		+=	plat/arm/css/drivers/scp/css_sds.c	\
+				plat/arm/css/drivers/sds/sds.c
+  else
+    BL2U_SOURCES	+=	plat/arm/css/drivers/scp/css_bom_bootloader.c	\
+				plat/arm/css/drivers/scpi/css_mhu.c		\
+				plat/arm/css/drivers/scpi/css_scpi.c
 
-# Process CSS_DETECT_PRE_1_7_0_SCP flag
-$(eval $(call assert_boolean,CSS_DETECT_PRE_1_7_0_SCP))
-$(eval $(call add_define,CSS_DETECT_PRE_1_7_0_SCP))
+    BL2_SOURCES		+=	plat/arm/css/drivers/scp/css_bom_bootloader.c	\
+				plat/arm/css/drivers/scpi/css_mhu.c		\
+				plat/arm/css/drivers/scpi/css_scpi.c
+    # Enable option to detect whether the SCP ROM firmware in use predates version
+    # 1.7.0 and therefore, is incompatible.
+    CSS_DETECT_PRE_1_7_0_SCP	:=	1
+
+    # Process CSS_DETECT_PRE_1_7_0_SCP flag
+    $(eval $(call assert_boolean,CSS_DETECT_PRE_1_7_0_SCP))
+    $(eval $(call add_define,CSS_DETECT_PRE_1_7_0_SCP))
+  endif
+endif
 
-# Process CSS_USE_SCMI_DRIVER flag
-$(eval $(call assert_boolean,CSS_USE_SCMI_DRIVER))
-$(eval $(call add_define,CSS_USE_SCMI_DRIVER))
+ifeq (${CSS_USE_SCMI_SDS_DRIVER},1)
+  PLAT_BL_COMMON_SOURCES	+=	plat/arm/css/drivers/sds/${ARCH}/sds_helpers.S
+endif
 
+# Process CSS_USE_SCMI_SDS_DRIVER flag
+$(eval $(call assert_boolean,CSS_USE_SCMI_SDS_DRIVER))
+$(eval $(call add_define,CSS_USE_SCMI_SDS_DRIVER))
diff --git a/plat/arm/css/common/sp_min/css_sp_min.mk b/plat/arm/css/common/sp_min/css_sp_min.mk
index 7423d781b..28eb2dbda 100644
--- a/plat/arm/css/common/sp_min/css_sp_min.mk
+++ b/plat/arm/css/common/sp_min/css_sp_min.mk
@@ -8,7 +8,7 @@
 BL32_SOURCES		+=	plat/arm/css/common/css_pm.c			\
 				plat/arm/css/common/css_topology.c
 
-ifeq (${CSS_USE_SCMI_DRIVER},0)
+ifeq (${CSS_USE_SCMI_SDS_DRIVER},0)
 BL32_SOURCES		+=	plat/arm/css/drivers/scp/css_pm_scpi.c		\
 				plat/arm/css/drivers/scpi/css_mhu.c		\
 				plat/arm/css/drivers/scpi/css_scpi.c
diff --git a/plat/arm/css/drivers/scp/css_bom_bootloader.c b/plat/arm/css/drivers/scp/css_bom_bootloader.c
index 70fc8ecff..24b6fd727 100644
--- a/plat/arm/css/drivers/scp/css_bom_bootloader.c
+++ b/plat/arm/css/drivers/scp/css_bom_bootloader.c
@@ -6,12 +6,12 @@
 
 #include <arch_helpers.h>
 #include <assert.h>
-#include <cassert.h>
 #include <css_def.h>
 #include <debug.h>
 #include <platform.h>
 #include <stdint.h>
 #include "../scpi/css_mhu.h"
+#include "../scpi/css_scpi.h"
 
 /* ID of the MHU slot used for the BOM protocol */
 #define BOM_MHU_SLOT_ID		0
@@ -45,18 +45,6 @@ typedef struct {
 	uint32_t block_size;
 } cmd_data_payload_t;
 
-/*
- * All CSS platforms load SCP_BL2/SCP_BL2U just below BL rw-data and above
- * BL2/BL2U (this is where BL31 usually resides except when ARM_BL31_IN_DRAM is
- * set. Ensure that SCP_BL2/SCP_BL2U do not overflow into BL1 rw-data nor
- * BL2/BL2U.
- */
-CASSERT(SCP_BL2_LIMIT <= BL1_RW_BASE, assert_scp_bl2_limit_overwrite_bl1);
-CASSERT(SCP_BL2U_LIMIT <= BL1_RW_BASE, assert_scp_bl2u_limit_overwrite_bl1);
-
-CASSERT(SCP_BL2_BASE >= BL2_LIMIT, assert_scp_bl2_overwrite_bl2);
-CASSERT(SCP_BL2U_BASE >= BL2U_LIMIT, assert_scp_bl2u_overwrite_bl2u);
-
 static void scp_boot_message_start(void)
 {
 	mhu_secure_message_start(BOM_MHU_SLOT_ID);
@@ -183,3 +171,11 @@ int css_scp_boot_image_xfer(void *image, unsigned int image_size)
 
 	return 0;
 }
+
+int css_scp_boot_ready(void)
+{
+	VERBOSE("Waiting for SCP to signal it is ready to go on\n");
+
+	/* Wait for SCP to signal it's ready */
+	return scpi_wait_ready();
+}
diff --git a/plat/arm/css/drivers/scp/css_pm_scmi.c b/plat/arm/css/drivers/scp/css_pm_scmi.c
index 1ca70a249..4df99205b 100644
--- a/plat/arm/css/drivers/scp/css_pm_scmi.c
+++ b/plat/arm/css/drivers/scp/css_pm_scmi.c
@@ -324,8 +324,8 @@ void __dead2 css_scp_sys_reboot(void)
 scmi_channel_plat_info_t plat_css_scmi_plat_info = {
 		.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
 		.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
-		.db_preserve_mask = 0xfffffffd,
-		.db_modify_mask = 0x2,
+		.db_preserve_mask = 0xfffffffe,
+		.db_modify_mask = 0x1,
 };
 
 void plat_arm_pwrc_setup(void)
diff --git a/plat/arm/css/drivers/scp/css_scp.h b/plat/arm/css/drivers/scp/css_scp.h
index 183022cd6..db7218f2b 100644
--- a/plat/arm/css/drivers/scp/css_scp.h
+++ b/plat/arm/css/drivers/scp/css_scp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,8 +7,9 @@
 #ifndef __CSS_SCP_H__
 #define __CSS_SCP_H__
 
+#include <cassert.h>
 #include <types.h>
-#include "../scpi/css_scpi.h"
+#include <platform_def.h>
 
 /* Forward declarations */
 struct psci_power_state;
@@ -28,10 +29,20 @@ int css_scp_boot_image_xfer(void *image, unsigned int image_size);
  * API to wait for SCP to signal till it's ready after booting the transferred
  * image.
  */
-static inline int css_scp_boot_ready(void)
-{
-	VERBOSE("Waiting for SCP to signal it is ready to go on\n");
-	return scpi_wait_ready();
-}
+int css_scp_boot_ready(void);
+
+#if CSS_LOAD_SCP_IMAGES
+/*
+ * All CSS platforms load SCP_BL2/SCP_BL2U just below BL rw-data and above
+ * BL2/BL2U (this is where BL31 usually resides except when ARM_BL31_IN_DRAM is
+ * set. Ensure that SCP_BL2/SCP_BL2U do not overflow into BL1 rw-data nor
+ * BL2/BL2U.
+ */
+CASSERT(SCP_BL2_LIMIT <= BL1_RW_BASE, assert_scp_bl2_limit_overwrite_bl1);
+CASSERT(SCP_BL2U_LIMIT <= BL1_RW_BASE, assert_scp_bl2u_limit_overwrite_bl1);
+
+CASSERT(SCP_BL2_BASE >= BL2_LIMIT, assert_scp_bl2_overwrite_bl2);
+CASSERT(SCP_BL2U_BASE >= BL2U_LIMIT, assert_scp_bl2u_overwrite_bl2u);
+#endif
 
 #endif	/* __CSS_SCP_H__ */
diff --git a/plat/arm/css/drivers/scp/css_sds.c b/plat/arm/css/drivers/scp/css_sds.c
new file mode 100644
index 000000000..666295dae
--- /dev/null
+++ b/plat/arm/css/drivers/scp/css_sds.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <assert.h>
+#include <css_def.h>
+#include <debug.h>
+#include <platform.h>
+#include <stdint.h>
+#include "../sds/sds.h"
+
+int css_scp_boot_image_xfer(void *image, unsigned int image_size)
+{
+	int ret;
+	unsigned int image_offset, image_flags;
+
+	ret = sds_init();
+	if (ret != SDS_OK) {
+		ERROR("SCP SDS initialization failed\n");
+		panic();
+	}
+
+	VERBOSE("Writing SCP image metadata\n");
+	image_offset = (uintptr_t) image - ARM_TRUSTED_SRAM_BASE;
+	ret = sds_struct_write(SDS_SCP_IMG_STRUCT_ID, SDS_SCP_IMG_ADDR_OFFSET,
+			&image_offset, SDS_SCP_IMG_ADDR_SIZE,
+			SDS_ACCESS_MODE_NON_CACHED);
+	if (ret != SDS_OK)
+		goto sds_fail;
+
+	ret = sds_struct_write(SDS_SCP_IMG_STRUCT_ID, SDS_SCP_IMG_SIZE_OFFSET, &image_size, SDS_SCP_IMG_SIZE_SIZE,
+			SDS_ACCESS_MODE_NON_CACHED);
+	if (ret != SDS_OK)
+			goto sds_fail;
+
+	VERBOSE("Marking SCP image metadata as valid\n");
+	image_flags = SDS_SCP_IMG_VALID_FLAG_BIT;
+	ret = sds_struct_write(SDS_SCP_IMG_STRUCT_ID, SDS_SCP_IMG_FLAG_OFFSET, &image_flags, SDS_SCP_IMG_FLAG_SIZE,
+			SDS_ACCESS_MODE_NON_CACHED);
+	if (ret != SDS_OK)
+			goto sds_fail;
+
+	return 0;
+sds_fail:
+	ERROR("SCP SDS write to SCP IMG struct failed\n");
+	panic();
+}
+
+/*
+ * API to wait for SCP to signal till it's ready after booting the transferred
+ * image.
+ */
+int css_scp_boot_ready(void)
+{
+	uint32_t scp_feature_availability_flags;
+	int ret;
+
+	VERBOSE("Waiting for SCP RAM to complete its initialization process\n");
+
+	/* Wait for the SCP RAM Firmware to complete its initialization process */
+	while (1) {
+		ret = sds_struct_read(SDS_FEATURE_AVAIL_STRUCT_ID, 0,
+				&scp_feature_availability_flags,
+				SDS_FEATURE_AVAIL_SIZE,
+				SDS_ACCESS_MODE_NON_CACHED);
+		if (ret == SDS_ERR_STRUCT_NOT_FINALIZED)
+			continue;
+
+		if (ret != SDS_OK) {
+			ERROR(" sds_struct_read failed /n");
+			panic();
+		}
+
+		if (scp_feature_availability_flags &
+				SDS_FEATURE_AVAIL_SCP_RAM_READY_BIT)
+			return 0;
+	}
+}