diff options
| author | Jagadeesh Ujja <jagadeesh.ujja@arm.com> | 2019-07-22 15:31:41 +0530 |
|---|---|---|
| committer | Thomas Abraham <thomas.abraham@arm.com> | 2019-07-22 19:12:22 +0530 |
| commit | 76b9d58bbc4fc93dae636f4fc002754b74008b48 (patch) | |
| tree | f95ef8747388049fc4fb0f980bf92a2bb22d8bf6 | |
| parent | 7dfb5174314cb3f9d5281de64d66465725d8b258 (diff) | |
product/rddaniel: add initial support for rd-daniel platformRD-DANIEL-CFGM-20191024-RC0
RD-Daniel is Arm's Infrastructure platform and is built using various
Arm IP's including Zeus and CMN-Rhodes. Add initial support for
RD-Daniel platform.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
80 files changed, 7979 insertions, 16 deletions
diff --git a/framework/src/fwk_module.c b/framework/src/fwk_module.c index 8f695842..74f21efd 100644 --- a/framework/src/fwk_module.c +++ b/framework/src/fwk_module.c @@ -19,8 +19,8 @@ #include <internal/fwk_notification.h> #endif -#define EVENT_COUNT 64 -#define NOTIFICATION_COUNT 64 +#define EVENT_COUNT 128 +#define NOTIFICATION_COUNT 128 #define BIND_ROUND_MAX 1 /* Pre-runtime phase stages */ diff --git a/module/cmn_rhodes/include/mod_cmn_rhodes.h b/module/cmn_rhodes/include/mod_cmn_rhodes.h new file mode 100644 index 00000000..458d145f --- /dev/null +++ b/module/cmn_rhodes/include/mod_cmn_rhodes.h @@ -0,0 +1,132 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MOD_CMN_RHODES_H +#define MOD_CMN_RHODES_H + +#include <stdint.h> + +/*! + * \addtogroup GroupModules Modules + * @{ + */ + +/*! + * \defgroup GroupModuleCMN_RHODES CMN_RHODES + * + * \brief Arm Coherent Mesh Network (CMN) RHODES module + * + * \details This module adds support for the CMN_RHODES interconnect + * @{ + */ + +/*! + * \brief Module API indices + */ +enum mod_cmn_rhodes_api_idx { + /*! Index of the PPU_V1 power state observer API */ + MOD_CMN_RHODES_API_IDX_PPU_OBSERVER, + + /*! Number of APIs */ + MOD_CMN_RHODES_API_COUNT +}; + +/*! + * \brief Memory region configuration type + */ +enum mod_cmn_rhodes_mem_region_type { + /*! Input/Output region (serviced by dedicated HN-I and HN-D nodes) */ + MOD_CMN_RHODES_MEM_REGION_TYPE_IO, + + /*! + * Region backed by the system cache (serviced by all HN-F nodes in the + * system) + */ + MOD_CMN_RHODES_MEM_REGION_TYPE_SYSCACHE, + + /*! + * Sub region of the system cache for non-hashed access (serviced by + * dedicated SN-F nodes). + */ + MOD_CMN_RHODES_REGION_TYPE_SYSCACHE_SUB, +}; + +/*! + * \brief Memory region map descriptor + */ +struct mod_cmn_rhodes_mem_region_map { + /*! Base address */ + uint64_t base; + + /*! Region size in bytes */ + uint64_t size; + + /*! Region configuration type */ + enum mod_cmn_rhodes_mem_region_type type; + + /*! + * \brief Target node identifier + * + * \note Not used for \ref + * mod_cmn_rhodes_mem_region_type. + * MOD_CMN_RHODES_MEM_REGION_TYPE_SYSCACHE + * memory regions as it uses the pool of HN-F nodes available in the + * system + */ + unsigned int node_id; +}; + +/*! + * \brief CMN_RHODES configuration data + */ +struct mod_cmn_rhodes_config { + /*! Peripheral base address. */ + uintptr_t base; + + /*! Size along x-axis of the interconnect mesh */ + unsigned int mesh_size_x; + + /*! Size along y-axis of the interconnect mesh */ + unsigned int mesh_size_y; + + /*! Default HN-D node identifier containing the global configuration */ + unsigned int hnd_node_id; + + /*! + * \brief Table of SN-Fs used as targets for the HN-F nodes + * + * \details Each entry of this table corresponds to a HN-F node in the + * system. The HN-F's logical identifiers are used as indices in this + * table + */ + const unsigned int *snf_table; + + /*! Number of entries in the \ref snf_table */ + size_t snf_count; + + /*! Table of region memory map entries */ + const struct mod_cmn_rhodes_mem_region_map *mmap_table; + + /*! Number of entries in the \ref mmap_table */ + size_t mmap_count; + + /*! Identifier of the clock that this device depends on */ + fwk_id_t clock_id; + + /*! Flag when set to true enables HN-F with CAL support */ + bool hnf_cal_mode; +}; + +/*! + * @} + */ + +/*! + * @} + */ + +#endif /* MOD_CMN_RHODES_H */ diff --git a/module/cmn_rhodes/src/Makefile b/module/cmn_rhodes/src/Makefile new file mode 100644 index 00000000..a5afe0cd --- /dev/null +++ b/module/cmn_rhodes/src/Makefile @@ -0,0 +1,13 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_LIB_NAME := CMN_RHODES + +BS_LIB_SOURCES = mod_cmn_rhodes.c +BS_LIB_SOURCES += cmn_rhodes.c + +include $(BS_DIR)/lib.mk diff --git a/module/cmn_rhodes/src/cmn_rhodes.c b/module/cmn_rhodes/src/cmn_rhodes.c new file mode 100644 index 00000000..4b39c102 --- /dev/null +++ b/module/cmn_rhodes/src/cmn_rhodes.c @@ -0,0 +1,207 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_assert.h> +#include <fwk_macros.h> +#include <fwk_math.h> +#include <cmn_rhodes.h> + +static bool node_id_size_9bits; + +unsigned int get_node_child_count(void *node_base) +{ + struct node_header *node = node_base; + return node->CHILD_INFO & CMN_RHODES_CHILD_INFO_COUNT; +} + +enum node_type get_node_type(void *node_base) +{ + struct node_header *node = node_base; + return (enum node_type)(node->NODE_INFO & CMN_RHODES_NODE_INFO_TYPE); +} + +unsigned int get_node_id(void *node_base) +{ + struct node_header *node = node_base; + return (node->NODE_INFO & CMN_RHODES_NODE_INFO_ID) >> + CMN_RHODES_NODE_INFO_ID_POS; +} + +unsigned int get_node_logical_id(void *node_base) +{ + struct node_header *node = node_base; + return (node->NODE_INFO & CMN_RHODES_NODE_INFO_LOGICAL_ID) >> + CMN_RHODES_NODE_INFO_LOGICAL_ID_POS; +} + +void *get_child_node(uintptr_t base, void *node_base, unsigned int child_index) +{ + struct node_header *node = node_base; + uint32_t child_pointer; + unsigned int offset; + void *child_node; + + child_pointer = node->CHILD_POINTER[child_index]; + offset = child_pointer & CMN_RHODES_CHILD_POINTER_OFFSET; + + child_node = (void *)(base + offset); + return child_node; +} + +unsigned int get_child_node_id(void *node_base, + unsigned int child_index) +{ + struct node_header *node = node_base; + uint32_t node_pointer; + unsigned int device_id; + + node_pointer = (node->CHILD_POINTER[child_index] & + CMN_RHODES_CHILD_POINTER_EXT_NODE_POINTER) >> + CMN_RHODES_CHILD_POINTER_EXT_NODE_POINTER_POS; + + device_id = (((node_pointer >> 6) & 0xff) << 3) | + ((node_pointer & 0x1) << 2) | + ((node_pointer >> 2) & 0x3); + + return device_id; +} + +bool is_child_external(void *node_base, unsigned int child_index) +{ + struct node_header *node = node_base; + return !!(node->CHILD_POINTER[child_index] & (1 << 31)); +} + +uint64_t sam_encode_region_size(uint64_t size) +{ + uint64_t blocks; + uint64_t result; + + /* Size must be a multiple of SAM_GRANULARITY */ + assert((size % SAM_GRANULARITY) == 0); + + blocks = size / SAM_GRANULARITY; + result = fwk_math_log2(blocks); + + return result; +} + +void configure_region(volatile uint64_t *reg, unsigned int bit_offset, + uint64_t base, uint64_t size, enum sam_node_type node_type) +{ + uint64_t value; + + assert(reg); + assert((base % size) == 0); + + value = CMN_RHODES_RNSAM_REGION_ENTRY_VALID; + value |= node_type << CMN_RHODES_RNSAM_REGION_ENTRY_TYPE_POS; + value |= sam_encode_region_size(size) << + CMN_RHODES_RNSAM_REGION_ENTRY_SIZE_POS; + value |= (base / SAM_GRANULARITY) << CMN_RHODES_RNSAM_REGION_ENTRY_BASE_POS; + + *reg = value; +} + +static const char * const type_to_name[] = { + [NODE_TYPE_INVALID] = "<Invalid>", + [NODE_TYPE_DVM] = "DVM", + [NODE_TYPE_CFG] = "CFG", + [NODE_TYPE_DTC] = "DTC", + [NODE_TYPE_HN_I] = "HN-I", + [NODE_TYPE_HN_F] = "HN-F", + [NODE_TYPE_XP] = "XP", + [NODE_TYPE_SBSX] = "SBSX", + [NODE_TYPE_RN_I] = "RN-I", + [NODE_TYPE_RN_D] = "RN-D", + [NODE_TYPE_RN_SAM] = "RN-SAM", +}; + +static const char * const type_to_name_cml[] = { + [NODE_TYPE_CXRA - NODE_TYPE_CML_BASE] = "CXRA", + [NODE_TYPE_CXHA - NODE_TYPE_CML_BASE] = "CXHA", + [NODE_TYPE_CXLA - NODE_TYPE_CML_BASE] = "CXLA", + +}; + +const char *get_node_type_name(enum node_type node_type) +{ + /* Base node IDs */ + if (node_type <= NODE_TYPE_RN_SAM) + return type_to_name[node_type]; + + /* CML node IDs */ + if ((node_type >= NODE_TYPE_CML_BASE) && + (node_type <= NODE_TYPE_CXLA)) + return type_to_name_cml[node_type - NODE_TYPE_CML_BASE]; + + /* Invalid node IDs */ + return type_to_name[NODE_TYPE_INVALID]; +} + +unsigned int get_node_pos_x(void *node_base) +{ + struct node_header *node = node_base; + if (node_id_size_9bits) + return (unsigned int)((node->NODE_INFO >> + CMN_RHODES_NODE_ID_X_POS_9_BIT) & + CMN_RHODES_NODE_ID_9_BIT_MASK); + else + return (unsigned int)((node->NODE_INFO >> + CMN_RHODES_NODE_ID_X_POS_9_BIT) & + CMN_RHODES_NODE_ID_7_BIT_MASK); +} + +unsigned int get_node_pos_y(void *node_base) +{ + struct node_header *node = node_base; + if (node_id_size_9bits) + return (unsigned int)((node->NODE_INFO >> + CMN_RHODES_NODE_ID_Y_POS) & + CMN_RHODES_NODE_ID_9_BIT_MASK); + else + return (unsigned int)((node->NODE_INFO >> + CMN_RHODES_NODE_ID_Y_POS) & + CMN_RHODES_NODE_ID_7_BIT_MASK); +} + +struct cmn_rhodes_cfgm_reg *get_root_node(uintptr_t base, + unsigned int hnd_node_id, unsigned int mesh_size_x, + unsigned int mesh_size_y) +{ + unsigned int encoding_bits; + unsigned int mask_bits; + unsigned int node_pos_x; + unsigned int node_pos_y; + unsigned int node_port; + uintptr_t offset; + + /* + * Determine the number of bits used to represent each node coordinate based + * on the mesh size as per CMN_RHODES specification. + */ + encoding_bits = ((mesh_size_x > 4) || (mesh_size_y > 4)) ? 3 : 2; + + if (encoding_bits == 3) + node_id_size_9bits = true; + + /* Extract node coordinates from the node identifier */ + mask_bits = (1 << encoding_bits) - 1; + node_pos_y = (hnd_node_id >> CMN_RHODES_NODE_ID_Y_POS_OFFSET) & mask_bits; + node_pos_x = (hnd_node_id >> (CMN_RHODES_NODE_ID_Y_POS_OFFSET + + encoding_bits)) & mask_bits; + node_port = (hnd_node_id >> CMN_RHODES_NODE_ID_PORT_POS) & + CMN_RHODES_NODE_ID_PORT_MASK; + + /* Calculate node address offset */ + offset = (node_pos_y << CMN_RHODES_ROOT_NODE_OFFSET_Y_POS) | + (node_pos_x << (CMN_RHODES_ROOT_NODE_OFFSET_Y_POS + + encoding_bits)) | + (node_port << CMN_RHODES_ROOT_NODE_OFFSET_PORT_POS); + + return (struct cmn_rhodes_cfgm_reg *)(base + offset); +} diff --git a/module/cmn_rhodes/src/cmn_rhodes.h b/module/cmn_rhodes/src/cmn_rhodes.h new file mode 100644 index 00000000..e231c104 --- /dev/null +++ b/module/cmn_rhodes/src/cmn_rhodes.h @@ -0,0 +1,346 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions and utility functions for the CMN RHODES module. + */ + +#ifndef CMN_RHODES_H +#define CMN_RHODES_H + +#include <stdint.h> +#include <stdbool.h> +#include <fwk_macros.h> + +#define SAM_GRANULARITY (64 * FWK_MIB) + +enum node_type { + NODE_TYPE_INVALID = 0x0, + NODE_TYPE_DVM = 0x1, + NODE_TYPE_CFG = 0x2, + NODE_TYPE_DTC = 0x3, + NODE_TYPE_HN_I = 0x4, + NODE_TYPE_HN_F = 0x5, + NODE_TYPE_XP = 0x6, + NODE_TYPE_SBSX = 0x7, + NODE_TYPE_RN_I = 0xA, + NODE_TYPE_RN_D = 0xD, + NODE_TYPE_RN_SAM = 0xF, + /* Coherent Multichip Link (CML) node types */ + NODE_TYPE_CML_BASE = 0x100, + NODE_TYPE_CXRA = 0x100, + NODE_TYPE_CXHA = 0x101, + NODE_TYPE_CXLA = 0x102, +}; + +/* Common node header */ +struct node_header { + FWK_R uint64_t NODE_INFO; + uint8_t RESERVED0[0x80 - 0x8]; + FWK_R uint64_t CHILD_INFO; + uint8_t RESERVED1[0x100 - 0x88]; + FWK_R uint64_t CHILD_POINTER[256]; +}; + +enum sam_node_type { + SAM_NODE_TYPE_HN_F = 0, + SAM_NODE_TYPE_HN_I = 1, + SAM_NODE_TYPE_CXRA = 2, + SAM_NODE_TYPE_COUNT +}; + +/* + * Request Node System Address Map (RN-SAM) registers + */ +struct cmn_rhodes_rnsam_reg { + FWK_R uint64_t NODE_INFO; + uint8_t RESERVED0[0x80 - 0x8]; + FWK_R uint64_t CHILD_INFO; + uint8_t RESERVED1[0x900 - 0x88]; + FWK_R uint64_t UNIT_INFO; + uint8_t RESERVED2[0xC00 - 0x908]; + FWK_RW uint64_t NON_HASH_MEM_REGION[20]; + uint8_t RESERVED3[0xD80 - 0xCA0]; + FWK_RW uint64_t NON_HASH_TGT_NODEID[5]; + uint8_t RESERVED4[0xE00 - 0xDA8]; + FWK_RW uint64_t SYS_CACHE_GRP_REGION[4]; + uint8_t RESERVED5[0xEA0 - 0xE20]; + FWK_RW uint64_t SYS_CACHE_GRP_HN_COUNT; + uint8_t RESERVED6[0xF00 - 0xEA8]; + FWK_RW uint64_t SYS_CACHE_GRP_HN_NODEID[16]; + uint8_t RESERVED7[0x1000 - 0xF80]; + FWK_RW uint64_t SYS_CACHE_GRP_SN_NODEID[16]; + uint8_t RESERVED8[0x1100 - 0x1080]; + FWK_RW uint64_t STATUS; + uint8_t RESERVED9[0x1120 - 0x1108]; + FWK_RW uint64_t SYS_CACHE_GRP_CAL_MODE; +}; + +/* + * Fully Coherent Home Node (HN-F) registers + */ +struct cmn_rhodes_hnf_reg { + FWK_R uint64_t NODE_INFO; + uint8_t RESERVED0[0x80 - 0x8]; + FWK_R uint64_t CHILD_INFO; + uint8_t RESERVED1[0x900 - 0x88]; + FWK_R uint64_t UNIT_INFO; + uint8_t RESERVED2[0xD00 - 0x908]; + FWK_RW uint64_t SAM_CONTROL; + FWK_RW uint64_t SAM_MEMREGION[2]; + uint8_t RESERVED8[0x1C00 - 0xD18]; + FWK_RW uint64_t PPU_PWPR; +}; + +/* + * Configuration slave registers + */ +struct cmn_rhodes_cfgm_reg { + FWK_R uint64_t NODE_INFO; + FWK_RW uint64_t PERIPH_ID[4]; + FWK_RW uint64_t COMPONENT_ID[2]; + uint8_t RESERVED0[0x80 - 0x38]; + FWK_R uint64_t CHILD_INFO; +}; + +/* + * Crosspoint (XP) registers + */ +struct cmn_rhodes_mxp_reg { + FWK_R uint64_t NODE_INFO; + uint8_t RESERVED0[0x80 - 0x8]; + FWK_R uint64_t CHILD_INFO; + uint8_t RESERVED1[0x100 - 0x88]; + FWK_R uint64_t CHILD_POINTER[16]; +}; + +#define CMN_RHODES_NODE_INFO_TYPE UINT64_C(0x000000000000FFFF) +#define CMN_RHODES_NODE_INFO_ID UINT64_C(0x00000000FFFF0000) +#define CMN_RHODES_NODE_INFO_ID_POS 16 +#define CMN_RHODES_NODE_INFO_LOGICAL_ID UINT64_C(0x0000FFFF00000000) +#define CMN_RHODES_NODE_INFO_LOGICAL_ID_POS 32 + +#define CMN_RHODES_CHILD_INFO_COUNT UINT64_C(0x000000000000FFFF) + +#define CMN_RHODES_CHILD_POINTER_OFFSET UINT64_C(0x000000000FFFFFFF) +#define CMN_RHODES_CHILD_POINTER_EXT UINT64_C(0x0000000080000000) + +/* External child node */ +#define CMN_RHODES_CHILD_POINTER_EXT_REGISTER_OFFSET UINT64_C(0x00003FFF) +#define CMN_RHODES_CHILD_POINTER_EXT_NODE_POINTER UINT64_C(0x0FFFC000) +#define CMN_RHODES_CHILD_POINTER_EXT_NODE_POINTER_POS 14 + +/* Used by NON_HASH_MEM_REGIONx and SYS_CACHE_GRP_REGIONx group registers */ +#define CMN_RHODES_RNSAM_REGION_ENTRY_TYPE_POS 2 +#define CMN_RHODES_RNSAM_REGION_ENTRY_SIZE_POS 56 +#define CMN_RHODES_RNSAM_REGION_ENTRY_BASE_POS 26 +#define CMN_RHODES_RNSAM_REGION_ENTRY_BITS_WIDTH 64 +#define CMN_RHODES_RNSAM_REGION_ENTRY_VALID UINT64_C(0x0000000000000001) +#define CMN_RHODES_RNSAM_REGION_ENTRIES_PER_GROUP 1 +#define CMN_RHODES_RNSAM_SYS_CACHE_GRP_SN_NODEID_ENTRIES_PER_GROUP 4 +#define CMN_RHODES_RNSAM_SCG0_HNF_CAL_MODE_EN UINT64_C(0x01) + +#define CMN_RHODES_RNSAM_STATUS_UNSTALL UINT64_C(0x0000000000000002) +#define CMN_RHODES_RNSAM_STATUS_DEFAULT_NODEID_POS 48 + +#define CMN_RHODES_HNF_SAM_MEMREGION_SIZE_POS 12 +#define CMN_RHODES_HNF_SAM_MEMREGION_BASE_POS 26 +#define CMN_RHODES_HNF_SAM_MEMREGION_VALID UINT64_C(0x8000000000000000) + +#define CMN_RHODES_HNF_CACHE_GROUP_ENTRIES_MAX 64 +#define CMN_RHODES_HNF_CACHE_GROUP_ENTRIES_PER_GROUP 4 +#define CMN_RHODES_HNF_CACHE_GROUP_ENTRY_BITS_WIDTH 12 + +#define CMN_RHODES_RNSAM_NON_HASH_TGT_NODEID_ENTRY_BITS_WIDTH 12 +#define CMN_RHODES_RNSAM_NON_HASH_TGT_NODEID_ENTRY_MASK UINT64_C(0xFFF) +#define CMN_RHODES_RNSAM_NON_HASH_TGT_NODEID_ENTRIES_PER_GROUP 4 + +#define CMN_RHODES_PPU_PWPR_POLICY_OFF UINT64_C(0x0000000000000000) +#define CMN_RHODES_PPU_PWPR_POLICY_MEM_RET UINT64_C(0x0000000000000002) +#define CMN_RHODES_PPU_PWPR_POLICY_FUNC_RET UINT64_C(0x000000000000007) +#define CMN_RHODES_PPU_PWPR_POLICY_ON UINT64_C(0x0000000000000008) +#define CMN_RHODES_PPU_PWPR_OPMODE_NOSFSLC UINT64_C(0x0000000000000000) +#define CMN_RHODES_PPU_PWPR_OPMODE_SFONLY UINT64_C(0x0000000000000010) +#define CMN_RHODES_PPU_PWPR_OPMODE_HAM UINT64_C(0x0000000000000020) +#define CMN_RHODES_PPU_PWPR_OPMODE_FAM UINT64_C(0x0000000000000030) +#define CMN_RHODES_PPU_PWPR_DYN_EN UINT64_C(0x0000000000000100) + +/* Mesh and Node ID mapping */ +#define CMN_RHODES_MESH_X_MAX 8 +#define CMN_RHODES_MESH_Y_MAX 8 + +#define CMN_RHODES_NODE_ID_PORT_POS 2 +#define CMN_RHODES_NODE_ID_PORT_MASK 0x1 +#define CMN_RHODES_NODE_ID_Y_POS_OFFSET 3 +#define CMN_RHODES_NODE_ID_Y_POS 19 +#define CMN_RHODES_NODE_ID_X_POS_7_BIT 21 +#define CMN_RHODES_NODE_ID_X_POS_9_BIT 22 +#define CMN_RHODES_NODE_ID_7_BIT_MASK 3 +#define CMN_RHODES_NODE_ID_9_BIT_MASK 7 + +#define CMN_RHODES_ROOT_NODE_OFFSET_PORT_POS 16 +#define CMN_RHODES_ROOT_NODE_OFFSET_Y_POS 22 + +/* + * Retrieve the number of child nodes of a given node + * + * \param node_base Pointer to the node descriptor + * \pre The node pointer must be valid + * + * \return Number of child nodes + */ +unsigned int get_node_child_count(void *node_base); + +/* + * Retrieve node type identifier + * + * \param node_base Pointer to the node descriptor + * \pre The node pointer must be valid + * + * \return Node's type identifier + */ +enum node_type get_node_type(void *node_base); + +/* + * Retrieve the physical identifier of a node from its hardware node descriptor. + * This identifier encodes the node's position in the mesh. + * + * Note: Multiple node descriptors can share the same identifier if they are + * related to the same device node in the mesh. + * + * \param node_base Pointer to the node descriptor + * \pre The node pointer must be valid + * + * \return Node's physical identifier + */ +unsigned int get_node_id(void *node_base); + +/* + * Retrieve the logical identifier of a node from its hardware node descriptor. + * This is an unique identifier (index) among nodes of the same type in the + * system. + * + * \param node_base Pointer to the node base address + * \pre The node pointer must be valid + * + * \return An integer representing the node's logical identifier + */ +unsigned int get_node_logical_id(void *node_base); + +/* + * Retrieve a child node given a node and child index + * + * \param node_base Pointer to the node descriptor + * \pre The node pointer must be valid + * \param child_index Child index + * \pre The child index must be valid + * + * \return Pointer to the child's node descriptor + */ +void *get_child_node(uintptr_t base, void *node_base, unsigned int child_index); + +/* + * Retrieve the physical identifier of a node using its child pointer in the + * parent's node hardware descriptor + * + * This function is used to extract a node's identifier without accessing the + * node descriptor. This is specially useful for external nodes that are in an + * unavailable power or clock domain. + * + * \param node_base Pointer to the parent node descriptor + * \pre The node pointer must be valid + * \param child_index Child index + * \pre The child index must be valid + * + * \return Physical child node identifier + */ +unsigned int get_child_node_id(void *node_base, unsigned int child_index); + +/* + * Verify if a child node (given a parent node base and child index) is an + * external node from the CMN RHODES instance point of view. + * + * \param node_base Pointer to the parent node descriptor + * \pre The node pointer must be valid + * \param child_index Child index + * \pre The child index must be valid + * + * \retval true if the node is external + * \retval false if the node is internal + */ +bool is_child_external(void *node_base, unsigned int child_index); + +/* + * Convert a memory region size into a size format used by the CMN RHODES + * registers. The format is the binary logarithm of the memory region size + * represented as blocks multiple of the CMN RHODES's granularity: + * n = log2(size / SAM_GRANULARITY) + * + * \param size Memory region size to be converted + * \pre size must be a multiple of SAM_GRANULARITY + * + * \return log2(size / SAM_GRANULARITY) + */ +uint64_t sam_encode_region_size(uint64_t size); + +/* + * Configure a memory region + * + * \param reg Pointer to the region group descriptor to be configured + * \pre Must be a valid pointer + * \param region Region entry in the region group descriptor + * \param bit_offset Bit offset of the memory region in the group descriptor + * \param base Region base address + * \param size Region size + * \param node_type Type of the target node + * + * \return None + */ +void configure_region(volatile uint64_t *reg, unsigned int bit_offset, + uint64_t base, uint64_t size, enum sam_node_type node_type); + +/* + * Retrieve the node type name + * + * \param node_type Node type + * + * \return Pointer to the node type name string + */ +const char *get_node_type_name(enum node_type node_type); + +/* + * Retrieve the node's position in the mesh along the X-axis + * + * \param node_base Pointer to the node descriptor + * + * \return Zero-indexed position along the X-axis + */ +unsigned int get_node_pos_x(void *node_base); + +/* + * Retrieve the node's position in the mesh along the Y-axis + * + * \param node_base Pointer to the node descriptor + * + * \return Zero-indexed position along the Y-axis + */ +unsigned int get_node_pos_y(void *node_base); + +/* + * Get the root node descriptor based on the peripheral base, HN-D node + * identifier and mesh size. + * + * \param base CMN RHODES peripheral base address + * \param hnd_node_id HN-D node identifier containing the global configuration + * \param mesh_size_x Size of the mesh along the x-axis + * \param mesh_size_y Size of the mesh along the x-axis + * + * \return Pointer to the root node descriptor + */ +struct cmn_rhodes_cfgm_reg *get_root_node(uintptr_t base, unsigned int hnd_node_id, + unsigned int mesh_size_x, unsigned int mesh_size_y); + +#endif /* CMN_RHODES_H */ diff --git a/module/cmn_rhodes/src/mod_cmn_rhodes.c b/module/cmn_rhodes/src/mod_cmn_rhodes.c new file mode 100644 index 00000000..bd7e3dcb --- /dev/null +++ b/module/cmn_rhodes/src/mod_cmn_rhodes.c @@ -0,0 +1,591 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <string.h> +#include <fwk_assert.h> +#include <fwk_errno.h> +#include <fwk_macros.h> +#include <fwk_mm.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <fwk_notification.h> +#include <mod_clock.h> +#include <mod_cmn_rhodes.h> +#include <mod_log.h> +#include <mod_power_domain.h> +#include <cmn_rhodes.h> +#include <mod_ppu_v1.h> + +#define MOD_NAME "[CMN_RHODES] " + +/* External nodes that require RN-SAM mapping during run-time */ +struct external_rnsam_tuple { + unsigned int node_id; + struct cmn_rhodes_rnsam_reg *node; +}; + +struct cmn_rhodes_ctx { + const struct mod_cmn_rhodes_config *config; + + struct cmn_rhodes_cfgm_reg *root; + + /* Number of HN-F (system cache) nodes in the system */ + unsigned int hnf_count; + uint64_t *hnf_cache_group; + uint64_t *sn_nodeid_group; + + /* + * External RN-SAMs. The driver keeps a list of tuples (node identifier and + * node pointers). The configuration of these nodes is via the SAM API. + */ + unsigned int external_rnsam_count; + struct external_rnsam_tuple *external_rnsam_table; + + /* + * Internal RN-SAMs. The driver keeps a list of RN-SAM pointers to + * configure them once the system has been fully discovered and all + * parameters are known + */ + unsigned int internal_rnsam_count; + struct cmn_rhodes_rnsam_reg **internal_rnsam_table; + + struct mod_log_api *log_api; + + bool initialized; +} *ctx; + +static void process_node_hnf(struct cmn_rhodes_hnf_reg *hnf) +{ + unsigned int logical_id; + unsigned int node_id; + unsigned int group; + unsigned int bit_pos; + unsigned int region_idx; + unsigned int region_sub_count = 0; + const struct mod_cmn_rhodes_mem_region_map *region; + const struct mod_cmn_rhodes_config *config = ctx->config; + static unsigned int cal_mode_factor = 1; + + logical_id = get_node_logical_id(hnf); + node_id = get_node_id(hnf); + + /* + * If CAL mode is set, only even numbered hnf node should be added to the + * sys_cache_grp_hn_nodeid registers and hnf_count should be considered + * only for the even numbered hnf nodes. + */ + if (config->hnf_cal_mode == true && (node_id % 2 == 1)) { + cal_mode_factor = 2; + + /* Reduce the hnf_count for odd numbered hnf nodes */ + ctx->hnf_count--; + } + + assert(logical_id < config->snf_count); + + group = logical_id / + (CMN_RHODES_HNF_CACHE_GROUP_ENTRIES_PER_GROUP * cal_mode_factor); + bit_pos = (CMN_RHODES_HNF_CACHE_GROUP_ENTRY_BITS_WIDTH / cal_mode_factor) * + ((logical_id % + (CMN_RHODES_HNF_CACHE_GROUP_ENTRIES_PER_GROUP * + cal_mode_factor))); + + /* + * If CAL mode is set, add only even numbered hnd node to + * sys_cache_grp_hn_nodeid registers + */ + if (config->hnf_cal_mode == true && (node_id % 2 == 0)) { + ctx->hnf_cache_group[group] += ((uint64_t)get_node_id(hnf)) << bit_pos; + ctx->sn_nodeid_group[group] += + ((uint64_t)config->snf_table[logical_id]) << bit_pos; + } + + /* Set target node */ + hnf->SAM_CONTROL = config->snf_table[logical_id]; + + /* + * Map sub-regions to this HN-F node + */ + for (region_idx = 0; region_idx < config->mmap_count; region_idx++) { + region = &config->mmap_table[region_idx]; + + /* Skip non sub-regions */ + if (region->type != MOD_CMN_RHODES_REGION_TYPE_SYSCACHE_SUB) + continue; + + /* Configure sub-region entry */ + hnf->SAM_MEMREGION[region_sub_count] = region->node_id | + (sam_encode_region_size(region->size) << + CMN_RHODES_HNF_SAM_MEMREGION_SIZE_POS) | + ((region->base / SAM_GRANULARITY) << + CMN_RHODES_HNF_SAM_MEMREGION_BASE_POS) | + CMN_RHODES_HNF_SAM_MEMREGION_VALID; + + region_sub_count++; + } + + /* Configure the system cache RAM PPU */ + hnf->PPU_PWPR = CMN_RHODES_PPU_PWPR_POLICY_ON | + CMN_RHODES_PPU_PWPR_OPMODE_FAM | + CMN_RHODES_PPU_PWPR_DYN_EN; +} + +/* + * Scan the CMN_RHODES to find out: + * - Number of external RN-SAM nodes + * - Number of internal RN-SAM nodes + * - Number of HN-F nodes (cache) + */ +static void cmn_rhodes_discovery(void) +{ + unsigned int xp_count; + unsigned int xp_idx; + unsigned int node_count; + unsigned int node_idx; + struct cmn_rhodes_mxp_reg *xp; + struct node_header *node; + const struct mod_cmn_rhodes_config *config = ctx->config; + + ctx->log_api->log(MOD_LOG_GROUP_DEBUG, MOD_NAME "Starting discovery...\n"); + + assert(get_node_type(ctx->root) == NODE_TYPE_CFG); + + /* Traverse cross points (XP) */ + xp_count = get_node_child_count(ctx->root); + for (xp_idx = 0; xp_idx < xp_count; xp_idx++) { + + xp = get_child_node(config->base, ctx->root, xp_idx); + assert(get_node_type(xp) == NODE_TYPE_XP); + + ctx->log_api->log(MOD_LOG_GROUP_DEBUG, MOD_NAME "\n"); + ctx->log_api->log(MOD_LOG_GROUP_DEBUG, + MOD_NAME "XP (%d, %d) ID:%d, LID:%d\n", + get_node_pos_x(xp), + get_node_pos_y(xp), + get_node_id(xp), + get_node_logical_id(xp)); + + /* Traverse nodes */ + node_count = get_node_child_count(xp); + for (node_idx = 0; node_idx < node_count; node_idx++) { + + node = get_child_node(config->base, xp, node_idx); + + /* External nodes */ + if (is_child_external(xp, node_idx)) { + ctx->external_rnsam_count++; + ctx->log_api->log(MOD_LOG_GROUP_DEBUG, + MOD_NAME " Found external node ID:%d\n", + get_child_node_id(xp, node_idx)); + + /* Internal nodes */ + } else { + switch (get_node_type(node)) { + case NODE_TYPE_HN_F: + ctx->hnf_count++; + break; + + case NODE_TYPE_RN_SAM: + ctx->internal_rnsam_count++; + break; + + default: + /* Nothing to be done for other node types */ + break; + } + + ctx->log_api->log(MOD_LOG_GROUP_DEBUG, + MOD_NAME " %s ID:%d, LID:%d\n", + get_node_type_name(get_node_type(node)), + get_node_id(node), + get_node_logical_id(node)); + } + } + } + + ctx->log_api->log(MOD_LOG_GROUP_DEBUG, + MOD_NAME "Total internal RN-SAM nodes: %d\n" + MOD_NAME "Total external RN-SAM nodes: %d\n" + MOD_NAME "Total HN-F nodes: %d\n", + ctx->internal_rnsam_count, + ctx->external_rnsam_count, + ctx->hnf_count); +} + +static void cmn_rhodes_configure(void) +{ + unsigned int xp_count; + unsigned int xp_idx; + unsigned int node_count; + unsigned int node_idx; + unsigned int xrnsam_entry; + unsigned int irnsam_entry; + struct cmn_rhodes_mxp_reg *xp; + void *node; + const struct mod_cmn_rhodes_config *config = ctx->config; + + assert(get_node_type(ctx->root) == NODE_TYPE_CFG); + + xrnsam_entry = 0; + irnsam_entry = 0; + + /* Traverse cross points (XP) */ + xp_count = get_node_child_count(ctx->root); + for (xp_idx = 0; xp_idx < xp_count; xp_idx++) { + xp = get_child_node(config->base, ctx->root, xp_idx); + assert(get_node_type(xp) == NODE_TYPE_XP); + + /* Traverse nodes */ + node_count = get_node_child_count(xp); + for (node_idx = 0; node_idx < node_count; node_idx++) { + node = get_child_node(config->base, xp, node_idx); + + if (is_child_external(xp, node_idx)) { + unsigned int node_id = get_child_node_id(xp, node_idx); + + fwk_assert(xrnsam_entry < ctx->external_rnsam_count); + + ctx->external_rnsam_table[xrnsam_entry].node_id = node_id; + ctx->external_rnsam_table[xrnsam_entry].node = node; + + xrnsam_entry++; + } else { + enum node_type node_type = get_node_type(node); + + if (node_type == NODE_TYPE_RN_SAM) { + fwk_assert(irnsam_entry < ctx->internal_rnsam_count); + + ctx->internal_rnsam_table[irnsam_entry] = node; + + irnsam_entry++; + } else if (node_type == NODE_TYPE_HN_F) + process_node_hnf(node); + } + } + } +} + +static const char * const mmap_type_name[] = { + [MOD_CMN_RHODES_MEM_REGION_TYPE_IO] = "I/O", + [MOD_CMN_RHODES_MEM_REGION_TYPE_SYSCACHE] = "System Cache", + [MOD_CMN_RHODES_REGION_TYPE_SYSCACHE_SUB] = "Sub-System Cache", +}; + +static int cmn_rhodes_setup_sam(struct cmn_rhodes_rnsam_reg *rnsam) +{ + unsigned int region_idx; + unsigned int region_io_count = 0; + const struct mod_cmn_rhodes_mem_region_map *region; + const struct mod_cmn_rhodes_config *config = ctx->config; + unsigned int bit_pos; + unsigned int group; + unsigned int group_count; + + ctx->log_api->log(MOD_LOG_GROUP_DEBUG, + MOD_NAME "Configuring SAM for node %d\n", + get_node_id(rnsam)); + + for (region_idx = 0; region_idx < config->mmap_count; region_idx++) { + region = &config->mmap_table[region_idx]; + ctx->log_api->log(MOD_LOG_GROUP_DEBUG, + MOD_NAME " [0x%lx - 0x%lx] %s\n", + region->base, + region->base + region->size - 1, + mmap_type_name[region->type]); + + group = region_io_count / CMN_RHODES_RNSAM_REGION_ENTRIES_PER_GROUP; + bit_pos = (region_io_count % + CMN_RHODES_RNSAM_REGION_ENTRIES_PER_GROUP) * + CMN_RHODES_RNSAM_REGION_ENTRY_BITS_WIDTH; + + switch (region->type) { + case MOD_CMN_RHODES_MEM_REGION_TYPE_IO: + /* + * Configure memory region + */ + configure_region(&rnsam->NON_HASH_MEM_REGION[group], + bit_pos, + region->base, + region->size, + SAM_NODE_TYPE_HN_I); + + /* + * Configure target node + */ + group = region_io_count / + CMN_RHODES_RNSAM_NON_HASH_TGT_NODEID_ENTRIES_PER_GROUP; + bit_pos = CMN_RHODES_RNSAM_NON_HASH_TGT_NODEID_ENTRY_BITS_WIDTH * + (region_io_count % + CMN_RHODES_RNSAM_NON_HASH_TGT_NODEID_ENTRIES_PER_GROUP); + + rnsam->NON_HASH_TGT_NODEID[group] &= + ~(CMN_RHODES_RNSAM_NON_HASH_TGT_NODEID_ENTRY_MASK << bit_pos); + rnsam->NON_HASH_TGT_NODEID[group] |= (region->node_id & + CMN_RHODES_RNSAM_NON_HASH_TGT_NODEID_ENTRY_MASK) << bit_pos; + + region_io_count++; + break; + + case MOD_CMN_RHODES_MEM_REGION_TYPE_SYSCACHE: + /* + * Configure memory region + */ + configure_region(&rnsam->SYS_CACHE_GRP_REGION[group], + bit_pos, + region->base, + region->size, + SAM_NODE_TYPE_HN_F); + break; + + case MOD_CMN_RHODES_REGION_TYPE_SYSCACHE_SUB: + /* Do nothing. System cache sub-regions are handled by HN-Fs */ + break; + + default: + assert(false); + return FWK_E_DATA; + } + } + + group_count = ctx->hnf_count / CMN_RHODES_HNF_CACHE_GROUP_ENTRIES_PER_GROUP; + for (group = 0; group < group_count; group++) + rnsam->SYS_CACHE_GRP_HN_NODEID[group] = ctx->hnf_cache_group[group]; + + /* Program the number of HNFs */ + rnsam->SYS_CACHE_GRP_HN_COUNT = ctx->hnf_count; + + /*TODO + * CAL_MODE is currently hardcoded to sys_cache_group0 as + * config_cmn_rhodes.c supports only one sys_cache_group (sys_cache_group0). + * Handle cases where config_cmn_rhodes.c can handle more than one + * sys_cache_group + */ + rnsam->SYS_CACHE_GRP_CAL_MODE = (uint64_t)config->hnf_cal_mode * + (CMN_RHODES_RNSAM_SCG0_HNF_CAL_MODE_EN); + + /* Program the SYS_CACHE_GRP_SN_NODEID register for PrefetchTgt */ + if (config->hnf_cal_mode) + group_count = config->snf_count/ + (CMN_RHODES_RNSAM_SYS_CACHE_GRP_SN_NODEID_ENTRIES_PER_GROUP * 2); + else + group_count = config->snf_count/ + CMN_RHODES_RNSAM_SYS_CACHE_GRP_SN_NODEID_ENTRIES_PER_GROUP; + + for (group = 0; group < group_count; group++) + rnsam->SYS_CACHE_GRP_SN_NODEID[group] = ctx->sn_nodeid_group[group]; + + /* Enable RNSAM */ + rnsam->STATUS = ((uint64_t)config->hnd_node_id << + CMN_RHODES_RNSAM_STATUS_DEFAULT_NODEID_POS) | + CMN_RHODES_RNSAM_STATUS_UNSTALL; + __sync_synchronize(); + + return FWK_SUCCESS; +} + +static int cmn_rhodes_setup(void) +{ + unsigned int rnsam_idx; + + if (!ctx->initialized) { + cmn_rhodes_discovery(); + + /* + * Allocate resources based on the discovery + */ + + /* Pointers for the internal RN-SAM nodes */ + if (ctx->internal_rnsam_count != 0) { + ctx->internal_rnsam_table = fwk_mm_calloc( + ctx->internal_rnsam_count, sizeof(*ctx->internal_rnsam_table)); + if (ctx->internal_rnsam_table == NULL) + return FWK_E_NOMEM; + } + + /* Tuples for the external RN-RAM nodes (including their node IDs) */ + if (ctx->external_rnsam_count != 0) { + ctx->external_rnsam_table = fwk_mm_calloc( + ctx->external_rnsam_count, sizeof(*ctx->external_rnsam_table)); + if (ctx->external_rnsam_table == NULL) + return FWK_E_NOMEM; + } + + /* Cache groups */ + if (ctx->hnf_count != 0) { + /* + * Allocate enough group descriptors to accommodate all expected + * HN-F nodes in the system. + */ + ctx->hnf_cache_group = fwk_mm_calloc( + ctx->hnf_count / CMN_RHODES_HNF_CACHE_GROUP_ENTRIES_PER_GROUP, + sizeof(*ctx->hnf_cache_group)); + if (ctx->hnf_cache_group == NULL) + return FWK_E_NOMEM; + ctx->sn_nodeid_group = fwk_mm_calloc( + ctx->hnf_count / + CMN_RHODES_RNSAM_SYS_CACHE_GRP_SN_NODEID_ENTRIES_PER_GROUP, + sizeof(*ctx->sn_nodeid_group)); + if (ctx->sn_nodeid_group == NULL) + return FWK_E_NOMEM; + } + } + + cmn_rhodes_configure(); + + /* Setup internal RN-SAM nodes */ + for (rnsam_idx = 0; rnsam_idx < ctx->internal_rnsam_count; rnsam_idx++) + cmn_rhodes_setup_sam(ctx->internal_rnsam_table[rnsam_idx]); + + ctx->log_api->log(MOD_LOG_GROUP_DEBUG, MOD_NAME "Done\n"); + + ctx->initialized = true; + + return FWK_SUCCESS; +} + +static int cmn_rhodes_setup_rnsam(unsigned int node_id) +{ + int status; + unsigned int node_idx; + + status = fwk_module_check_call(FWK_ID_MODULE(FWK_MODULE_IDX_CMN_RHODES)); + if (status != FWK_SUCCESS) + return status; + + for (node_idx = 0; node_idx < ctx->external_rnsam_count; node_idx++) { + if (ctx->external_rnsam_table[node_idx].node_id == node_id) { + cmn_rhodes_setup_sam(ctx->external_rnsam_table[node_idx].node); + return FWK_SUCCESS; + } + } + + return FWK_E_PARAM; +} + +/* + * PPUv1 State Observer API + */ + +static void post_ppu_on(void *data) +{ + assert(data != NULL); + cmn_rhodes_setup_rnsam(*(unsigned int *)data); +} + +static const struct mod_ppu_v1_power_state_observer_api +cmn_rhodes_observer_api = { + .post_ppu_on = post_ppu_on, +}; + +/* + * Framework handlers + */ + +static int cmn_rhodes_init(fwk_id_t module_id, unsigned int element_count, + const void *data) +{ + const struct mod_cmn_rhodes_config *config = data; + + /* No elements support */ + if (element_count > 0) + return FWK_E_DATA; + + /* Allocate space for the context */ + ctx = fwk_mm_calloc(1, sizeof(*ctx)); + if (ctx == NULL) + return FWK_E_NOMEM; + + if (config->base == 0) + return FWK_E_DATA; + + if ((config->mesh_size_x == 0) || (config->mesh_size_x > + CMN_RHODES_MESH_X_MAX)) + return FWK_E_DATA; + + if ((config->mesh_size_y == 0) || (config->mesh_size_y > + CMN_RHODES_MESH_Y_MAX)) + return FWK_E_DATA; + + if (config->snf_count > CMN_RHODES_HNF_CACHE_GROUP_ENTRIES_MAX) + return FWK_E_DATA; + + ctx->root = get_root_node(config->base, config->hnd_node_id, + config->mesh_size_x, config->mesh_size_y); + + ctx->config = config; + + return FWK_SUCCESS; +} + +static int cmn_rhodes_bind(fwk_id_t id, unsigned int round) +{ + int status; + + /* Use second round only (round numbering is zero-indexed) */ + if (round == 1) { + + /* Bind to the log component */ + status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_LOG), + FWK_ID_API(FWK_MODULE_IDX_LOG, 0), + &ctx->log_api); + + if (status != FWK_SUCCESS) + return FWK_E_PANIC; + } + + return FWK_SUCCESS; +} + +static int cmn_rhodes_process_bind_request(fwk_id_t requester_id, + fwk_id_t target_id, fwk_id_t api_id, const void **api) +{ + *api = &cmn_rhodes_observer_api; + return FWK_SUCCESS; +} + +int cmn_rhodes_start(fwk_id_t id) +{ + if (fwk_id_is_equal(ctx->config->clock_id, FWK_ID_NONE)) { + cmn_rhodes_setup(); + return FWK_SUCCESS; + } + + /* Register the module for clock state notifications */ + return fwk_notification_subscribe( + mod_clock_notification_id_state_changed, + ctx->config->clock_id, + id); +} + +static int cmn_rhodes_process_notification( + const struct fwk_event *event, + struct fwk_event *resp_event) +{ + struct clock_notification_params *params; + + assert(fwk_id_is_equal(event->id, mod_clock_notification_id_state_changed)); + assert(fwk_id_is_type(event->target_id, FWK_ID_TYPE_MODULE)); + + params = (struct clock_notification_params *)event->params; + + if (params->new_state == MOD_CLOCK_STATE_RUNNING) + cmn_rhodes_setup(); + + return FWK_SUCCESS; +} + +const struct fwk_module module_cmn_rhodes = { + .name = "CMN_RHODES", + .type = FWK_MODULE_TYPE_DRIVER, + .api_count = MOD_CMN_RHODES_API_COUNT, + .init = cmn_rhodes_init, + .bind = cmn_rhodes_bind, + .start = cmn_rhodes_start, + .process_bind_request = cmn_rhodes_process_bind_request, + .process_notification = cmn_rhodes_process_notification, +}; diff --git a/module/ppu_v1/include/mod_ppu_v1.h b/module/ppu_v1/include/mod_ppu_v1.h index 02174202..e9389823 100644 --- a/module/ppu_v1/include/mod_ppu_v1.h +++ b/module/ppu_v1/include/mod_ppu_v1.h @@ -111,6 +111,12 @@ struct mod_ppu_v1_pd_config { * \ref mod_ppu_v1_power_state_observer_api::post_ppu_on(). */ void *post_ppu_on_param; + + /*! + * Flag indicating if cluster power domain supported + * default value: False and cluster power domain exist + */ + bool no_cluter_power_domain; }; /*! diff --git a/module/ppu_v1/src/mod_ppu_v1.c b/module/ppu_v1/src/mod_ppu_v1.c index 116c22a5..9a8f717d 100644 --- a/module/ppu_v1/src/mod_ppu_v1.c +++ b/module/ppu_v1/src/mod_ppu_v1.c @@ -457,13 +457,15 @@ static void cluster_on(struct ppu_v1_pd_ctx *pd_ctx) assert(pd_ctx != NULL); - ppu = pd_ctx->ppu; + if (!pd_ctx->config->no_cluter_power_domain) { + ppu = pd_ctx->ppu; - ppu_v1_set_input_edge_sensitivity(ppu, - PPU_V1_MODE_ON, - PPU_V1_EDGE_SENSITIVITY_MASKED); + ppu_v1_set_input_edge_sensitivity(ppu, + PPU_V1_MODE_ON, + PPU_V1_EDGE_SENSITIVITY_MASKED); - ppu_v1_set_power_mode(ppu, PPU_V1_MODE_ON); + ppu_v1_set_power_mode(ppu, PPU_V1_MODE_ON); + } status = pd_ctx->pd_driver_input_api->report_power_state_transition( pd_ctx->bound_id, MOD_PD_STATE_ON); assert(status == FWK_SUCCESS); @@ -518,11 +520,13 @@ static int ppu_v1_cluster_pd_set_state(fwk_id_t cluster_pd_id, switch (state) { case MOD_PD_STATE_ON: cluster_on(pd_ctx); - #ifdef BUILD_HAS_MULTITHREADING - ppu_v1_set_input_edge_sensitivity(ppu, - PPU_V1_MODE_ON, - PPU_V1_EDGE_SENSITIVITY_FALLING_EDGE); - #endif + if (!pd_ctx->config->no_cluter_power_domain) { + #ifdef BUILD_HAS_MULTITHREADING + ppu_v1_set_input_edge_sensitivity(ppu, + PPU_V1_MODE_ON, + PPU_V1_EDGE_SENSITIVITY_FALLING_EDGE); + #endif + } return FWK_SUCCESS; case MOD_PD_STATE_OFF: @@ -620,7 +624,8 @@ static void ppu_interrupt_handler(uintptr_t pd_ctx_param) if (pd_ctx->config->pd_type == MOD_PD_TYPE_CORE) core_pd_ppu_interrupt_handler(pd_ctx); else - cluster_pd_ppu_interrupt_handler(pd_ctx); + if (!pd_ctx->config->no_cluter_power_domain) + cluster_pd_ppu_interrupt_handler(pd_ctx); } static void ppu_isr_api_interrupt_handler(fwk_id_t pd_id) @@ -927,10 +932,15 @@ static int ppu_v1_start(fwk_id_t id) switch (pd_ctx->config->pd_type) { case MOD_PD_TYPE_CORE: - case MOD_PD_TYPE_CLUSTER: fwk_interrupt_clear_pending(pd_ctx->config->ppu.irq); fwk_interrupt_enable(pd_ctx->config->ppu.irq); break; + case MOD_PD_TYPE_CLUSTER: + if (!pd_ctx->config->no_cluter_power_domain) { + fwk_interrupt_clear_pending(pd_ctx->config->ppu.irq); + fwk_interrupt_enable(pd_ctx->config->ppu.irq); + break; + } default: /* Nothing to be done for other types */ break; @@ -969,7 +979,10 @@ static int ppu_v1_process_notification( return ppu_v1_core_pd_init(pd_ctx); case MOD_PD_TYPE_CLUSTER: - return ppu_v1_cluster_pd_init(pd_ctx); + if (pd_ctx->config->no_cluter_power_domain) + return FWK_SUCCESS; + else + return ppu_v1_cluster_pd_init(pd_ctx); default: ppu_v1_init(pd_ctx->ppu); diff --git a/module/system_pll/include/mod_system_pll.h b/module/system_pll/include/mod_system_pll.h index 1130e0bc..3e5732e3 100644 --- a/module/system_pll/include/mod_system_pll.h +++ b/module/system_pll/include/mod_system_pll.h @@ -50,7 +50,7 @@ struct mod_system_pll_dev_config { * Mask for the bit within the status register that indicates whether the * PLL has locked at the programmed rate. */ - const uint8_t lock_flag_mask; + const uint32_t lock_flag_mask; /*! The initial rate the PLL is set to during initialization. */ const uint64_t initial_rate; diff --git a/product/rddaniel/include/fmw_cmsis.h b/product/rddaniel/include/fmw_cmsis.h new file mode 100644 index 00000000..f904b953 --- /dev/null +++ b/product/rddaniel/include/fmw_cmsis.h @@ -0,0 +1,34 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#define __CHECK_DEVICE_DEFINES +#define __CM7_REV 0x0000U +#define __FPU_PRESENT 0U +#define __MPU_PRESENT 1U +#define __ICACHE_PRESENT 0U +#define __DCACHE_PRESENT 0U +#define __DTCM_PRESENT 0U +#define __NVIC_PRIO_BITS 3U +#define __Vendor_SysTickConfig 0U + +typedef enum IRQn { + NonMaskableInt_IRQn = -14, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, +} IRQn_Type; + +#include <core_cm7.h> + +#endif /* FMW_CMSIS_H */ diff --git a/product/rddaniel/include/mcp_rddaniel_irq.h b/product/rddaniel/include/mcp_rddaniel_irq.h new file mode 100644 index 00000000..adca62a7 --- /dev/null +++ b/product/rddaniel/include/mcp_rddaniel_irq.h @@ -0,0 +1,266 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MCP_RDDANIEL_IRQ_H +#define MCP_RDDANIEL_IRQ_H + +#include <fwk_interrupt.h> + +#define MCP_WDOG_IRQ FWK_INTERRUPT_NMI /* MCP Watchdog (SP805) */ + +enum mcp_rddaniel_interrupt { + RESERVED0_IRQ = 0, /* Reserved */ + CDBG_PWR_UP_REQ_IRQ = 1, /* Coresight Debug Power Request */ + CSYS_PWR_UP_REQ_IRQ = 2, /* Coresight System Power Request */ + CDBG_RST_REQ_IRQ = 3, /* Coresight Debug Reset Request */ + GIC_EXT_WAKEUP_IRQ = 4, /* External GIC Wakeup Request */ + RESERVED5_IRQ = 5, /* Reserved */ + RESERVED6_IRQ = 6, /* Reserved */ + RESERVED7_IRQ = 7, /* Reserved */ + RESERVED8_IRQ = 8, /* Reserved */ + RESERVED9_IRQ = 9, /* Reserved */ + RESERVED10_IRQ = 10, /* Reserved */ + RESERVED11_IRQ = 11, /* Reserved */ + RESERVED12_IRQ = 12, /* Reserved */ + RESERVED13_IRQ = 13, /* Reserved */ + RESERVED14_IRQ = 14, /* Reserved */ + RESERVED15_IRQ = 15, /* Reserved */ + SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */ + SOC_WAKEUP1_IRQ = 17, /* SoC Expansion Wakeup */ + SOC_WAKEUP2_IRQ = 18, /* SoC Expansion Wakeup */ + SOC_WAKEUP3_IRQ = 19, /* SoC Expansion Wakeup */ + SOC_WAKEUP4_IRQ = 20, /* SoC Expansion Wakeup */ + SOC_WAKEUP5_IRQ = 21, /* SoC Expansion Wakeup */ + SOC_WAKEUP6_IRQ = 22, /* SoC Expansion Wakeup */ + SOC_WAKEUP7_IRQ = 23, /* SoC Expansion Wakeup */ + SOC_WAKEUP8_IRQ = 24, /* SoC Expansion Wakeup */ + SOC_WAKEUP9_IRQ = 25, /* SoC Expansion Wakeup */ + SOC_WAKEUP10_IRQ = 26, /* SoC Expansion Wakeup */ + SOC_WAKEUP11_IRQ = 27, /* SoC Expansion Wakeup */ + SOC_WAKEUP12_IRQ = 28, /* SoC Expansion Wakeup */ + SOC_WAKEUP13_IRQ = 29, /* SoC Expansion Wakeup */ + SOC_WAKEUP14_IRQ = 30, /* SoC Expansion Wakeup */ + SOC_WAKEUP15_IRQ = 31, /* SoC Expansion Wakeup */ + MCP_PIK_IRQ = 32, /* Power Intergration Kit Interrupt */ + TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ + MHU_AP_NONSEC_IRQ = 34, /* MHU Non-Secure IRQ between MCP and AP */ + RESERVED35_IRQ = 35, /* Reserved */ + MHU_AP_SEC_IRQ = 36, /* MHU Secure IRQ between MCP and AP */ + CTI_TRIGGER0_IRQ = 37, /* MCP CTI Trigger */ + CTI_TRIGGER1_IRQ = 38, /* MCP CTI Trigger */ + RESERVED39_IRQ = 39, /* Reserved */ + RESERVED40_IRQ = 40, /* Reserved */ + RESERVED41_IRQ = 41, /* Reserved */ + MCP_UART0_INT_IRQ = 42, /* Always-on UART interrupt */ + MCP_UART1_INT_IRQ = 43, /* Always-on UART interrupt */ + RESERVED44_IRQ = 44, /* Reserved */ + RESERVED45_IRQ = 45, /* Reserved */ + RESERVED46_IRQ = 46, /* Reserved */ + RESERVED47_IRQ = 47, /* Reserved */ + RESERVED48_IRQ = 48, /* Reserved */ + RESERVED49_IRQ = 49, /* Reserved */ + RESERVED50_IRQ = 50, /* Reserved */ + RESERVED51_IRQ = 51, /* Reserved */ + RESERVED52_IRQ = 52, /* Reserved */ + RESERVED53_IRQ = 53, /* Reserved */ + RESERVED54_IRQ = 54, /* Reserved */ + RESERVED55_IRQ = 55, /* Reserved */ + RESERVED56_IRQ = 56, /* Reserved */ + RESERVED57_IRQ = 57, /* Reserved */ + RESERVED58_IRQ = 58, /* Reserved */ + RESERVED59_IRQ = 59, /* Reserved */ + RESERVED60_IRQ = 60, /* Reserved */ + RESERVED61_IRQ = 61, /* Reserved */ + RESERVED62_IRQ = 62, /* Reserved */ + RESERVED63_IRQ = 63, /* Reserved */ + RESERVED64_IRQ = 64, /* Reserved */ + RESERVED65_IRQ = 65, /* Reserved */ + RESERVED66_IRQ = 66, /* Reserved */ + RESERVED67_IRQ = 67, /* Reserved */ + RESERVED68_IRQ = 68, /* Reserved */ + RESERVED69_IRQ = 69, /* Reserved */ + RESERVED70_IRQ = 70, /* Reserved */ + RESERVED71_IRQ = 71, /* Reserved */ + RESERVED72_IRQ = 72, /* Reserved */ + RESERVED73_IRQ = 73, /* Reserved */ + RESERVED74_IRQ = 74, /* Reserved */ + RESERVED75_IRQ = 75, /* Reserved */ + RESERVED76_IRQ = 76, /* Reserved */ + RESERVED77_IRQ = 77, /* Reserved */ + RESERVED78_IRQ = 78, /* Reserved */ + RESERVED79_IRQ = 79, /* Reserved */ + RESERVED80_IRQ = 80, /* Reserved */ + RESERVED81_IRQ = 81, /* Reserved */ + RESERVED82_IRQ = 82, /* Reserved */ + RESERVED83_IRQ = 83, /* Reserved */ + MHU_SCP_NONSEC_IRQ = 84, /* MHU Non-Sec IRQ between SCP and MCP */ + MHU_SCP_SEC_IRQ = 85, /* MHU Secure IRQ between SCP and MCP */ + RESERVED86_IRQ = 86, /* Reserved */ + RESERVED87_IRQ = 87, /* Reserved */ + RESERVED88_IRQ = 88, /* Reserved */ + RESERVED89_IRQ = 89, /* Reserved */ + RESERVED90_IRQ = 90, /* Reserved */ + RESERVED91_IRQ = 91, /* Reserved */ + RESERVED92_IRQ = 92, /* Reserved */ + RESERVED93_IRQ = 93, /* Reserved */ + MMU_TCU_RASIRPT_IRQ = 94, /* Consolidated MMU RAS */ + MMU_TBU_RASIRPT_IRQ = 95, /* Consolidated TBU RAS */ + INT_PPU_IRQ = 96, /* PPU interrupt from Interconnect PPU */ + INT_ERRNS_IRQ = 97, /* Non-Sec error interrupt from + Interconnect PPU */ + INT_ERRS_IRQ = 98, /* Secure error interrupt from + Interconnect PPU */ + INT_FAULTS_IRQ = 99, /* Secure fault interrupt from + Interconnect PPU */ + INT_FAULTNS_IRQ = 100, /* Non-Sec fault interrupt from + Interconnect PPU */ + INT_PMU_IRQ = 101, /* PMU count overflow interrupt */ + RESERVED102_IRQ = 102, /* Reserved */ + RESERVED103_IRQ = 103, /* Reserved */ + RESERVED104_IRQ = 104, /* Reserved */ + RESERVED105_IRQ = 105, /* Reserved */ + RESERVED106_IRQ = 106, /* Reserved */ + RESERVED107_IRQ = 107, /* Reserved */ + RESERVED108_IRQ = 108, /* Reserved */ + RESERVED109_IRQ = 109, /* Reserved */ + RESERVED110_IRQ = 110, /* Reserved */ + RESERVED111_IRQ = 111, /* Reserved */ + RESERVED112_IRQ = 112, /* Reserved */ + RESERVED113_IRQ = 113, /* Reserved */ + RESERVED114_IRQ = 114, /* Reserved */ + RESERVED115_IRQ = 115, /* Reserved */ + RESERVED116_IRQ = 116, /* Reserved */ + RESERVED117_IRQ = 117, /* Reserved */ + RESERVED118_IRQ = 118, /* Reserved */ + RESERVED119_IRQ = 119, /* Reserved */ + RESERVED120_IRQ = 120, /* Reserved */ + RESERVED121_IRQ = 121, /* Reserved */ + RESERVED122_IRQ = 122, /* Reserved */ + RESERVED123_IRQ = 123, /* Reserved */ + RESERVED124_IRQ = 124, /* Reserved */ + RESERVED125_IRQ = 125, /* Reserved */ + RESERVED126_IRQ = 126, /* Reserved */ + RESERVED127_IRQ = 127, /* Reserved */ + RESERVED128_IRQ = 128, /* Reserved */ + RESERVED129_IRQ = 129, /* Reserved */ + RESERVED130_IRQ = 130, /* Reserved */ + RESERVED131_IRQ = 131, /* Reserved */ + RESERVED132_IRQ = 132, /* Reserved */ + RESERVED133_IRQ = 133, /* Reserved */ + RESERVED134_IRQ = 134, /* Reserved */ + RESERVED135_IRQ = 135, /* Reserved */ + RESERVED136_IRQ = 136, /* Reserved */ + RESERVED137_IRQ = 137, /* Reserved */ + RESERVED138_IRQ = 138, /* Reserved */ + MCP_WD_WS1_IRQ = 139, /* MCP watchdog reset */ + RESERVED140_IRQ = 140, /* Reserved */ + RESERVED141_IRQ = 141, /* Reserved */ + RESERVED142_IRQ = 142, /* Reserved */ + RESERVED143_IRQ = 143, /* Reserved */ + RESERVED144_IRQ = 144, /* Reserved */ + RESERVED145_IRQ = 145, /* Reserved */ + RESERVED146_IRQ = 146, /* Reserved */ + RESERVED147_IRQ = 147, /* Reserved */ + RESERVED148_IRQ = 148, /* Reserved */ + RESERVED149_IRQ = 149, /* Reserved */ + RESERVED150_IRQ = 150, /* Reserved */ + RESERVED151_IRQ = 151, /* Reserved */ + RESERVED152_IRQ = 152, /* Reserved */ + RESERVED153_IRQ = 153, /* Reserved */ + RESERVED154_IRQ = 154, /* Reserved */ + RESERVED155_IRQ = 155, /* Reserved */ + RESERVED156_IRQ = 156, /* Reserved */ + RESERVED157_IRQ = 157, /* Reserved */ + RESERVED158_IRQ = 158, /* Reserved */ + RESERVED159_IRQ = 159, /* Reserved */ + RESERVED160_IRQ = 160, /* Reserved */ + RESERVED161_IRQ = 161, /* Reserved */ + RESERVED162_IRQ = 162, /* Reserved */ + RESERVED163_IRQ = 163, /* Reserved */ + RESERVED164_IRQ = 164, /* Reserved */ + RESERVED165_IRQ = 165, /* Reserved */ + RESERVED166_IRQ = 166, /* Reserved */ + RESERVED167_IRQ = 167, /* Reserved */ + RESERVED168_IRQ = 168, /* Reserved */ + RESERVED169_IRQ = 169, /* Reserved */ + RESERVED170_IRQ = 170, /* Reserved */ + RESERVED171_IRQ = 171, /* Reserved */ + RESERVED172_IRQ = 172, /* Reserved */ + RESERVED173_IRQ = 173, /* Reserved */ + RESERVED174_IRQ = 174, /* Reserved */ + RESERVED175_IRQ = 175, /* Reserved */ + RESERVED176_IRQ = 176, /* Reserved */ + RESERVED177_IRQ = 177, /* Reserved */ + RESERVED178_IRQ = 178, /* Reserved */ + RESERVED179_IRQ = 179, /* Reserved */ + DMCS0_MISC_OFLOW_IRQ = 180, /* DMC 0/4 Combined Error Overflow */ + DMCS0_ERR_OFLOW_IRQ = 181, /* DMC 0/4 Error Overflow */ + DMCS0_ECC_ERR_INT_IRQ = 182, /* DMC 0/4 ECC Error Int */ + DMCS0_MISC_ACCESS_INT_IRQ = 183, /* DMC 0/4 Combined Miscellaneous + access int */ + DMCS0_TEMPERATURE_EVENT_INT_IRQ = 184, /* DMC 0/4 Temperature event int */ + DMCS0_FAILED_ACCESS_INT_IRQ = 185, /* DMC 0/4 Failed access int */ + DMCS0_MGR_INT_IRQ = 186, /* DMC 0/4 combined manager int */ + DMCS1_MISC_OFLOW_IRQ = 187, /* DMC 1/5 Combined Error Overflow */ + DMCS1_ERR_OFLOW_IRQ = 188, /* DMC 1/5 Error Overflow */ + DMCS1_ECC_ERR_INT_IRQ = 189, /* DMC 1/5 ECC Error Int */ + DMCS1_MISC_ACCESS_INT_IRQ = 190, /* DMC 1/5 Combined Miscellaneous + access int */ + DMCS1_TEMPERATURE_EVENT_INT_IRQ = 191, /* DMC 1/5 Temperature event int */ + DMCS1_FAILED_ACCESS_INT_IRQ = 192, /* DMC 1/5 Failed access int */ + DMCS1_MGR_INT_IRQ = 193, /* DMC 1/5 combined manager int */ + DMCS2_MISC_OFLOW_IRQ = 194, /* DMC 2/6 Combined Error Overflow */ + DMCS2_ERR_OFLOW_IRQ = 195, /* DMC 2/6 Error Overflow */ + DMCS2_ECC_ERR_INT_IRQ = 196, /* DMC 2/6 ECC Error Int */ + DMCS2_MISC_ACCESS_INT_IRQ = 197, /* DMC 2/6 Combined Miscellaneous + access int */ + DMCS2_TEMPERATURE_EVENT_INT_IRQ = 198, /* DMC 2/6 Temperature event int */ + DMCS2_FAILED_ACCESS_INT_IRQ = 199, /* DMC 2/6 Failed access int */ + DMCS2_MGR_INT_IRQ = 200, /* DMC 2/6 combined manager int */ + DMCS3_MISC_OFLOW_IRQ = 201, /* DMC 3/7 Combined Error Overflow */ + DMCS3_ERR_OFLOW_IRQ = 202, /* DMC 3/7 Error Overflow */ + DMCS3_ECC_ERR_INT_IRQ = 203, /* DMC 3/7 ECC Error Int */ + DMCS3_MISC_ACCESS_INT_IRQ = 204, /* DMC 3/7 Combined Miscellaneous + access int */ + DMCS3_TEMPERATURE_EVENT_INT_IRQ = 205, /* DMC 3/7 Temperature event int */ + DMCS3_FAILED_ACCESS_INT_IRQ = 206, /* DMC 3/7 Failed access int */ + DMCS3_MGR_INT_IRQ = 207, /* DMC 3/7 combined manager int */ + MCP_EXT_INTR0_IRQ = 208, /* MCP Customer Extension */ + MCP_EXT_INTR1_IRQ = 209, /* MCP Customer Extension */ + MCP_EXT_INTR2_IRQ = 210, /* MCP Customer Extension */ + MCP_EXT_INTR3_IRQ = 211, /* MCP Customer Extension */ + MCP_EXT_INTR4_IRQ = 212, /* MCP Customer Extension */ + MCP_EXT_INTR5_IRQ = 213, /* MCP Customer Extension */ + MCP_EXT_INTR6_IRQ = 214, /* MCP Customer Extension */ + MCP_EXT_INTR7_IRQ = 215, /* MCP Customer Extension */ + MCP_EXT_INTR8_IRQ = 216, /* MCP Customer Extension */ + MCP_EXT_INTR9_IRQ = 217, /* MCP Customer Extension */ + MCP_EXT_INTR10_IRQ = 218, /* MCP Customer Extension */ + MCP_EXT_INTR11_IRQ = 219, /* MCP Customer Extension */ + MCP_EXT_INTR12_IRQ = 220, /* MCP Customer Extension */ + MCP_EXT_INTR13_IRQ = 221, /* MCP Customer Extension */ + MCP_EXT_INTR14_IRQ = 222, /* MCP Customer Extension */ + MCP_EXT_INTR15_IRQ = 223, /* MCP Customer Extension */ + MCP_EXT_INTR16_IRQ = 224, /* MCP Customer Extension */ + MCP_EXT_INTR17_IRQ = 225, /* MCP Customer Extension */ + MCP_EXT_INTR18_IRQ = 226, /* MCP Customer Extension */ + MCP_EXT_INTR19_IRQ = 227, /* MCP Customer Extension */ + MCP_EXT_INTR20_IRQ = 228, /* MCP Customer Extension */ + MCP_EXT_INTR21_IRQ = 229, /* MCP Customer Extension */ + MCP_EXT_INTR22_IRQ = 230, /* MCP Customer Extension */ + MCP_EXT_INTR23_IRQ = 231, /* MCP Customer Extension */ + MCP_EXT_INTR24_IRQ = 232, /* MCP Customer Extension */ + MCP_EXT_INTR25_IRQ = 233, /* MCP Customer Extension */ + MCP_EXT_INTR26_IRQ = 234, /* MCP Customer Extension */ + MCP_EXT_INTR27_IRQ = 235, /* MCP Customer Extension */ + MCP_EXT_INTR28_IRQ = 236, /* MCP Customer Extension */ + MCP_EXT_INTR29_IRQ = 237, /* MCP Customer Extension */ + MCP_EXT_INTR30_IRQ = 238, /* MCP Customer Extension */ + MCP_EXT_INTR31_IRQ = 239 /* MCP Customer Extension */ +}; + +#endif /* MCP_RDDANIEL_IRQ_H */ diff --git a/product/rddaniel/include/mcp_rddaniel_mmap.h b/product/rddaniel/include/mcp_rddaniel_mmap.h new file mode 100644 index 00000000..bc122d3e --- /dev/null +++ b/product/rddaniel/include/mcp_rddaniel_mmap.h @@ -0,0 +1,50 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MCP_RDDANIEL_MMAP_H +#define MCP_RDDANIEL_MMAP_H + +#include <stdint.h> + +/* + * Top-level base addresses + */ +#define MCP_SOC_EXPANSION1_BASE UINT32_C(0x01000000) +#define MCP_SOC_EXPANSION2_BASE UINT32_C(0x21000000) +#define MCP_SOC_EXPANSION3_BASE UINT32_C(0x40000000) +#define MCP_MHU_SCP_BASE UINT32_C(0x45600000) +#define MCP_SOC_EXPANSION4_BASE UINT32_C(0x48000000) +#define MCP_PERIPH_BASE UINT32_C(0x4C000000) +#define MCP_MEMORY_CONTROLLER UINT32_C(0x4E000000) +#define MCP_POWER_PERIPH_BASE UINT32_C(0x50000000) +#define MCP_SYS0_BASE UINT32_C(0x60000000) +#define MCP_SYS1_BASE UINT32_C(0xA0000000) +#define MCP_PPB_BASE_INTERNAL UINT32_C(0xE0000000) +#define MCP_PPB_BASE_EXTERNAL UINT32_C(0xE0040000) + +/* + * Peripherals + */ +#define MCP_REFCLK_CNTCTL_BASE (MCP_PERIPH_BASE) +#define MCP_REFCLK_CNTBASE0_BASE (MCP_PERIPH_BASE + 0x1000) +#define MCP_UART0_BASE (MCP_PERIPH_BASE + 0x2000) +#define MCP_UART1_BASE (MCP_PERIPH_BASE + 0x3000) +#define MCP_WDOG_BASE (MCP_PERIPH_BASE + 0x6000) +#define MCP_MHU_AP_BASE (MCP_PERIPH_BASE + 0x400000) + +/* + * Power control peripherals + */ +#define MCP_PIK_BASE (MCP_POWER_PERIPH_BASE) + +/* + * Base addresses of MHU devices v2 + */ +#define MCP_MHU_MCP_SCP_SND (MCP_MHU_SCP_BASE + 0x00000) +#define MCP_MHU_MCP_SCP_RCV (MCP_MHU_SCP_BASE + 0x10000) + +#endif /* MCP_RDDANIEL_MMAP_H */ diff --git a/product/rddaniel/include/mcp_rddaniel_mmap_mcp.h b/product/rddaniel/include/mcp_rddaniel_mmap_mcp.h new file mode 100644 index 00000000..668b1f31 --- /dev/null +++ b/product/rddaniel/include/mcp_rddaniel_mmap_mcp.h @@ -0,0 +1,15 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MCP_RDDANIEL_MMAP_MCP_H +#define MCP_RDDANIEL_MMAP_MCP_H + +#define MCP_ROM_BASE 0x00000000 +#define MCP_RAM0_BASE 0x00800000 +#define MCP_RAM1_BASE 0x20000000 + +#endif /* MCP_RDDANIEL_MMAP_MCP_H */ diff --git a/product/rddaniel/include/mcp_system_mmap_mcp.h b/product/rddaniel/include/mcp_system_mmap_mcp.h new file mode 100644 index 00000000..73554a21 --- /dev/null +++ b/product/rddaniel/include/mcp_system_mmap_mcp.h @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MCP_SYSTEM_MMAP_MCP_H +#define MCP_SYSTEM_MMAP_MCP_H + +#include <mcp_rddaniel_mmap_mcp.h> + +#define MCP_ROM_SIZE (64 * 1024) +#define MCP_RAM0_SIZE (64 * 1024) +#define MCP_RAM1_SIZE (64 * 1024) + +#endif /* MCP_SYSTEM_MMAP_MCP_H */ diff --git a/product/rddaniel/include/rddaniel_core.h b/product/rddaniel/include/rddaniel_core.h new file mode 100644 index 00000000..13b60f0b --- /dev/null +++ b/product/rddaniel/include/rddaniel_core.h @@ -0,0 +1,36 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RDDANIEL_CORE_H +#define RDDANIEL_CORE_H + +#include <fwk_assert.h> + +#define RDDANIEL_CORE_PER_CLUSTER_MAX 1 + +#define CORES_PER_CLUSTER 1 +#define NUMBER_OF_CLUSTERS 16 + +static inline unsigned int rddaniel_core_get_cluster_count(void) +{ + return NUMBER_OF_CLUSTERS; +} + +static inline unsigned int rddaniel_core_get_core_per_cluster_count( + unsigned int cluster) +{ + fwk_assert(cluster < rddaniel_core_get_cluster_count()); + + return CORES_PER_CLUSTER; +} + +static inline unsigned int rddaniel_core_get_core_count(void) +{ + return NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER; +} + +#endif /* RDDANIEL_CORE_H */ diff --git a/product/rddaniel/include/rddaniel_pik_cpu.h b/product/rddaniel/include/rddaniel_pik_cpu.h new file mode 100644 index 00000000..f54e5a50 --- /dev/null +++ b/product/rddaniel/include/rddaniel_pik_cpu.h @@ -0,0 +1,92 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RDDANIEL_PIK_CPU_H +#define RDDANIEL_PIK_CPU_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief PE Static Configuration register definitions + */ +struct static_config_reg { + FWK_RW uint32_t STATIC_CONFIG; + FWK_RW uint32_t RVBARADDR_LW; + FWK_RW uint32_t RVBARADDR_UP; + uint32_t RESERVED; +}; + +/*! + * \brief AP cores clock control register definitions + */ +struct coreclk_reg { + FWK_RW uint32_t CTRL; + FWK_RW uint32_t DIV; + uint32_t RESERVED; + FWK_RW uint32_t MOD; +}; + +/*! + * \brief CPU (V8.2) PIK register definitions + */ +struct pik_cpu_reg { + FWK_RW uint32_t CLUSTER_CONFIG; + uint8_t RESERVED0[0x10 - 0x4]; + struct static_config_reg STATIC_CONFIG[16]; + uint8_t RESERVED1[0x800 - 0x110]; + FWK_RW uint32_t PPUCLK_CTRL; + FWK_RW uint32_t PPUCLK_DIV1; + uint8_t RESERVED2[0x810 - 0x808]; + FWK_RW uint32_t PCLK_CTRL; + uint8_t RESERVED3[0x820 - 0x814]; + FWK_RW uint32_t DBGCLK_CTRL; + FWK_RW uint32_t DBGCLK_DIV1; + uint8_t RESERVED4[0x830 - 0x828]; + FWK_RW uint32_t GICCLK_CTRL; + uint8_t RESERVED5[0x840 - 0x834]; + FWK_RW uint32_t AMBACLK_CTRL; + uint8_t RESERVED6[0x850 - 0x844]; + FWK_RW uint32_t CLUSCLK_CTRL; + FWK_RW uint32_t CLUSCLK_DIV1; + uint8_t RESERVED7[0x860 - 0x858]; + struct coreclk_reg CORECLK[8]; + uint8_t RESERVED8[0xA00 - 0x8E0]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xB00 - 0xA0C]; + FWK_R uint32_t NERRIQ_INT_STATUS; + FWK_R uint32_t NFAULTIQ_INT_STATUS; + uint8_t RESERVED10[0xFB4 - 0xB08]; + FWK_R uint32_t CAP3; + FWK_R uint32_t CAP2; + FWK_R uint32_t CAP; + FWK_R uint32_t PCL_CONFIG; + uint8_t RESERVED11[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#define PIK_CPU_CAP_CLUSSYNC UINT32_C(0x00000001) +#define PIK_CPU_CAP_CORESYNC(CORE) ((uint32_t)(1 << ((CORE) + 1))) +#define PIK_CPU_CAP_PE_MASK UINT32_C(0xF0000000) +#define PIK_CPU_CAP_PE_POS 28 + +#define PIK_CPU_PCL_CONFIG_NO_OF_PPU UINT32_C(0x0000000F) + +#endif /* RDDANIEL_PIK_CPU_H */ diff --git a/product/rddaniel/include/rddaniel_pik_debug.h b/product/rddaniel/include/rddaniel_pik_debug.h new file mode 100644 index 00000000..6352d89e --- /dev/null +++ b/product/rddaniel/include/rddaniel_pik_debug.h @@ -0,0 +1,50 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RDDANIEL_PIK_DEBUG_H +#define RDDANIEL_PIK_DEBUG_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief Debug register definitions + */ +struct pik_debug_reg { + FWK_RW uint32_t DEBUG_CTRL; + FWK_R uint32_t DEBUG_STATUS; + FWK_RW uint32_t DEBUG_CONFIG; + uint8_t RESERVED0[0x10 - 0xC]; + FWK_R uint32_t APP_DAP_TARGET_ID; + FWK_R uint32_t SCP_DAP_TARGET_ID; + FWK_R uint32_t DAP_INSTANCE_ID; + uint8_t RESERVED1[0x810 - 0x1C]; + FWK_RW uint32_t TRACECLK_CTRL; + FWK_RW uint32_t TRACECLK_DIV1; + uint8_t RESERVED2[0x820 - 0x818]; + FWK_RW uint32_t PCLKDBG_CTRL; + uint8_t RESERVED3[0x830 - 0x824]; + FWK_RW uint32_t ATCLKDBG_CTRL; + FWK_RW uint32_t ATCLKDBG_DIV1; + FWK_R uint8_t RESERVED4[0xFC0 - 0x838]; + FWK_R uint32_t PCL_CONFIG; + uint8_t RESERVED5[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#endif /* RDDANIEL_PIK_DEBUG_H */ diff --git a/product/rddaniel/include/rddaniel_pik_scp.h b/product/rddaniel/include/rddaniel_pik_scp.h new file mode 100644 index 00000000..2b5f45d3 --- /dev/null +++ b/product/rddaniel/include/rddaniel_pik_scp.h @@ -0,0 +1,100 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP PIK registers + */ + +#ifndef RDDANIEL_PIK_SCP_H +#define RDDANIEL_PIK_SCP_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief SCP PIK register definitions + */ +struct pik_scp_reg { + uint8_t RESERVED0[0x10 - 0x0]; + FWK_RW uint32_t RESET_SYNDROME; + uint8_t RESERVED1[0x20 - 0x14]; + FWK_RW uint32_t SURVIVAL_RESET_STATUS; + uint8_t RESERVED2[0x34 - 0x24]; + FWK_RW uint32_t ADDR_TRANS; + FWK_RW uint32_t DBG_ADDR_TRANS; + uint8_t RESERVED3[0x40 - 0x3C]; + FWK_RW uint32_t WS1_TIMER_MATCH; + FWK_RW uint32_t WS1_TIMER_EN; + uint8_t RESERVED4[0x200 - 0x48]; + FWK_R uint32_t SS_RESET_STATUS; + FWK_W uint32_t SS_RESET_SET; + FWK_W uint32_t SS_RESET_CLR; + uint8_t RESERVED5[0x810 - 0x20C]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + uint8_t RESERVED6[0x820 - 0x818]; + FWK_RW uint32_t ACLK_CTRL; + FWK_RW uint32_t ACLK_DIV1; + uint8_t RESERVED7[0x830 - 0x828]; + FWK_RW uint32_t GTSYNCCLK_CTRL; + FWK_RW uint32_t GTSYNCCLK_DIV1; + uint8_t RESERVED8[0xA10 - 0x838]; + FWK_R uint32_t PLL_STATUS[17]; + uint8_t RESERVED9[0xA60 - 0xA54]; + FWK_R uint32_t CONS_MMUTCU_INT_STATUS; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS0; + FWK_R uint32_t CONS_MMUTBU_INT_STATUS1; + FWK_W uint32_t CONS_MMUTCU_INT_CLR; + FWK_W uint32_t CONS_MMUTBU_INT_CLR0; + FWK_W uint32_t CONS_MMUTBU_INT_CLR1; + uint8_t RESERVED10[0xB00 - 0xA78]; + FWK_R uint32_t MHU_NS_INT_STATUS; + FWK_R uint32_t MHU_S_INT_STATUS; + uint8_t RESERVED11[0xB20 - 0xB08]; + FWK_R uint32_t CPU_PPU_INT_STATUS[8]; + FWK_R uint32_t CLUS_PPU_INT_STATUS; + uint8_t RESERVED12[0xB60 - 0xB44]; + FWK_R uint32_t TIMER_INT_STATUS[8]; + FWK_R uint32_t CPU_PLL_LOCK_STATUS[8]; + uint8_t RESERVED13[0xBC0 - 0xBA0]; + FWK_R uint32_t CPU_PLL_UNLOCK_STATUS[8]; + uint8_t RESERVED14[0xBF0 - 0xBE0]; + FWK_R uint32_t CLUSTER_PLL_LOCK_STATUS; + FWK_R uint32_t CLUSTER_PLL_UNLOCK_STATUS; + uint8_t RESERVED15[0xC00 - 0xBF8]; + FWK_R uint32_t CLUS_FAULT_INT_STATUS; + uint8_t RESERVED16[0xC30 - 0xC04]; + FWK_R uint32_t CLUSTER_ECCERR_INT_STATUS; + uint8_t RESERVED17[0xD00 - 0xC34]; + FWK_R uint32_t DMC0_4_INT_STATUS; + FWK_R uint32_t DMC1_5_INT_STATUS; + FWK_R uint32_t DMC2_6_INT_STATUS; + FWK_R uint32_t DMC3_7_INT_STATUS; + uint8_t RESERVED18[0xFC0 - 0xD10]; + FWK_R uint32_t PCL_CFG; + uint8_t RESERVED19[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#define PLL_STATUS_0_REFCLK UINT32_C(0x00000001) +#define PLL_STATUS_0_SYSPLLLOCK UINT32_C(0x00000002) +#define PLL_STATUS_0_DDRPLLLOCK UINT32_C(0x00000004) +#define PLL_STATUS_0_INTPLLLOCK UINT32_C(0x00000008) + +#define PLL_STATUS_CPUPLLLOCK(CPU) ((uint32_t)(1 << (CPU % 32))) + +#endif /* RDDANIEL_PIK_SCP_H */ diff --git a/product/rddaniel/include/rddaniel_pik_system.h b/product/rddaniel/include/rddaniel_pik_system.h new file mode 100644 index 00000000..159a5b31 --- /dev/null +++ b/product/rddaniel/include/rddaniel_pik_system.h @@ -0,0 +1,74 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RDDANIEL_PIK_SYSTEM_H +#define RDDANIEL_PIK_SYSTEM_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief TCU clock register definitions + */ +struct tcuclk_ctrl_reg { + FWK_RW uint32_t TCUCLK_CTRL; + FWK_RW uint32_t TCUCLK_DIV1; +}; + +/*! + * \brief System PIK register definitions + */ +struct pik_system_reg { + uint8_t RESERVED0[0x800 - 0x0]; + FWK_RW uint32_t PPUCLK_CTRL; + FWK_RW uint32_t PPUCLK_DIV1; + uint8_t RESERVED1[0x820 - 0x808]; + FWK_RW uint32_t INTCLK_CTRL; + FWK_RW uint32_t INTCLK_DIV1; + uint8_t RESERVED2[0x830 - 0x828]; + struct tcuclk_ctrl_reg TCUCLK[4]; + FWK_RW uint32_t GICCLK_CTRL; + FWK_RW uint32_t GICCLK_DIV1; + uint8_t RESERVED3[0x860 - 0x858]; + FWK_RW uint32_t PCLKSCP_CTRL; + FWK_RW uint32_t PCLKSCP_DIV1; + uint8_t RESERVED4[0x870 - 0x868]; + FWK_RW uint32_t SYSPERCLK_CTRL; + FWK_RW uint32_t SYSPERCLK_DIV1; + uint8_t RESERVED5[0x880 - 0x878]; + FWK_RW uint32_t DMCCLK_CTRL; + FWK_RW uint32_t DMCCLK_DIV1; + uint8_t RESERVED6[0x890 - 0x888]; + FWK_RW uint32_t SYSPCLKDBG_CTRL; + FWK_RW uint32_t SYSPCLKDBG_DIV1; + uint8_t RESERVED7[0x8A0 - 0x898]; + FWK_RW uint32_t UARTCLK_CTRL; + FWK_RW uint32_t UARTCLK_DIV1; + uint8_t RESERVED8[0xA00 - 0x8A8]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xB0C - 0xA0C]; + FWK_RW uint32_t SYSTOP_RST_DLY; + uint8_t RESERVED10[0xFC0 - 0xB10]; + FWK_R uint32_t PCL_CONFIG; + uint8_t RESERVED11[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#endif /* RDDANIEL_PIK_SYSTEM_H */ diff --git a/product/rddaniel/include/rddaniel_power_domain.h b/product/rddaniel/include/rddaniel_power_domain.h new file mode 100644 index 00000000..f3b381c1 --- /dev/null +++ b/product/rddaniel/include/rddaniel_power_domain.h @@ -0,0 +1,51 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RDDANIEL System Support + */ + +#ifndef RDDANIEL_POWER_DOMAIN_H +#define RDDANIEL_POWER_DOMAIN_H + +#include <mod_power_domain.h> + +/*! Additional RDDANIEL power domain states */ +enum rddaniel_power_domain_states { + RDDANIEL_POWER_DOMAIN_STATE_FUNC_RET = MOD_PD_STATE_COUNT, + RDDANIEL_POWER_DOMAIN_STATE_FULL_RET, + RDDANIEL_POWER_DOMAIN_STATE_MEM_RET, + RDDANIEL_POWER_DOMAIN_STATE_COUNT +}; + +/*! Power domain state masks */ +enum rddaniel_power_domain_state_masks { + RDDANIEL_POWER_DOMAIN_STATE_FUNC_RET_MASK = + (1 << RDDANIEL_POWER_DOMAIN_STATE_FUNC_RET), + RDDANIEL_POWER_DOMAIN_STATE_FULL_RET_MASK = + (1 << RDDANIEL_POWER_DOMAIN_STATE_FULL_RET), + RDDANIEL_POWER_DOMAIN_STATE_MEM_RET_MASK = + (1 << RDDANIEL_POWER_DOMAIN_STATE_MEM_RET), +}; + +/*! Mask for the cluster valid power states */ +#define RDDANIEL_CLUSTER_VALID_STATE_MASK ( \ + MOD_PD_STATE_OFF_MASK | \ + MOD_PD_STATE_ON_MASK | \ + MOD_PD_STATE_SLEEP_MASK | \ + RDDANIEL_POWER_DOMAIN_STATE_MEM_RET_MASK | \ + RDDANIEL_POWER_DOMAIN_STATE_FUNC_RET_MASK \ + ) + +/*! Mask for the core valid power states */ +#define RDDANIEL_CORE_VALID_STATE_MASK ( \ + MOD_PD_STATE_OFF_MASK | \ + MOD_PD_STATE_ON_MASK | \ + MOD_PD_STATE_SLEEP_MASK | \ + RDDANIEL_POWER_DOMAIN_STATE_FULL_RET_MASK \ + ) + +#endif /* RDDANIEL_POWER_DOMAIN_H */ diff --git a/product/rddaniel/include/rddaniel_sds.h b/product/rddaniel/include/rddaniel_sds.h new file mode 100644 index 00000000..628387de --- /dev/null +++ b/product/rddaniel/include/rddaniel_sds.h @@ -0,0 +1,65 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RDDANIEL_SDS_H +#define RDDANIEL_SDS_H + +#include <mod_sds.h> + +/* + * Structure identifiers. + */ +enum rddaniel_sds_struct_id { + RDDANIEL_SDS_CPU_INFO = 1 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIEL_SDS_FIRMWARE_VERSION = 2 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIEL_SDS_PLATFORM_ID = 3 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIEL_SDS_RESET_SYNDROME = 4 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIEL_SDS_FEATURE_AVAILABILITY = + 5 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIEL_SDS_CPU_BOOTCTR = 6 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + RDDANIEL_SDS_CPU_FLAGS = 7 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), +}; + +/* + * Structure sizes. + */ +#define RDDANIEL_SDS_CPU_INFO_SIZE 4 +#define RDDANIEL_SDS_FIRMWARE_VERSION_SIZE 4 +#define RDDANIEL_SDS_PLATFORM_ID_SIZE 8 +#define RDDANIEL_SDS_RESET_SYNDROME_SIZE 4 +#define RDDANIEL_SDS_FEATURE_AVAILABILITY_SIZE 4 +#define RDDANIEL_SDS_CPU_BOOTCTR_SIZE 256 +#define RDDANIEL_SDS_CPU_FLAGS_SIZE 256 + +/* + * Field masks and offsets for the RDDANIEL_SDS_AP_CPU_INFO structure. + */ +#define RDDANIEL_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF +#define RDDANIEL_SDS_CPU_INFO_PRIMARY_POS 0 + +/* + * Platform information + */ +struct rddaniel_sds_platid { + /* Subsystem part number */ + uint32_t platform_identifier; + /* Platform type information */ + uint32_t platform_type_identifier; +}; + +/* + * Field masks and offsets for the RDDANIEL_SDS_FEATURE_AVAILABILITY structure. + */ +#define RDDANIEL_SDS_FEATURE_FIRMWARE_MASK 0x1 +#define RDDANIEL_SDS_FEATURE_DMC_MASK 0x2 +#define RDDANIEL_SDS_FEATURE_MESSAGING_MASK 0x4 + +#define RDDANIEL_SDS_FEATURE_FIRMWARE_POS 0 +#define RDDANIEL_SDS_FEATURE_DMC_POS 1 +#define RDDANIEL_SDS_FEATURE_MESSAGING_POS 2 + +#endif /* RDDANIEL_SDS_H */ diff --git a/product/rddaniel/include/scp_rddaniel_irq.h b/product/rddaniel/include/scp_rddaniel_irq.h new file mode 100644 index 00000000..785bbbfe --- /dev/null +++ b/product/rddaniel/include/scp_rddaniel_irq.h @@ -0,0 +1,283 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_RDDANIEL_IRQ_H +#define SCP_RDDANIEL_IRQ_H + +#include <fwk_interrupt.h> + +#define SCP_WDOG_IRQ FWK_INTERRUPT_NMI /* SCP Watchdog (SP805) */ + +enum scp_rddaniel_interrupt { + RESERVED0_IRQ = 0, /* Reserved */ + CDBG_PWR_UP_REQ_IRQ = 1, /* Coresight Debug Power Request */ + CSYS_PWR_UP_REQ_IRQ = 2, /* Coresight System Power Request */ + CDBG_RST_REQ_IRQ = 3, /* Coresight Debug Reset Request */ + GIC_EXT_WAKEUP_IRQ = 4, /* External GIC Wakeup Request */ + RESERVED5_IRQ = 5, /* Reserved */ + RESERVED6_IRQ = 6, /* Reserved */ + RESERVED7_IRQ = 7, /* Reserved */ + RESERVED8_IRQ = 8, /* Reserved */ + RESERVED9_IRQ = 9, /* Reserved */ + RESERVED10_IRQ = 10, /* Reserved */ + RESERVED11_IRQ = 11, /* Reserved */ + RESERVED12_IRQ = 12, /* Reserved */ + RESERVED13_IRQ = 13, /* Reserved */ + RESERVED14_IRQ = 14, /* Reserved */ + RESERVED15_IRQ = 15, /* Reserved */ + SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */ + SOC_WAKEUP1_IRQ = 17, /* SoC Expansion Wakeup */ + SOC_WAKEUP2_IRQ = 18, /* SoC Expansion Wakeup */ + SOC_WAKEUP3_IRQ = 19, /* SoC Expansion Wakeup */ + SOC_WAKEUP4_IRQ = 20, /* SoC Expansion Wakeup */ + SOC_WAKEUP5_IRQ = 21, /* SoC Expansion Wakeup */ + SOC_WAKEUP6_IRQ = 22, /* SoC Expansion Wakeup */ + SOC_WAKEUP7_IRQ = 23, /* SoC Expansion Wakeup */ + SOC_WAKEUP8_IRQ = 24, /* SoC Expansion Wakeup */ + SOC_WAKEUP9_IRQ = 25, /* SoC Expansion Wakeup */ + SOC_WAKEUP10_IRQ = 26, /* SoC Expansion Wakeup */ + SOC_WAKEUP11_IRQ = 27, /* SoC Expansion Wakeup */ + SOC_WAKEUP12_IRQ = 28, /* SoC Expansion Wakeup */ + SOC_WAKEUP13_IRQ = 29, /* SoC Expansion Wakeup */ + SOC_WAKEUP14_IRQ = 30, /* SoC Expansion Wakeup */ + SOC_WAKEUP15_IRQ = 31, /* SoC Expansion Wakeup */ + RESERVED32_IRQ = 32, /* Reserved */ + TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ + SYS_GEN_TIMER_SYNC_IRQ = 34, /* System Generic Timer synchronization */ + CSTS_SYNC_IRQ = 35, /* Coresight Time stamp synchronization */ + RESERVED36_IRQ = 36, /* Reserved */ + CTI_TRIGGER0_IRQ = 37, /* SCP CTI Trigger */ + CTI_TRIGGER1_IRQ = 38, /* SCP CTI Trigger */ + GIC_ERROR_ECC_IRQ = 39, /* GIC Error (ECC Fatal) */ + GIC_ERROR_AXIM_IRQ = 40, /* GIC Error (AXIM) */ + RESERVED41_IRQ = 41, /* Reserved */ + AON_UART_IRQ = 42, /* Always on UART */ + RESERVED43_IRQ = 43, /* Reserved */ + GEN_WD_WS0_IRQ = 44, /* Generic Watchdog timer WS0 */ + GEN_WD_WS1_IRQ = 45, /* Generic Watchdog timer WS1 */ + TRUSTED_WD_WS0_IRQ = 46, /* Trusted Watchdog timer WS0 */ + TRUSTED_WD_WS1_IRQ = 47, /* Trusted Watchdog timer WS1 */ + APPS_UART_IRQ = 48, /* Application UART */ + RESERVED49_IRQ = 49, /* Reserved */ + PPU_CORES0_IRQ = 50, /* Consolidated PPU Interrupt for cores + 1-32, 129-160 */ + PPU_CORES1_IRQ = 51, /* Consolidated PPU Interrupt for cores + 33-64, 161-192 */ + PPU_CORES2_IRQ = 52, /* Consolidated PPU Interrupt for cores + 65-96, 193-224 */ + PPU_CORES3_IRQ = 53, /* Consolidated PPU Interrupt for cores + 97-128, 225-256 */ + PPU_CLUSTERS_IRQ = 54, /* Consolidated clusters PPU */ + PLL_CORES0_LOCK_IRQ = 55, /* Consolidated PLL lock for PLLs + 1-32, 65-96, 129-160, 193-224 */ + PLL_CORES1_LOCK_IRQ = 56, /* Consolidated PLL lock for PLLs + 33-64, 97-128, 161-192, 225-256 */ + PLL_CORES0_UNLOCK_IRQ = 57, /* Consolidated PLL unlock for PLLs + 1-32, 65-96, 129-160, 193-224 */ + PLL_CORES1_UNLOCK_IRQ = 58, /* Consolidated PLL unlock for PLLs + 33-64, 97-128, 161-192, 225-256 */ + FAULT_CORES0_IRQ = 59, /* Consolidated fault IRQ for cores 1-32, + 129-160 */ + FAULT_CORES1_IRQ = 60, /* Consolidated fault IRQ for cores 33-64, + 161-192 */ + FAULT_CORES2_IRQ = 61, /* Consolidated fault IRQ for cores 65-96, + 193-224 */ + FAULT_CORES3_IRQ = 62, /* Consolidated fault IRQ for cores 97-128, + 225-256 */ + FAULT_CLUSTERS_IRQ = 63, /* Consolidated clusters fault */ + ECC_CORES0_ERROR_IRQ = 64, /* Consolidated ECC ERROR for cores + 1-32, 129-160 */ + ECC_CORES1_ERROR_IRQ = 65, /* Consolidated ECC ERROR for cores + 33-64, 161-192 */ + ECC_CORES2_ERROR_IRQ = 66, /* Consolidated ECC ERROR for cores + 65-96, 193-224 */ + ECC_CORES3_ERROR_IRQ = 67, /* Consolidated ECC ERROR for cores + 96-128, 225-256 */ + ECC_CLUSTERS_ERROR_IRQ = 68, /* Consolidated clusters ECC ERROR */ + PLL_CLUSTERS_LOCK_IRQ = 69, /* Consolidated clusters PLL Lock */ + PLL_CLUSTERS_UNLOCK_IRQ = 70, /* Consolidated clusters PLL Unlock*/ + RESERVED71_IRQ = 71, /* Reserved */ + RESERVED72_IRQ = 72, /* Reserved */ + RESERVED73_IRQ = 73, /* Reserved */ + RESERVED74_IRQ = 74, /* Reserved */ + RESERVED75_IRQ = 75, /* Reserved */ + RESERVED76_IRQ = 76, /* Reserved */ + RESERVED77_IRQ = 77, /* Reserved */ + RESERVED78_IRQ = 78, /* Reserved */ + RESERVED79_IRQ = 79, /* Reserved */ + RESERVED80_IRQ = 80, /* Reserved */ + RESERVED81_IRQ = 81, /* Reserved */ + MHU_AP_NONSEC_IRQ = 82, /* MHU non-secure irq bewteen SCP and AP */ + MHU_AP_SEC_IRQ = 83, /* MHU secure irq bewteen SCP and AP */ + MHU_MCP_NONSEC_IRQ = 84, /* MHU non-secure irq between SCP and + MCP */ + MHU_MCP_SEC_IRQ = 85, /* MHU secure irq bewteen SCP and MCP */ + RESERVED86_IRQ = 86, /* Reserved */ + RESERVED87_IRQ = 87, /* Reserved */ + RESERVED88_IRQ = 88, /* Reserved */ + RESERVED89_IRQ = 89, /* Reserved */ + TIMER_CLUSTERS_IRQ = 90, /* Consolidated clusters timer interrupt */ + RESERVED91_IRQ = 91, /* Reserved */ + RESERVED92_IRQ = 92, /* Reserved */ + RESERVED93_IRQ = 93, /* Reserved */ + MMU_TCU_RASIRPT_IRQ = 94, /* Consolidated MMU RAS */ + MMU_TBU_RASIRPT_IRQ = 95, /* Consolidated TBU RAS */ + INT_PPU_IRQ = 96, /* PPU interrupt from Interconnect PPU */ + INT_ERRNS_IRQ = 97, /* Non-Sec error interrupt from + Interconnect PPU */ + INT_ERRS_IRQ = 98, /* Secure error interrupt from + Interconnect PPU */ + INT_FAULTS_IRQ = 99, /* Secure fault interrupt from + Interconnect PPU */ + INT_FAULTNS_IRQ = 100, /* Non-Sec fault interrupt from + Interconnect PPU */ + INT_PMU_IRQ = 101, /* PMU count overflow interrupt */ + RESERVED102_IRQ = 102, /* Reserved */ + RESERVED103_IRQ = 103, /* Reserved */ + RESERVED104_IRQ = 104, /* Reserved */ + RESERVED105_IRQ = 105, /* Reserved */ + RESERVED106_IRQ = 106, /* Reserved */ + RESERVED107_IRQ = 107, /* Reserved */ + RESERVED108_IRQ = 108, /* Reserved */ + RESERVED109_IRQ = 109, /* Reserved */ + RESERVED110_IRQ = 110, /* Reserved */ + RESERVED111_IRQ = 111, /* Reserved */ + RESERVED112_IRQ = 112, /* Reserved */ + RESERVED113_IRQ = 113, /* Reserved */ + RESERVED114_IRQ = 114, /* Reserved */ + RESERVED115_IRQ = 115, /* Reserved */ + RESERVED116_IRQ = 116, /* Reserved */ + RESERVED117_IRQ = 117, /* Reserved */ + RESERVED118_IRQ = 118, /* Reserved */ + RESERVED119_IRQ = 119, /* Reserved */ + PPU_DBGCH0_IRQ = 120, /* Debug Chain 0 PPU */ + PPU_DBGCH1_IRQ = 121, /* Debug Chain 1 PPU */ + PPU_DBGCH2_IRQ = 122, /* Debug Chain 2 PPU */ + PPU_DBGCH3_IRQ = 123, /* Debug Chain 3 PPU */ + PPU_DBGCH4_IRQ = 124, /* Debug Chain 4 PPU */ + PPU_DBGCH5_IRQ = 125, /* Debug Chain 5 PPU */ + PPU_DBGCH6_IRQ = 126, /* Debug Chain 6 PPU */ + PPU_DBGCH7_IRQ = 127, /* Debug Chain 7 PPU */ + RESERVED128_IRQ = 128, /* Reserved */ + RESERVED129_IRQ = 129, /* Reserved */ + DEBUG_PIK_IRQ = 130, /* DEBUG PIK */ + PPU_LOGIC_IRQ = 131, /* PPU LOGIC */ + RESERVED132_IRQ = 132, /* Reserved */ + RESERVED133_IRQ = 133, /* Reserved */ + RESERVED134_IRQ = 134, /* Reserved */ + PPU_SRAM_IRQ = 135, /* PPU SRAM */ + RESERVED136_IRQ = 136, /* Reserved */ + RESERVED137_IRQ = 137, /* Reserved */ + RESERVED138_IRQ = 138, /* Reserved */ + MCP_WD_WS1_IRQ = 139, /* MCP watchdog reset */ + PLL_SYS_LOCK_IRQ = 140, /* System PLL Lock */ + PLL_SYS_UNLOCK_IRQ = 141, /* System PLL Unlock */ + PLL_INT_LOCK_IRQ = 142, /* Interconnect PLL Lock */ + PLL_INT_UNLOCK_IRQ = 143, /* Interconnect PLL Unlock */ + RESERVED144_IRQ = 144, /* Reserved */ + RESERVED145_IRQ = 145, /* Reserved */ + RESERVED146_IRQ = 146, /* Reserved */ + RESERVED147_IRQ = 147, /* Reserved */ + RESERVED148_IRQ = 148, /* Reserved */ + RESERVED149_IRQ = 149, /* Reserved */ + RESERVED150_IRQ = 150, /* Reserved */ + RESERVED151_IRQ = 151, /* Reserved */ + RESERVED152_IRQ = 152, /* Reserved */ + RESERVED153_IRQ = 153, /* Reserved */ + RESERVED154_IRQ = 154, /* Reserved */ + RESERVED155_IRQ = 155, /* Reserved */ + RESERVED156_IRQ = 156, /* Reserved */ + RESERVED157_IRQ = 157, /* Reserved */ + RESERVED158_IRQ = 158, /* Reserved */ + RESERVED159_IRQ = 159, /* Reserved */ + RESERVED160_IRQ = 160, /* Reserved */ + RESERVED161_IRQ = 161, /* Reserved */ + RESERVED162_IRQ = 162, /* Reserved */ + RESERVED163_IRQ = 163, /* Reserved */ + RESERVED164_IRQ = 164, /* Reserved */ + RESERVED165_IRQ = 165, /* Reserved */ + RESERVED166_IRQ = 166, /* Reserved */ + RESERVED167_IRQ = 167, /* Reserved */ + RESERVED168_IRQ = 168, /* Reserved */ + RESERVED169_IRQ = 169, /* Reserved */ + RESERVED170_IRQ = 170, /* Reserved */ + RESERVED171_IRQ = 171, /* Reserved */ + RESERVED172_IRQ = 172, /* Reserved */ + RESERVED173_IRQ = 173, /* Reserved */ + PLL_DMC_LOCK_IRQ = 174, /* DMC PLL LOCK */ + PLL_DMC_UNLOCK_IRQ = 175, /* DMC PLL LOCK */ + RESERVED176_IRQ = 176, /* Reserved */ + RESERVED177_IRQ = 177, /* Reserved */ + RESERVED178_IRQ = 178, /* Reserved */ + RESERVED179_IRQ = 179, /* Reserved */ + DMCS0_MISC_OFLOW_IRQ = 180, /* DMC 0/4 Combined Error Overflow */ + DMCS0_ERR_OFLOW_IRQ = 181, /* DMC 0/4 Error Overflow */ + DMCS0_ECC_ERR_INT_IRQ = 182, /* DMC 0/4 ECC Error Int */ + DMCS0_MISC_ACCESS_INT_IRQ = 183, /* DMC 0/4 Combined Miscellaneous + access int */ + DMCS0_TEMPERATURE_EVENT_INT_IRQ = 184, /* DMC 0/4 Temperature event int */ + DMCS0_FAILED_ACCESS_INT_IRQ = 185, /* DMC 0/4 Failed access int */ + DMCS0_MGR_INT_IRQ = 186, /* DMC 0/4 combined manager int */ + DMCS1_MISC_OFLOW_IRQ = 187, /* DMC 1/5 Combined Error Overflow */ + DMCS1_ERR_OFLOW_IRQ = 188, /* DMC 1/5 Error Overflow */ + DMCS1_ECC_ERR_INT_IRQ = 189, /* DMC 1/5 ECC Error Int */ + DMCS1_MISC_ACCESS_INT_IRQ = 190, /* DMC 1/5 Combined Miscellaneous + access int */ + DMCS1_TEMPERATURE_EVENT_INT_IRQ = 191, /* DMC 1/5 Temperature event int */ + DMCS1_FAILED_ACCESS_INT_IRQ = 192, /* DMC 1/5 Failed access int */ + DMCS1_MGR_INT_IRQ = 193, /* DMC 1/5 combined manager int */ + DMCS2_MISC_OFLOW_IRQ = 194, /* DMC 2/6 Combined Error Overflow */ + DMCS2_ERR_OFLOW_IRQ = 195, /* DMC 2/6 Error Overflow */ + DMCS2_ECC_ERR_INT_IRQ = 196, /* DMC 2/6 ECC Error Int */ + DMCS2_MISC_ACCESS_INT_IRQ = 197, /* DMC 2/6 Combined Miscellaneous + access int */ + DMCS2_TEMPERATURE_EVENT_INT_IRQ = 198, /* DMC 2/6 Temperature event int */ + DMCS2_FAILED_ACCESS_INT_IRQ = 199, /* DMC 2/6 Failed access int */ + DMCS2_MGR_INT_IRQ = 200, /* DMC 2/6 combined manager int */ + DMCS3_MISC_OFLOW_IRQ = 201, /* DMC 3/7 Combined Error Overflow */ + DMCS3_ERR_OFLOW_IRQ = 202, /* DMC 3/7 Error Overflow */ + DMCS3_ECC_ERR_INT_IRQ = 203, /* DMC 3/7 ECC Error Int */ + DMCS3_MISC_ACCESS_INT_IRQ = 204, /* DMC 3/7 Combined Miscellaneous + access int */ + DMCS3_TEMPERATURE_EVENT_INT_IRQ = 205, /* DMC 3/7 Temperature event int */ + DMCS3_FAILED_ACCESS_INT_IRQ = 206, /* DMC 3/7 Failed access int */ + DMCS3_MGR_INT_IRQ = 207, /* DMC 3/7 combined manager int */ + SCP_EXT_INTR0_IRQ = 208, /* SCP Customer Extension */ + SCP_EXT_INTR1_IRQ = 209, /* SCP Customer Extension */ + SCP_EXT_INTR2_IRQ = 210, /* SCP Customer Extension */ + SCP_EXT_INTR3_IRQ = 211, /* SCP Customer Extension */ + SCP_EXT_INTR4_IRQ = 212, /* SCP Customer Extension */ + SCP_EXT_INTR5_IRQ = 213, /* SCP Customer Extension */ + SCP_EXT_INTR6_IRQ = 214, /* SCP Customer Extension */ + SCP_EXT_INTR7_IRQ = 215, /* SCP Customer Extension */ + SCP_EXT_INTR8_IRQ = 216, /* SCP Customer Extension */ + SCP_EXT_INTR9_IRQ = 217, /* SCP Customer Extension */ + SCP_EXT_INTR10_IRQ = 218, /* SCP Customer Extension */ + SCP_EXT_INTR11_IRQ = 219, /* SCP Customer Extension */ + SCP_EXT_INTR12_IRQ = 220, /* SCP Customer Extension */ + SCP_EXT_INTR13_IRQ = 221, /* SCP Customer Extension */ + SCP_EXT_INTR14_IRQ = 222, /* SCP Customer Extension */ + SCP_EXT_INTR15_IRQ = 223, /* SCP Customer Extension */ + SCP_EXT_INTR16_IRQ = 224, /* SCP Customer Extension */ + SCP_EXT_INTR17_IRQ = 225, /* SCP Customer Extension */ + SCP_EXT_INTR18_IRQ = 226, /* SCP Customer Extension */ + SCP_EXT_INTR19_IRQ = 227, /* SCP Customer Extension */ + SCP_EXT_INTR20_IRQ = 228, /* SCP Customer Extension */ + SCP_EXT_INTR21_IRQ = 229, /* SCP Customer Extension */ + SCP_EXT_INTR22_IRQ = 230, /* SCP Customer Extension */ + SCP_EXT_INTR23_IRQ = 231, /* SCP Customer Extension */ + SCP_EXT_INTR24_IRQ = 232, /* SCP Customer Extension */ + SCP_EXT_INTR25_IRQ = 233, /* SCP Customer Extension */ + SCP_EXT_INTR26_IRQ = 234, /* SCP Customer Extension */ + SCP_EXT_INTR27_IRQ = 235, /* SCP Customer Extension */ + SCP_EXT_INTR28_IRQ = 236, /* SCP Customer Extension */ + SCP_EXT_INTR29_IRQ = 237, /* SCP Customer Extension */ + SCP_EXT_INTR30_IRQ = 238, /* SCP Customer Extension */ + SCP_EXT_INTR31_IRQ = 239 /* SCP Customer Extension */ +}; + +#endif /* SCP_RDDANIEL_IRQ_H */ diff --git a/product/rddaniel/include/scp_rddaniel_mhu.h b/product/rddaniel/include/scp_rddaniel_mhu.h new file mode 100644 index 00000000..c1d3025b --- /dev/null +++ b/product/rddaniel/include/scp_rddaniel_mhu.h @@ -0,0 +1,20 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * MHU module device indexes. + */ + +#ifndef SCP_RDDANIEL_MHU_H +#define SCP_RDDANIEL_MHU_H + +enum scp_rddaniel_mhu_device_idx { + SCP_RDDANIEL_MHU_DEVICE_IDX_SCP_AP_S_CLUS0, + SCP_RDDANIEL_MHU_DEVICE_IDX_SCP_AP_NS_CLUS0, + SCP_RDDANIEL_MHU_DEVICE_IDX_COUNT +}; + +#endif /* SCP_RDDANIEL_MHU_H */ diff --git a/product/rddaniel/include/scp_rddaniel_mmap.h b/product/rddaniel/include/scp_rddaniel_mmap.h new file mode 100644 index 00000000..fc8188cb --- /dev/null +++ b/product/rddaniel/include/scp_rddaniel_mmap.h @@ -0,0 +1,87 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_RDDANIEL_MMAP_H +#define SCP_RDDANIEL_MMAP_H + +#include <stdint.h> + +/* + * Top-level base addresses + */ +#define SCP_EXPANSION1_BASE UINT32_C(0x01000000) +#define SCP_EXPANSION2_BASE UINT32_C(0x21000000) +#define SCP_EXPANSION3_BASE UINT32_C(0x40000000) +#define SCP_PERIPHERAL_BASE UINT32_C(0x44000000) +#define SCP_MEMORY_CONTROLLER UINT32_C(0x4E000000) +#define SCP_POWER_PERIPHERAL_BASE UINT32_C(0x50000000) +#define SCP_NOC_GPV_BASE UINT32_C(0x51000000) +#define SCP_SYS0_BASE UINT32_C(0x60000000) +#define SCP_SYS1_BASE UINT32_C(0xA0000000) +#define SCP_PPB_BASE_INTERNAL UINT32_C(0xE0000000) +#define SCP_PPB_BASE_EXTERNAL UINT32_C(0xE0040000) + +/* + * Peripherals + */ +#define SCP_REFCLK_CNTCTL_BASE (SCP_PERIPHERAL_BASE + 0x0000) +#define SCP_REFCLK_CNTBASE0_BASE (SCP_PERIPHERAL_BASE + 0x1000) +#define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000) +#define SCP_WDOG_BASE (SCP_PERIPHERAL_BASE + 0x6000) +#define SCP_CS_CNTCONTROL_BASE (SCP_PERIPHERAL_BASE + 0xA000) +#define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE + 0x1000000) +#define SCP_MHU_MCP_BASE (SCP_PERIPHERAL_BASE + 0x1800000) + +/* + * Power control peripherals + */ +#define SCP_PIK_SCP_BASE (SCP_POWER_PERIPHERAL_BASE + 0x00000) +#define SCP_PIK_DEBUG_BASE (SCP_POWER_PERIPHERAL_BASE + 0x20000) +#define SCP_SCP_SENSOR_DEBUG_BASE (SCP_POWER_PERIPHERAL_BASE + 0x30000) +#define SCP_PIK_SYSTEM_BASE (SCP_POWER_PERIPHERAL_BASE + 0x40000) +#define SCP_SENSOR_SYSTEM_BASE (SCP_POWER_PERIPHERAL_BASE + 0x50000) +#define SCP_SENSOR_CLUS0_BASE (SCP_POWER_PERIPHERAL_BASE + 0x70000) +#define SCP_SENSOR_CLUS1_BASE (SCP_POWER_PERIPHERAL_BASE + 0x90000) +#define SCP_PIK_DEBUG_CHAIN_BASE (SCP_POWER_PERIPHERAL_BASE + 0x500000) +#define SCP_PIK_CLUSTER_BASE(n) ((SCP_POWER_PERIPHERAL_BASE + 0x60000) + \ + ((n) * 0x20000)) + +/* + * PPU base address + */ +#define SCP_PPU_SCP_BASE (SCP_PIK_SCP_BASE + 0x1000) +#define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000) +#define SCP_PPU_SYS1_BASE (SCP_PIK_SYSTEM_BASE + 0x5000) +#define SCP_PPU_DEBUG_BASE (SCP_PIK_DEBUG_BASE + 0x1000) +#define SCP_PPU_CLUSTER_BASE(n) (SCP_PIK_CLUSTER_BASE((n)) + 0x1000) +#define SCP_PPU_CORE_BASE(n, m) (SCP_PPU_CLUSTER_BASE((n)) + \ + ((m) + 1) * 0x1000) + +/* + * System access port 0 + */ +#define SCP_CMN_RHODES_BASE (SCP_SYS0_BASE + 0x10000000) + +/* + * System access port 1 + */ +#define SCP_TRUSTED_RAM_BASE (SCP_SYS1_BASE + 0x04000000) +#define SCP_NONTRUSTED_RAM_BASE (SCP_SYS1_BASE + 0x06000000) +#define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYS1_BASE + 0x2A430000) +#define SCP_SID_BASE (SCP_SYS1_BASE + 0x2A4A0000) + +/* + * Base addresses of MHU devices v2 + */ +#define SCP_MHU_SCP_AP_SND_NS_CLUS0 (SCP_MHU_AP_BASE + 0x00000) +#define SCP_MHU_SCP_AP_RCV_NS_CLUS0 (SCP_MHU_AP_BASE + 0x10000) +#define SCP_MHU_SCP_AP_SND_S_CLUS0 (SCP_MHU_AP_BASE + 0x400000) +#define SCP_MHU_SCP_AP_RCV_S_CLUS0 (SCP_MHU_AP_BASE + 0x410000) +#define SCP_MHU_SCP_MCP_SND (SCP_MHU_MCP_BASE + 0x00000) +#define SCP_MHU_SCP_MCP_RCV (SCP_MHU_MCP_BASE + 0x10000) + +#endif /* SCP_RDDANIEL_MMAP_H */ diff --git a/product/rddaniel/include/scp_rddaniel_mmap_scp.h b/product/rddaniel/include/scp_rddaniel_mmap_scp.h new file mode 100644 index 00000000..8e30b607 --- /dev/null +++ b/product/rddaniel/include/scp_rddaniel_mmap_scp.h @@ -0,0 +1,15 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_RDDANIEL_MMAP_SCP_H +#define SCP_RDDANIEL_MMAP_SCP_H + +#define SCP_ROM_BASE 0x00000000 +#define SCP_RAM0_BASE 0x00800000 +#define SCP_RAM1_BASE 0x20000000 + +#endif /* SCP_RDDANIEL_MMAP_SCP_H */ diff --git a/product/rddaniel/include/scp_rddaniel_pik.h b/product/rddaniel/include/scp_rddaniel_pik.h new file mode 100644 index 00000000..15d55081 --- /dev/null +++ b/product/rddaniel/include/scp_rddaniel_pik.h @@ -0,0 +1,20 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_RDDANIEL_PIK_H +#define SCP_RDDANIEL_PIK_H + +#include <scp_rddaniel_mmap.h> +#include <rddaniel_pik_cpu.h> +#include <rddaniel_pik_scp.h> +#include <rddaniel_pik_system.h> + +#define PIK_CLUSTER(IDX) ((struct pik_cpu_reg *) SCP_PIK_CLUSTER_BASE(IDX)) +#define PIK_SCP ((struct pik_scp_reg *) SCP_PIK_SCP_BASE) +#define PIK_SYSTEM ((struct pik_system_reg *) SCP_PIK_SYSTEM_BASE) + +#endif /* SCP_RDDANIEL_PIK_H */ diff --git a/product/rddaniel/include/scp_rddaniel_scmi.h b/product/rddaniel/include/scp_rddaniel_scmi.h new file mode 100644 index 00000000..f3ae5d41 --- /dev/null +++ b/product/rddaniel/include/scp_rddaniel_scmi.h @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for SCMI and SMT module configurations. + */ + +#ifndef SCP_RDDANIEL_SCMI_H +#define SCP_RDDANIEL_SCMI_H + +/* SCMI agent identifiers */ +enum scp_rddaniel_scmi_agent_id { + /* 0 is reserved for the platform */ + SCP_SCMI_AGENT_ID_OSPM = 1, + SCP_SCMI_AGENT_ID_PSCI, +}; + +/* SCMI service indexes */ +enum scp_rddaniel_scmi_service_idx { + SCP_RDDANIEL_SCMI_SERVICE_IDX_PSCI, + SCP_RDDANIEL_SCMI_SERVICE_IDX_OSPM, + SCP_RDDANIEL_SCMI_SERVICE_IDX_COUNT, +}; + +#endif /* SCP_RDDANIEL_SCMI_H */ diff --git a/product/rddaniel/include/scp_software_mmap.h b/product/rddaniel/include/scp_software_mmap.h new file mode 100644 index 00000000..dc6b8778 --- /dev/null +++ b/product/rddaniel/include/scp_software_mmap.h @@ -0,0 +1,50 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Software defined memory map shared between SCP and AP cores. + */ + +#ifndef SCP_SOFTWARE_MMAP_H +#define SCP_SOFTWARE_MMAP_H + +#include <scp_rddaniel_mmap.h> +#include <fwk_macros.h> + +#define SCP_NOR_FLASH_BASE 0x08000000 +#define SCP_NOR_BASE (SCP_NOR_FLASH_BASE + 0x03D80000) +#define SCP_IMAGE_SIZE (256 * FWK_KIB) + +#define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE) +#define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB) + +/* Non-secure shared memory at the base of Non-trusted SRAM */ +#define SCP_AP_SHARED_NONSECURE_BASE (SCP_NONTRUSTED_RAM_BASE) +#define SCP_AP_SHARED_NONSECURE_SIZE (4 * FWK_KIB) + +/* SDS Memory Region */ +#define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE) +#define SCP_SDS_MEM_SIZE (3520) + +/* AP Context Area */ +#define SCP_AP_CONTEXT_BASE (SCP_AP_SHARED_SECURE_BASE + \ + SCP_AP_SHARED_SECURE_SIZE - \ + SCP_AP_CONTEXT_SIZE) +#define SCP_AP_CONTEXT_SIZE (64) + +/* SCMI Secure Payload Areas */ +#define SCP_SCMI_PAYLOAD_SIZE (128) +#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + \ + SCP_SDS_MEM_SIZE) +#define SCP_SCMI_PAYLOAD_S_P2A_BASE (SCP_SCMI_PAYLOAD_S_A2P_BASE + \ + SCP_SCMI_PAYLOAD_SIZE) + +/* SCMI Non-Secure Payload Areas */ +#define SCP_SCMI_PAYLOAD_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE) +#define SCP_SCMI_PAYLOAD_NS_P2A_BASE (SCP_SCMI_PAYLOAD_NS_A2P_BASE + \ + SCP_SCMI_PAYLOAD_SIZE) + +#endif /* SCP_SOFTWARE_MMAP_H */ diff --git a/product/rddaniel/include/scp_system_mmap.h b/product/rddaniel/include/scp_system_mmap.h new file mode 100644 index 00000000..ef8e2799 --- /dev/null +++ b/product/rddaniel/include/scp_system_mmap.h @@ -0,0 +1,53 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_SYSTEM_MMAP_H +#define SCP_SYSTEM_MMAP_H + +#include <scp_rddaniel_mmap.h> + +#define SCP_PLAT_BASE (SCP_SYS0_BASE + 0x3FFE0000) + +#define SCP_PLL_BASE (SCP_EXPANSION2_BASE + 0x01000000) + +#define SCP_PLL_SYSPLL (SCP_PLL_BASE) +#define SCP_PLL_CLUS0 (SCP_PLL_BASE + 0x00000004) +#define SCP_PLL_CLUS1 (SCP_PLL_BASE + 0x00000008) +#define SCP_PLL_DMC (SCP_PLL_BASE + 0x00000010) +#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020) + +#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100) +#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104) +#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108) +#define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C) +#define SCP_PLL_CPU4 (SCP_PLL_BASE + 0x00000110) +#define SCP_PLL_CPU5 (SCP_PLL_BASE + 0x00000114) +#define SCP_PLL_CPU6 (SCP_PLL_BASE + 0x00000118) +#define SCP_PLL_CPU7 (SCP_PLL_BASE + 0x0000011C) +#define SCP_PLL_CPU8 (SCP_PLL_BASE + 0x00000120) +#define SCP_PLL_CPU9 (SCP_PLL_BASE + 0x00000124) +#define SCP_PLL_CPU10 (SCP_PLL_BASE + 0x00000128) +#define SCP_PLL_CPU11 (SCP_PLL_BASE + 0x0000012c) +#define SCP_PLL_CPU12 (SCP_PLL_BASE + 0x00000130) +#define SCP_PLL_CPU13 (SCP_PLL_BASE + 0x00000134) +#define SCP_PLL_CPU14 (SCP_PLL_BASE + 0x00000138) +#define SCP_PLL_CPU15 (SCP_PLL_BASE + 0x0000013c) + +#define SCP_DDR_PHY0 (SCP_SYS0_BASE + 0x3FB60000) +#define SCP_DDR_PHY1 (SCP_SYS0_BASE + 0x3FB70000) +#define SCP_DDR_PHY2 (SCP_SYS0_BASE + 0x3FB80000) +#define SCP_DDR_PHY3 (SCP_SYS0_BASE + 0x3FB90000) + +#define SCP_DMC0 (SCP_MEMORY_CONTROLLER + 0x00000000) +#define SCP_DMC1 (SCP_MEMORY_CONTROLLER + 0x00100000) +#define SCP_DMC2 (SCP_MEMORY_CONTROLLER + 0x00200000) +#define SCP_DMC3 (SCP_MEMORY_CONTROLLER + 0x00300000) + +#define SCP_SENSOR_SOC_TEMP (SCP_PLAT_BASE + 0x00000080) +#define SCP_PLATFORM_ID (SCP_PLAT_BASE + 0x000000E0) + +#endif /* SCP_SYSTEM_MMAP_H*/ diff --git a/product/rddaniel/include/scp_system_mmap_scp.h b/product/rddaniel/include/scp_system_mmap_scp.h new file mode 100644 index 00000000..4a2db437 --- /dev/null +++ b/product/rddaniel/include/scp_system_mmap_scp.h @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_SYSTEM_MMAP_SCP_H +#define SCP_SYSTEM_MMAP_SCP_H + +#include <scp_rddaniel_mmap_scp.h> + +#define SCP_ROM_SIZE (64 * 1024) +#define SCP_RAM0_SIZE (256 * 1024) +#define SCP_RAM1_SIZE (256 * 1024) + +#endif /* SCP_SYSTEM_MMAP_SCP_H */ diff --git a/product/rddaniel/include/system_clock.h b/product/rddaniel/include/system_clock.h new file mode 100644 index 00000000..43459353 --- /dev/null +++ b/product/rddaniel/include/system_clock.h @@ -0,0 +1,16 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SYSTEM_CLOCK_H +#define SYSTEM_CLOCK_H + +#include <fwk_macros.h> + +#define CLOCK_RATE_REFCLK (100UL * FWK_MHZ) +#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) + +#endif /* SYSTEM_CLOCK_H */ diff --git a/product/rddaniel/mcp_romfw/config_clock.c b/product/rddaniel/mcp_romfw/config_clock.c new file mode 100644 index 00000000..8e781762 --- /dev/null +++ b/product/rddaniel/mcp_romfw/config_clock.c @@ -0,0 +1,10 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_module.h> + +const struct fwk_module_config config_clock = { 0 }; diff --git a/product/rddaniel/mcp_romfw/config_log.c b/product/rddaniel/mcp_romfw/config_log.c new file mode 100644 index 00000000..39340447 --- /dev/null +++ b/product/rddaniel/mcp_romfw/config_log.c @@ -0,0 +1,58 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_banner.h> +#include <fwk_macros.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_log.h> +#include <mod_pl011.h> +#include <mcp_rddaniel_mmap.h> + +/* + * PL011 module + */ +static const struct fwk_element pl011_element_desc_table[] = { + [0] = { + .name = "uart0", + .data = &((struct mod_pl011_device_config) { + .reg_base = MCP_UART0_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + .clock_id = FWK_ID_NONE_INIT, + }), + }, + [1] = { 0 }, +}; + +static const struct fwk_element *get_pl011_table(fwk_id_t module_id) +{ + return pl011_element_desc_table; +} + +struct fwk_module_config config_pl011 = { + .get_element_table = get_pl011_table, +}; + +/* + * Log module + */ +static const struct mod_log_config log_data = { + .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0), + .log_groups = MOD_LOG_GROUP_ERROR | + MOD_LOG_GROUP_INFO | + MOD_LOG_GROUP_WARNING | + MOD_LOG_GROUP_DEBUG, + .banner = FWK_BANNER_MCP + FWK_BANNER_ROM_FIRMWARE + BUILD_VERSION_DESCRIBE_STRING "\n", +}; + +struct fwk_module_config config_log = { + .data = &log_data, +}; diff --git a/product/rddaniel/mcp_romfw/config_rddaniel_rom.c b/product/rddaniel/mcp_romfw/config_rddaniel_rom.c new file mode 100644 index 00000000..fc355341 --- /dev/null +++ b/product/rddaniel/mcp_romfw/config_rddaniel_rom.c @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_module.h> +#include <mod_rddaniel_rom.h> +#include <mcp_rddaniel_mmap_mcp.h> + +const struct fwk_module_config config_rddaniel_rom = { + .data = &((struct rddaniel_rom_config) { + .ramfw_base = MCP_RAM0_BASE, + .load_ram_size = 0, + }) +}; diff --git a/product/rddaniel/mcp_romfw/firmware.mk b/product/rddaniel/mcp_romfw/firmware.mk new file mode 100644 index 00000000..7d202e16 --- /dev/null +++ b/product/rddaniel/mcp_romfw/firmware.mk @@ -0,0 +1,25 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := no +BS_FIRMWARE_HAS_NOTIFICATION := yes +BS_FIRMWARE_MODULE_HEADERS_ONLY := \ + power_domain + +BS_FIRMWARE_MODULES := \ + pl011 \ + log \ + clock \ + rddaniel_rom + +BS_FIRMWARE_SOURCES := \ + config_log.c \ + config_clock.c \ + config_rddaniel_rom.c + +include $(BS_DIR)/firmware.mk diff --git a/product/rddaniel/mcp_romfw/fmw_memory.ld.S b/product/rddaniel/mcp_romfw/fmw_memory.ld.S new file mode 100644 index 00000000..29cd4048 --- /dev/null +++ b/product/rddaniel/mcp_romfw/fmw_memory.ld.S @@ -0,0 +1,32 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * ROM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_LD_S +#define FMW_MEMORY_LD_S + +#include <mcp_system_mmap_mcp.h> + +#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * ROM memory + */ +#define FIRMWARE_MEM0_SIZE MCP_ROM_SIZE +#define FIRMWARE_MEM0_BASE MCP_ROM_BASE + +/* + * RAM memory + */ +#define FIRMWARE_MEM1_SIZE MCP_RAM1_SIZE +#define FIRMWARE_MEM1_BASE MCP_RAM1_BASE + +#define FIRMWARE_STACK_SIZE (1 * 1024) + +#endif /* FMW_MEMORY_LD_S */ diff --git a/product/rddaniel/module/rddaniel_rom/include/mod_rddaniel_rom.h b/product/rddaniel/module/rddaniel_rom/include/mod_rddaniel_rom.h new file mode 100644 index 00000000..c7e39779 --- /dev/null +++ b/product/rddaniel/module/rddaniel_rom/include/mod_rddaniel_rom.h @@ -0,0 +1,45 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MOD_RDDANIEL_ROM_H +#define MOD_RDDANIEL_ROM_H + +#include <stdint.h> + +/*! + * \addtogroup GroupRDDANIELModule RDDANIEL Product Modules + * @{ + */ + +/*! + * \defgroup GroupRDDANIEL ROM Support + * @{ + */ + +/*! + * \brief Module configuration data. + */ +struct rddaniel_rom_config { + /*! Base address of the RAM firmware image */ + const uintptr_t ramfw_base; + + /*! Base address of the NOR flash memory */ + const uintptr_t nor_base; + + /*! The RAM size to load */ + const unsigned int load_ram_size; +}; + +/*! + * @} + */ + +/*! + * @} + */ + +#endif /* MOD_RDDANIEL_ROM_H */ diff --git a/product/rddaniel/module/rddaniel_rom/src/Makefile b/product/rddaniel/module/rddaniel_rom/src/Makefile new file mode 100644 index 00000000..4cadbe08 --- /dev/null +++ b/product/rddaniel/module/rddaniel_rom/src/Makefile @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_LIB_NAME := RDDANIEL ROM +BS_LIB_SOURCES := mod_rddaniel_rom.c + +include $(BS_DIR)/lib.mk diff --git a/product/rddaniel/module/rddaniel_rom/src/mod_rddaniel_rom.c b/product/rddaniel/module/rddaniel_rom/src/mod_rddaniel_rom.c new file mode 100644 index 00000000..4887079a --- /dev/null +++ b/product/rddaniel/module/rddaniel_rom/src/mod_rddaniel_rom.c @@ -0,0 +1,118 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> +#include <string.h> +#include <fwk_errno.h> +#include <fwk_interrupt.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <fwk_thread.h> +#include <mod_log.h> +#include <mod_rddaniel_rom.h> + +static const struct rddaniel_rom_config *rom_config; +static struct mod_log_api *log_api; + +enum rom_event { + ROM_EVENT_RUN, + ROM_EVENT_COUNT +}; + +/* + * This function assumes that the RAM firmware image is located at the beginning + * of the SCP SRAM. The reset handler will be at offset 0x4 (the second entry of + * the vector table). + */ +static void jump_to_ramfw(void) +{ + uintptr_t const *reset_base = (uintptr_t *)(rom_config->ramfw_base + 0x4); + void (*ramfw_reset_handler)(void); + + /* + * Disable interrupts for the duration of the ROM firmware to RAM firmware + * transition. + */ + fwk_interrupt_global_disable(); + + ramfw_reset_handler = (void (*)(void))*reset_base; + + /* + * Execute the RAM firmware's reset handler to pass control from ROM + * firmware to the RAM firmware. + */ + ramfw_reset_handler(); +} + +/* + * Framework API + */ +static int rddaniel_rom_init(fwk_id_t module_id, unsigned int element_count, + const void *data) +{ + rom_config = data; + + return FWK_SUCCESS; +} + +static int rddaniel_rom_bind(fwk_id_t id, unsigned int round) +{ + int status; + + /* Use second round only (round numbering is zero-indexed) */ + if (round == 1) { + /* Bind to the log component */ + status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_LOG), + FWK_ID_API(FWK_MODULE_IDX_LOG, 0), + &log_api); + + if (status != FWK_SUCCESS) + return FWK_E_PANIC; + } + + return FWK_SUCCESS; +} + +static int rddaniel_rom_start(fwk_id_t id) +{ + int status; + struct fwk_event event = { + .source_id = FWK_ID_MODULE(FWK_MODULE_IDX_RDDANIEL_ROM), + .target_id = FWK_ID_MODULE(FWK_MODULE_IDX_RDDANIEL_ROM), + .id = FWK_ID_EVENT(FWK_MODULE_IDX_RDDANIEL_ROM, ROM_EVENT_RUN), + }; + + status = fwk_thread_put_event(&event); + + return status; +} + +static int rddaniel_rom_process_event(const struct fwk_event *event, + struct fwk_event *resp) +{ + log_api->log(MOD_LOG_GROUP_INFO, "[ROM] Launch RAM\n"); + + if (rom_config->load_ram_size != 0) { + memcpy((void *)rom_config->ramfw_base, + (uint8_t *)rom_config->nor_base, rom_config->load_ram_size); + } + + jump_to_ramfw(); + + return FWK_SUCCESS; +} + +/* Module descriptor */ +const struct fwk_module module_rddaniel_rom = { + .name = "RDDANIEL_ROM", + .type = FWK_MODULE_TYPE_SERVICE, + .event_count = ROM_EVENT_COUNT, + .init = rddaniel_rom_init, + .bind = rddaniel_rom_bind, + .start = rddaniel_rom_start, + .process_event = rddaniel_rom_process_event, +}; diff --git a/product/rddaniel/module/rddaniel_system/include/mod_rddaniel_system.h b/product/rddaniel/module/rddaniel_system/include/mod_rddaniel_system.h new file mode 100644 index 00000000..8d063f0c --- /dev/null +++ b/product/rddaniel/module/rddaniel_system/include/mod_rddaniel_system.h @@ -0,0 +1,64 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RDDANIEL System Support + */ + +#ifndef MOD_RDDANIEL_SYSTEM_H +#define MOD_RDDANIEL_SYSTEM_H + +#include <mod_power_domain.h> + +/*! + * \addtogroup GroupRDDANIELModule RDDANIEL Product Modules + * @{ + */ + +/*! + * \defgroup GroupRDDANIELSystem RDDANIEL System Support + * @{ + */ + +/*! + * \brief Additional RDDANIEL system power states. + */ +enum mod_rddaniel_system_power_states { + MOD_RDDANIEL_SYSTEM_POWER_STATE_SLEEP0 = MOD_PD_STATE_COUNT, + MOD_RDDANIEL_SYSTEM_POWER_STATE_SLEEP1, + MOD_RDDANIEL_SYSTEM_POWER_STATE_COUNT +}; + +/*! + * \brief System power state masks. + */ +enum mod_rddaniel_system_power_state_masks { + MOD_RDDANIEL_SYSTEM_POWER_STATE_SLEEP0_MASK = + (1 << MOD_RDDANIEL_SYSTEM_POWER_STATE_SLEEP0), + MOD_RDDANIEL_SYSTEM_POWER_STATE_SLEEP1_MASK = + (1 << MOD_RDDANIEL_SYSTEM_POWER_STATE_SLEEP1), +}; + +/*! + * \brief Indices of the interfaces exposed by the module. + */ +enum mod_rddaniel_system_api_idx { + /*! API index for the driver interface of the SYSTEM POWER module */ + MOD_RDDANIEL_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER, + + /*! Number of exposed interfaces */ + MOD_RDDANIEL_SYSTEM_API_COUNT +}; + +/*! + * @} + */ + +/*! + * @} + */ + +#endif /* MOD_RDDANIEL_SYSTEM_H */ diff --git a/product/rddaniel/module/rddaniel_system/src/Makefile b/product/rddaniel/module/rddaniel_system/src/Makefile new file mode 100644 index 00000000..0fa81449 --- /dev/null +++ b/product/rddaniel/module/rddaniel_system/src/Makefile @@ -0,0 +1,11 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_LIB_NAME := RDDANIEL SYSTEM +BS_LIB_SOURCES = mod_rddaniel_system.c + +include $(BS_DIR)/lib.mk diff --git a/product/rddaniel/module/rddaniel_system/src/mod_rddaniel_system.c b/product/rddaniel/module/rddaniel_system/src/mod_rddaniel_system.c new file mode 100644 index 00000000..836681ea --- /dev/null +++ b/product/rddaniel/module/rddaniel_system/src/mod_rddaniel_system.c @@ -0,0 +1,361 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RDDANIEL System Support. + */ + +#include <stdint.h> +#include <fmw_cmsis.h> +#include <fwk_assert.h> +#include <fwk_id.h> +#include <fwk_interrupt.h> +#include <fwk_macros.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <fwk_notification.h> +#include <mod_clock.h> +#include <mod_rddaniel_system.h> +#include <mod_log.h> +#include <mod_scmi.h> +#include <mod_sds.h> +#include <mod_system_power.h> +#include <mod_power_domain.h> +#include <mod_ppu_v1.h> +#include <rddaniel_core.h> +#include <rddaniel_pik_scp.h> +#include <rddaniel_sds.h> +#include <scp_rddaniel_irq.h> +#include <scp_rddaniel_mmap.h> +#include <scp_rddaniel_scmi.h> +#include <config_clock.h> + +/* SCMI services required to enable the messaging stack */ +static unsigned int scmi_notification_table[] = { + SCP_RDDANIEL_SCMI_SERVICE_IDX_PSCI, + SCP_RDDANIEL_SCMI_SERVICE_IDX_OSPM, +}; + +/* Module context */ +struct rddaniel_system_ctx { + /* Pointer to the SCP PIK registers */ + struct pik_scp_reg *pik_scp_reg; + + /* Log API pointer */ + const struct mod_log_api *log_api; + + /* Pointer to the Interrupt Service Routine API of the PPU_V1 module */ + const struct ppu_v1_isr_api *ppu_v1_isr_api; + + /* Power domain module restricted API pointer */ + struct mod_pd_restricted_api *mod_pd_restricted_api; + + /* SDS API pointer */ + const struct mod_sds_api *sds_api; +}; + +struct rddaniel_system_isr { + unsigned int interrupt; + void (*handler)(void); +}; + +static struct rddaniel_system_ctx rddaniel_system_ctx; +const struct fwk_module_config config_rddaniel_system = { 0 }; + +static const uint32_t feature_flags = (RDDANIEL_SDS_FEATURE_FIRMWARE_MASK | + RDDANIEL_SDS_FEATURE_DMC_MASK | + RDDANIEL_SDS_FEATURE_MESSAGING_MASK); + +static fwk_id_t sds_feature_availability_id = + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SDS, 3); + +/* + * SCMI Messaging stack + */ + +static int messaging_stack_ready(void) +{ + const struct mod_sds_structure_desc *sds_structure_desc = + fwk_module_get_data(sds_feature_availability_id); + + /* + * Write SDS Feature Availability to signal the completion of the messaging + * stack + */ + return rddaniel_system_ctx.sds_api->struct_write(sds_structure_desc->id, + 0, (void *)(&feature_flags), sds_structure_desc->size); +} + +/* + * PPU Interrupt Service Routines for cluster and core power domains + */ + +static void ppu_cores_isr(unsigned int first, uint32_t status) +{ + unsigned int core_idx; + + while (status != 0) { + core_idx = __builtin_ctz(status); + status &= ~(1 << core_idx); + + if ((first + core_idx) >= rddaniel_core_get_core_count()) + continue; + + rddaniel_system_ctx.ppu_v1_isr_api->ppu_interrupt_handler( + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, first + core_idx)); + } +} + +static void ppu_cores_isr_0(void) +{ + ppu_cores_isr(0, rddaniel_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[0]); + ppu_cores_isr(128, rddaniel_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[4]); +} + +static void ppu_cores_isr_1(void) +{ + ppu_cores_isr(32, rddaniel_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[1]); + ppu_cores_isr(160, rddaniel_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[5]); +} + +static void ppu_cores_isr_2(void) +{ + ppu_cores_isr(64, rddaniel_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[2]); + ppu_cores_isr(192, rddaniel_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[6]); +} + +static void ppu_cores_isr_3(void) +{ + ppu_cores_isr(96, rddaniel_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[3]); + ppu_cores_isr(224, rddaniel_system_ctx.pik_scp_reg->CPU_PPU_INT_STATUS[7]); +} + +static void ppu_clusters_isr(void) +{ + uint32_t status = rddaniel_system_ctx.pik_scp_reg->CLUS_PPU_INT_STATUS; + unsigned int cluster_idx; + + while (status != 0) { + cluster_idx = __builtin_ctz(status); + + rddaniel_system_ctx.ppu_v1_isr_api->ppu_interrupt_handler( + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, + rddaniel_core_get_core_count() + cluster_idx)); + + status &= ~(1 << cluster_idx); + } +} + +/* + * PPU Interrupt Service Routine table + */ + +static struct rddaniel_system_isr isrs[] = { + [0] = { .interrupt = PPU_CORES0_IRQ, + .handler = ppu_cores_isr_0 }, + [1] = { .interrupt = PPU_CORES1_IRQ, + .handler = ppu_cores_isr_1 }, + [2] = { .interrupt = PPU_CORES2_IRQ, + .handler = ppu_cores_isr_2 }, + [3] = { .interrupt = PPU_CORES3_IRQ, + .handler = ppu_cores_isr_3 }, + [4] = { .interrupt = PPU_CLUSTERS_IRQ, + .handler = ppu_clusters_isr }, +}; + +/* + * System power's driver API + */ + +static int rddaniel_system_shutdown( + enum mod_pd_system_shutdown system_shutdown) +{ + NVIC_SystemReset(); + + return FWK_E_DEVICE; +} + +static const struct mod_system_power_driver_api + rddaniel_system_system_power_driver_api = { + .system_shutdown = rddaniel_system_shutdown, +}; + +/* + * Functions fulfilling the framework's module interface + */ + +static int rddaniel_system_mod_init(fwk_id_t module_id, unsigned int unused, + const void *unused2) +{ + int status; + unsigned int idx; + struct rddaniel_system_isr *isr; + + for (idx = 0; idx < FWK_ARRAY_SIZE(isrs); idx++) { + isr = &isrs[idx]; + status = fwk_interrupt_set_isr(isr->interrupt, isr->handler); + if (status != FWK_SUCCESS) + return status; + } + + rddaniel_system_ctx.pik_scp_reg = (struct pik_scp_reg *)SCP_PIK_SCP_BASE; + + return FWK_SUCCESS; +} + +static int rddaniel_system_bind(fwk_id_t id, unsigned int round) +{ + int status; + + if (round > 0) + return FWK_SUCCESS; + + status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_LOG), + FWK_ID_API(FWK_MODULE_IDX_LOG, 0), &rddaniel_system_ctx.log_api); + if (status != FWK_SUCCESS) + return status; + + status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_POWER_DOMAIN), + FWK_ID_API(FWK_MODULE_IDX_POWER_DOMAIN, MOD_PD_API_IDX_RESTRICTED), + &rddaniel_system_ctx.mod_pd_restricted_api); + if (status != FWK_SUCCESS) + return status; + + status = fwk_module_bind(FWK_ID_MODULE(FWK_MODULE_IDX_PPU_V1), + FWK_ID_API(FWK_MODULE_IDX_PPU_V1, MOD_PPU_V1_API_IDX_ISR), + &rddaniel_system_ctx.ppu_v1_isr_api); + if (status != FWK_SUCCESS) + return status; + + return fwk_module_bind(fwk_module_id_sds, + FWK_ID_API(FWK_MODULE_IDX_SDS, 0), + &rddaniel_system_ctx.sds_api); +} + +static int rddaniel_system_process_bind_request(fwk_id_t requester_id, + fwk_id_t pd_id, fwk_id_t api_id, const void **api) +{ + *api = &rddaniel_system_system_power_driver_api; + return FWK_SUCCESS; +} + +static int rddaniel_system_start(fwk_id_t id) +{ + int status; + unsigned int i; + + status = fwk_notification_subscribe( + mod_clock_notification_id_state_changed, + FWK_ID_ELEMENT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_INTERCONNECT), + id); + if (status != FWK_SUCCESS) + return status; + + rddaniel_system_ctx.log_api->log(MOD_LOG_GROUP_DEBUG, + "[RD-DANIEL SYSTEM] Requesting SYSTOP initialization...\n"); + + /* + * Subscribe to these SCMI channels in order to know when they have all + * initialized. + * At that point we can consider the SCMI stack to be initialized from + * the point of view of the PSCI agent. + */ + for (i = 0; i < FWK_ARRAY_SIZE(scmi_notification_table); i++) { + status = fwk_notification_subscribe( + mod_scmi_notification_id_initialized, + fwk_id_build_element_id(fwk_module_id_scmi, + scmi_notification_table[i]), + id); + if (status != FWK_SUCCESS) + return status; + } + + /* + * Subscribe to the SDS initialized notification so we can correctly let the + * PSCI agent know that the SCMI stack is initialized. + */ + status = fwk_notification_subscribe( + mod_sds_notification_id_initialized, + fwk_module_id_sds, + id); + if (status != FWK_SUCCESS) + return status; + + return + rddaniel_system_ctx.mod_pd_restricted_api->set_composite_state_async( + FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, 0), false, + MOD_PD_COMPOSITE_STATE(MOD_PD_LEVEL_2, 0, MOD_PD_STATE_ON, + MOD_PD_STATE_OFF, MOD_PD_STATE_OFF)); +} + +int rddaniel_system_process_notification(const struct fwk_event *event, + struct fwk_event *resp_event) +{ + int status; + struct clock_notification_params *params; + struct mod_pd_restricted_api *mod_pd_restricted_api; + static unsigned int scmi_notification_count = 0; + static bool sds_notification_received = false; + + assert(fwk_id_is_type(event->target_id, FWK_ID_TYPE_MODULE)); + + if (fwk_id_is_equal(event->id, mod_clock_notification_id_state_changed)) { + params = (struct clock_notification_params *)event->params; + + /* + * Initialize primary core when the system is initialized for the first + * time only + */ + if (params->new_state == MOD_CLOCK_STATE_RUNNING) { + rddaniel_system_ctx.log_api->log(MOD_LOG_GROUP_DEBUG, + "[RD-DANIEL SYSTEM] Initializing the primary core...\n"); + + mod_pd_restricted_api = rddaniel_system_ctx.mod_pd_restricted_api; + + status = mod_pd_restricted_api->set_composite_state_async( + FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, 0), + false, + MOD_PD_COMPOSITE_STATE(MOD_PD_LEVEL_2, 0, MOD_PD_STATE_ON, + MOD_PD_STATE_ON, MOD_PD_STATE_ON)); + if (status != FWK_SUCCESS) + return status; + + /* Unsubscribe to the notification */ + return fwk_notification_unsubscribe(event->id, event->source_id, + event->target_id); + } + + return FWK_SUCCESS; + } else if (fwk_id_is_equal(event->id, + mod_scmi_notification_id_initialized)) { + scmi_notification_count++; + } else if (fwk_id_is_equal(event->id, + mod_sds_notification_id_initialized)) { + sds_notification_received = true; + } else + return FWK_E_PARAM; + + if ((scmi_notification_count == FWK_ARRAY_SIZE(scmi_notification_table)) && + sds_notification_received) { + messaging_stack_ready(); + + scmi_notification_count = 0; + sds_notification_received = false; + } + + return FWK_SUCCESS; +} + +const struct fwk_module module_rddaniel_system = { + .name = "RDDANIEL_SYSTEM", + .type = FWK_MODULE_TYPE_DRIVER, + .api_count = MOD_RDDANIEL_SYSTEM_API_COUNT, + .init = rddaniel_system_mod_init, + .bind = rddaniel_system_bind, + .process_bind_request = rddaniel_system_process_bind_request, + .process_notification = rddaniel_system_process_notification, + .start = rddaniel_system_start, +}; diff --git a/product/rddaniel/product.mk b/product/rddaniel/product.mk new file mode 100644 index 00000000..b51d6539 --- /dev/null +++ b/product/rddaniel/product.mk @@ -0,0 +1,13 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# Platforms supported by the rddaniel product: RDDANIEL. +# + +BS_PRODUCT_NAME := rddaniel +BS_FIRMWARE_LIST := scp_romfw \ + scp_ramfw \ + mcp_romfw diff --git a/product/rddaniel/scp_ramfw/RTX_Config.h b/product/rddaniel/scp_ramfw/RTX_Config.h new file mode 100644 index 00000000..688d384f --- /dev/null +++ b/product/rddaniel/scp_ramfw/RTX_Config.h @@ -0,0 +1,56 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RTX2 v5 configuration file. + * The file must be called RTX_Config.h as it is included by the an RTX + * file in order to create a object file containing the configuration. + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +/* System */ +#define OS_DYNAMIC_MEM_SIZE 0 +#define OS_TICK_FREQ 1000 /* Hz */ +#define OS_ROBIN_ENABLE 0 +#define OS_ROBIN_TIMEOUT 0 +#define OS_ISR_FIFO_QUEUE 16 + +/* Thread */ +#define OS_THREAD_OBJ_MEM 0 +#define OS_THREAD_NUM 1 +#define OS_THREAD_DEF_STACK_NUM 0 +#define OS_THREAD_USER_STACK_SIZE 0 +#define OS_STACK_SIZE 200 +#define OS_IDLE_THREAD_STACK_SIZE 200 +#define OS_STACK_CHECK 1 +#define OS_STACK_WATERMARK 0 +#define OS_PRIVILEGE_MODE 1 + +/* Timer */ +#define OS_TIMER_OBJ_MEM 0 +#define OS_TIMER_NUM 1 +#define OS_TIMER_THREAD_PRIO 40 +#define OS_TIMER_THREAD_STACK_SIZE 200 +#define OS_TIMER_CB_QUEUE 4 + +/* Event flags */ +#define OS_EVFLAGS_OBJ_MEM 0 +#define OS_EVFLAGS_NUM 1 + +#define OS_MUTEX_OBJ_MEM 0 +#define OS_MUTEX_NUM 1 +#define OS_SEMAPHORE_OBJ_MEM 0 +#define OS_SEMAPHORE_NUM 1 +#define OS_MEMPOOL_OBJ_MEM 0 +#define OS_MEMPOOL_NUM 1 +#define OS_MEMPOOL_DATA_SIZE 0 +#define OS_MSGQUEUE_OBJ_MEM 0 +#define OS_MSGQUEUE_NUM 1 +#define OS_MSGQUEUE_DATA_SIZE 0 + +#endif /* RTX_CONFIG_H_ */ diff --git a/product/rddaniel/scp_ramfw/config_apcontext.c b/product/rddaniel/scp_ramfw/config_apcontext.c new file mode 100644 index 00000000..250d5209 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_apcontext.c @@ -0,0 +1,26 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_apcontext.h> +#include <scp_software_mmap.h> +#include <config_clock.h> + +/* + * AP Context module configuration + */ +static const struct mod_apcontext_config apcontext_data = { + .base = SCP_AP_CONTEXT_BASE, + .size = SCP_AP_CONTEXT_SIZE, + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), +}; + +struct fwk_module_config config_apcontext = { + .data = &apcontext_data, +}; diff --git a/product/rddaniel/scp_ramfw/config_armv7m_mpu.c b/product/rddaniel/scp_ramfw/config_armv7m_mpu.c new file mode 100644 index 00000000..7ff36959 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_armv7m_mpu.c @@ -0,0 +1,47 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <scp_rddaniel_mmap.h> +#include <scp_rddaniel_mmap_scp.h> +#include <mod_armv7m_mpu.h> +#include <fwk_macros.h> +#include <fwk_module.h> + +static const ARM_MPU_Region_t regions[] = { + { /* 0x0000_0000 - 0xFFFF_FFFF */ + .RBAR = ARM_MPU_RBAR(0, 0x00000000), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 1, 0, 1, 0, ARM_MPU_REGION_SIZE_4GB), + }, + { /* 0x0080_0000 - 0x00FF_FFFF */ + .RBAR = ARM_MPU_RBAR(1, SCP_RAM0_BASE), + .RASR = ARM_MPU_RASR( + 0, ARM_MPU_AP_PRO, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_256KB), + }, + { /* 0x2000_0000 - 0x20FF_FFFF */ + .RBAR = ARM_MPU_RBAR(2, SCP_RAM1_BASE), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB), + }, + { /* 0xA400_0000 - 0xA400_7FFF*/ + .RBAR = ARM_MPU_RBAR(3, SCP_TRUSTED_RAM_BASE), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_4KB), + }, + { /* 0xA600_0000 - 0xA600_7FFF */ + .RBAR = ARM_MPU_RBAR(4, SCP_NONTRUSTED_RAM_BASE), + .RASR = ARM_MPU_RASR( + 1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_256B), + }, +}; + +const struct fwk_module_config config_armv7m_mpu = { + .data = &((struct mod_armv7m_mpu_config){ + .region_count = FWK_ARRAY_SIZE(regions), + .regions = regions, + }), +}; diff --git a/product/rddaniel/scp_ramfw/config_clock.c b/product/rddaniel/scp_ramfw/config_clock.c new file mode 100644 index 00000000..a9a9e03c --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_clock.c @@ -0,0 +1,204 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_clock.h> +#include <mod_css_clock.h> +#include <mod_pik_clock.h> +#include <mod_power_domain.h> +#include <rddaniel_core.h> +#include <system_clock.h> +#include <config_clock.h> +#include <config_power_domain.h> + +static const struct fwk_element clock_dev_desc_table[] = { + [CLOCK_IDX_INTERCONNECT] = { + .name = "Interconnect", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, + CLOCK_PIK_IDX_INTERCONNECT), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP0] = { + .name = "CPU_GROUP0", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP0), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP1] = { + .name = "CPU_GROUP1", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP1), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP2] = { + .name = "CPU_GROUP2", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP2), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP3] = { + .name = "CPU_GROUP3", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP3), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP4] = { + .name = "CPU_GROUP4", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP4), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP5] = { + .name = "CPU_GROUP5", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP5), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP6] = { + .name = "CPU_GROUP6", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP6), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP7] = { + .name = "CPU_GROUP7", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP7), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP8] = { + .name = "CPU_GROUP8", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP8), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP9] = { + .name = "CPU_GROUP9", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP9), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP10] = { + .name = "CPU_GROUP10", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP10), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP11] = { + .name = "CPU_GROUP11", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP11), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP12] = { + .name = "CPU_GROUP12", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP12), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP13] = { + .name = "CPU_GROUP13", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP13), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP14] = { + .name = "CPU_GROUP14", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP14), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + [CLOCK_IDX_CPU_GROUP15] = { + .name = "CPU_GROUP15", + .data = &((struct mod_clock_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK, + CLOCK_CSS_IDX_CPU_GROUP15), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK, + MOD_CSS_CLOCK_API_TYPE_CLOCK), + }), + }, + { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *clock_get_dev_desc_table(fwk_id_t module_id) +{ + unsigned int i; + struct mod_clock_dev_config *dev_config; + + for (i = 0; i < CLOCK_IDX_COUNT; i++) { + dev_config = + (struct mod_clock_dev_config *)clock_dev_desc_table[i].data; + dev_config->pd_source_id = fwk_id_build_element_id( + fwk_module_id_power_domain, + rddaniel_core_get_core_count() + PD_STATIC_DEV_IDX_SYSTOP); + } + + return clock_dev_desc_table; +} + +const struct fwk_module_config config_clock = { + .get_element_table = clock_get_dev_desc_table, + .data = &((struct mod_clock_config) { + .pd_transition_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), + .pd_pre_transition_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_PRE_TRANSITION), + }), + +}; diff --git a/product/rddaniel/scp_ramfw/config_clock.h b/product/rddaniel/scp_ramfw/config_clock.h new file mode 100644 index 00000000..502613c3 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_clock.h @@ -0,0 +1,114 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_CLOCK_H +#define CONFIG_CLOCK_H + +/* + * Clock indexes. + */ +enum clock_idx { + CLOCK_IDX_INTERCONNECT, + CLOCK_IDX_CPU_GROUP0, + CLOCK_IDX_CPU_GROUP1, + CLOCK_IDX_CPU_GROUP2, + CLOCK_IDX_CPU_GROUP3, + CLOCK_IDX_CPU_GROUP4, + CLOCK_IDX_CPU_GROUP5, + CLOCK_IDX_CPU_GROUP6, + CLOCK_IDX_CPU_GROUP7, + CLOCK_IDX_CPU_GROUP8, + CLOCK_IDX_CPU_GROUP9, + CLOCK_IDX_CPU_GROUP10, + CLOCK_IDX_CPU_GROUP11, + CLOCK_IDX_CPU_GROUP12, + CLOCK_IDX_CPU_GROUP13, + CLOCK_IDX_CPU_GROUP14, + CLOCK_IDX_CPU_GROUP15, + CLOCK_IDX_COUNT +}; + +/* + * PIK clock indexes. + */ +enum clock_pik_idx { + CLOCK_PIK_IDX_CLUS0_CPU0, + CLOCK_PIK_IDX_CLUS1_CPU0, + CLOCK_PIK_IDX_CLUS2_CPU0, + CLOCK_PIK_IDX_CLUS3_CPU0, + CLOCK_PIK_IDX_CLUS4_CPU0, + CLOCK_PIK_IDX_CLUS5_CPU0, + CLOCK_PIK_IDX_CLUS6_CPU0, + CLOCK_PIK_IDX_CLUS7_CPU0, + CLOCK_PIK_IDX_CLUS8_CPU0, + CLOCK_PIK_IDX_CLUS9_CPU0, + CLOCK_PIK_IDX_CLUS10_CPU0, + CLOCK_PIK_IDX_CLUS11_CPU0, + CLOCK_PIK_IDX_CLUS12_CPU0, + CLOCK_PIK_IDX_CLUS13_CPU0, + CLOCK_PIK_IDX_CLUS14_CPU0, + CLOCK_PIK_IDX_CLUS15_CPU0, + CLOCK_PIK_IDX_DMC, + CLOCK_PIK_IDX_INTERCONNECT, + CLOCK_PIK_IDX_SCP, + CLOCK_PIK_IDX_GIC, + CLOCK_PIK_IDX_PCLKSCP, + CLOCK_PIK_IDX_SYSPERCLK, + CLOCK_PIK_IDX_UARTCLK, + CLOCK_PIK_IDX_COUNT +}; + +/* + * CSS clock indexes. + */ +enum clock_css_idx { + CLOCK_CSS_IDX_CPU_GROUP0, + CLOCK_CSS_IDX_CPU_GROUP1, + CLOCK_CSS_IDX_CPU_GROUP2, + CLOCK_CSS_IDX_CPU_GROUP3, + CLOCK_CSS_IDX_CPU_GROUP4, + CLOCK_CSS_IDX_CPU_GROUP5, + CLOCK_CSS_IDX_CPU_GROUP6, + CLOCK_CSS_IDX_CPU_GROUP7, + CLOCK_CSS_IDX_CPU_GROUP8, + CLOCK_CSS_IDX_CPU_GROUP9, + CLOCK_CSS_IDX_CPU_GROUP10, + CLOCK_CSS_IDX_CPU_GROUP11, + CLOCK_CSS_IDX_CPU_GROUP12, + CLOCK_CSS_IDX_CPU_GROUP13, + CLOCK_CSS_IDX_CPU_GROUP14, + CLOCK_CSS_IDX_CPU_GROUP15, + CLOCK_CSS_IDX_COUNT +}; + +/* + * PLL clock indexes. + */ +enum clock_pll_idx { + CLOCK_PLL_IDX_CPU0, + CLOCK_PLL_IDX_CPU1, + CLOCK_PLL_IDX_CPU2, + CLOCK_PLL_IDX_CPU3, + CLOCK_PLL_IDX_CPU4, + CLOCK_PLL_IDX_CPU5, + CLOCK_PLL_IDX_CPU6, + CLOCK_PLL_IDX_CPU7, + CLOCK_PLL_IDX_CPU8, + CLOCK_PLL_IDX_CPU9, + CLOCK_PLL_IDX_CPU10, + CLOCK_PLL_IDX_CPU11, + CLOCK_PLL_IDX_CPU12, + CLOCK_PLL_IDX_CPU13, + CLOCK_PLL_IDX_CPU14, + CLOCK_PLL_IDX_CPU15, + CLOCK_PLL_IDX_SYS, + CLOCK_PLL_IDX_DMC, + CLOCK_PLL_IDX_INTERCONNECT, + CLOCK_PLL_IDX_COUNT +}; + +#endif /* CONFIG_CLOCK_H */ diff --git a/product/rddaniel/scp_ramfw/config_cmn600.c b/product/rddaniel/scp_ramfw/config_cmn600.c new file mode 100644 index 00000000..adb0b14e --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_cmn600.c @@ -0,0 +1,108 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_macros.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_cmn600.h> +#include <scp_rddaniel_mmap.h> +#include <config_clock.h> + +#define ROOT_NODE_OFFSET 0xD00000 + +/* + * CMN600 nodes + */ +#define DMC0_ID 0x60 +#define DMC1_ID 0x6c +#define NODE_ID_HND 0x68 +#define NODE_ID_SBSX 0x64 + +static const unsigned int snf_table[] = { + DMC0_ID, /* Maps to HN-F logical node 0 */ + DMC0_ID, /* Maps to HN-F logical node 1 */ + DMC1_ID, /* Maps to HN-F logical node 2 */ + DMC1_ID, /* Maps to HN-F logical node 3 */ +}; + +static const struct mod_cmn600_memory_region_map mmap[] = { + { + /* + * System cache backed region + * Map: 0x0000_0000_0000 - 0xFFFF_FFFF_FFFF (256 TB) + */ + .base = UINT64_C(0x000000000000), + .size = UINT64_C(256) * FWK_TIB, + .type = MOD_CMN600_MEMORY_REGION_TYPE_SYSCACHE, + }, + { + /* + * Boot region + * Map: 0x0000_0000_0000 - 0x0000_0001_FFFF (128 MB) + */ + .base = UINT64_C(0x000000000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN600_REGION_TYPE_SYSCACHE_SUB, + .node_id = NODE_ID_SBSX, + }, + { + /* + * Peripherals + * Map: 0x00_0800_0000 - 0x00_0FFF_FFFF (128 MB) + */ + .base = UINT64_C(0x0008000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN600_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_1000_0000 - 0x00_1FFF_FFFF (256 MB) + */ + .base = UINT64_C(0x0010000000), + .size = UINT64_C(256) * FWK_MIB, + .type = MOD_CMN600_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_2000_0000 - 0x00_3FFF_FFFF (512 MB) + */ + .base = UINT64_C(0x0020000000), + .size = UINT64_C(512) * FWK_MIB, + .type = MOD_CMN600_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_4000_0000 - 0x00_7FFF_FFFF (1 GB) + */ + .base = UINT64_C(0x0040000000), + .size = UINT64_C(1) * FWK_GIB, + .type = MOD_CMN600_MEMORY_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, +}; + +const struct fwk_module_config config_cmn600 = { + .get_element_table = NULL, + .data = &((struct mod_cmn600_config) { + .base = SCP_CMN600_BASE, + .mesh_size_x = 4, + .mesh_size_y = 2, + .hnd_node_id = NODE_ID_HND, + .snf_table = snf_table, + .snf_count = FWK_ARRAY_SIZE(snf_table), + .mmap_table = mmap, + .mmap_count = FWK_ARRAY_SIZE(mmap), + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + }), +}; diff --git a/product/rddaniel/scp_ramfw/config_cmn_rhodes.c b/product/rddaniel/scp_ramfw/config_cmn_rhodes.c new file mode 100644 index 00000000..2cd2d7ae --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_cmn_rhodes.c @@ -0,0 +1,121 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_macros.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_cmn_rhodes.h> +#include <scp_rddaniel_mmap.h> +#include <config_clock.h> + +/* + * CMN_RHODES nodes + */ +#define DMC0_ID 12 +#define DMC1_ID 136 +#define DMC2_ID 28 +#define DMC3_ID 152 +#define NODE_ID_HND 4 +#define NODE_ID_SBSX 0 + +static const unsigned int snf_table[] = { + DMC0_ID, /* Maps to HN-F logical node 0 */ + DMC0_ID, /* Maps to HN-F logical node 1 */ + DMC0_ID, /* Maps to HN-F logical node 2 */ + DMC0_ID, /* Maps to HN-F logical node 3 */ + DMC1_ID, /* Maps to HN-F logical node 0 */ + DMC1_ID, /* Maps to HN-F logical node 1 */ + DMC1_ID, /* Maps to HN-F logical node 2 */ + DMC1_ID, /* Maps to HN-F logical node 3 */ + DMC2_ID, /* Maps to HN-F logical node 0 */ + DMC2_ID, /* Maps to HN-F logical node 1 */ + DMC2_ID, /* Maps to HN-F logical node 2 */ + DMC2_ID, /* Maps to HN-F logical node 3 */ + DMC3_ID, /* Maps to HN-F logical node 0 */ + DMC3_ID, /* Maps to HN-F logical node 1 */ + DMC3_ID, /* Maps to HN-F logical node 2 */ + DMC3_ID, /* Maps to HN-F logical node 3 */ +}; + +static const struct mod_cmn_rhodes_mem_region_map mmap[] = { + { + /* + * System cache backed region + * Map: 0x0000_0000_0000 - 0x003F_FFFFF_FFFF (4 TB) + */ + .base = UINT64_C(0x000000000000), + .size = UINT64_C(4) * FWK_TIB, + .type = MOD_CMN_RHODES_MEM_REGION_TYPE_SYSCACHE, + }, + { + /* + * Boot region + * Map: 0x0000_0000_0000 - 0x0000_0001_FFFF (128 MB) + */ + .base = UINT64_C(0x000000000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_RHODES_REGION_TYPE_SYSCACHE_SUB, + .node_id = NODE_ID_SBSX, + }, + { + /* + * Peripherals + * Map: 0x00_0800_0000 - 0x00_0FFF_FFFF (128 MB) + */ + .base = UINT64_C(0x0008000000), + .size = UINT64_C(128) * FWK_MIB, + .type = MOD_CMN_RHODES_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_1000_0000 - 0x00_1FFF_FFFF (256 MB) + */ + .base = UINT64_C(0x0010000000), + .size = UINT64_C(256) * FWK_MIB, + .type = MOD_CMN_RHODES_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_2000_0000 - 0x00_3FFF_FFFF (512 MB) + */ + .base = UINT64_C(0x0020000000), + .size = UINT64_C(512) * FWK_MIB, + .type = MOD_CMN_RHODES_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, + { + /* + * Peripherals + * Map: 0x00_4000_0000 - 0x00_7FFF_FFFF (1 GB) + */ + .base = UINT64_C(0x0040000000), + .size = UINT64_C(1) * FWK_GIB, + .type = MOD_CMN_RHODES_MEM_REGION_TYPE_IO, + .node_id = NODE_ID_HND, + }, +}; + +const struct fwk_module_config config_cmn_rhodes = { + .get_element_table = NULL, + .data = &((struct mod_cmn_rhodes_config) { + .base = SCP_CMN_RHODES_BASE, + .mesh_size_x = 3, + .mesh_size_y = 5, + .hnd_node_id = NODE_ID_HND, + .snf_table = snf_table, + .snf_count = FWK_ARRAY_SIZE(snf_table), + .mmap_table = mmap, + .mmap_count = FWK_ARRAY_SIZE(mmap), + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT), + .hnf_cal_mode = true, + }), +}; diff --git a/product/rddaniel/scp_ramfw/config_css_clock.c b/product/rddaniel/scp_ramfw/config_css_clock.c new file mode 100644 index 00000000..0f0bb849 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_css_clock.c @@ -0,0 +1,1247 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_id.h> +#include <fwk_macros.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_css_clock.h> +#include <mod_system_pll.h> +#include <mod_pik_clock.h> +#include <scp_rddaniel_pik.h> +#include <config_clock.h> + +static const struct mod_css_clock_rate rate_table_cpu_group_0[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_1[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_2[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_3[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_4[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_5[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_6[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_7[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_8[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_9[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_10[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_11[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_12[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_13[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_14[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const struct mod_css_clock_rate rate_table_cpu_group_15[] = { + { + /* Super Underdrive */ + .rate = 1313 * FWK_MHZ, + .pll_rate = 1313 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Underdrive */ + .rate = 1531 * FWK_MHZ, + .pll_rate = 1531 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Nominal */ + .rate = 1750 * FWK_MHZ, + .pll_rate = 1750 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Overdrive */ + .rate = 2100 * FWK_MHZ, + .pll_rate = 2100 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, + { + /* Super Overdrive */ + .rate = 2600 * FWK_MHZ, + .pll_rate = 2600 * FWK_MHZ, + .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .clock_div = 1, + .clock_mod_numerator = 1, + .clock_mod_denominator = 1, + }, +}; + +static const fwk_id_t member_table_cpu_group_0[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), +}; + +static const fwk_id_t member_table_cpu_group_1[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_2[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS2_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_3[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS3_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_4[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS4_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_5[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS5_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_6[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS6_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_7[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS7_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_8[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS8_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_9[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS9_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_10[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS10_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_11[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS11_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_12[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS12_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_13[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS13_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_14[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS14_CPU0), +}; + +static const fwk_id_t rddaniel_member_table_cpu_group_15[] = { + FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS15_CPU0), +}; + +static const struct fwk_element css_clock_element_table[] = { + [CLOCK_CSS_IDX_CPU_GROUP0] = { + .name = "CPU_GROUP_0", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_0, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU0), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_0, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP1] = { + .name = "CPU_GROUP_1", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_1, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU1), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = member_table_cpu_group_1, + .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_1), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP2] = { + .name = "CPU_GROUP_2", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_2, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_2), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU2), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_2, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_2), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP3] = { + .name = "CPU_GROUP_3", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_3, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_3), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU3), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_3, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_3), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP4] = { + .name = "CPU_GROUP_4", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_4, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_4), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU4), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_4, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_4), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP5] = { + .name = "CPU_GROUP_5", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_5, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_5), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU5), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_5, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_5), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP6] = { + .name = "CPU_GROUP_6", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_6, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_6), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU6), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_6, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_6), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP7] = { + .name = "CPU_GROUP_7", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_7, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_7), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU7), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_7, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_7), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP8] = { + .name = "CPU_GROUP_8", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_8, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_8), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU8), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_8, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_8), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP9] = { + .name = "CPU_GROUP_9", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_9, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_9), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU9), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_9, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_9), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP10] = { + .name = "CPU_GROUP_10", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_10, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_10), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU10), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_10, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_10), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP11] = { + .name = "CPU_GROUP_11", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_11, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_11), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU11), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_11, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_11), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP12] = { + .name = "CPU_GROUP_12", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_12, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_12), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU12), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_12, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_12), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP13] = { + .name = "CPU_GROUP_13", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_13, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_13), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU13), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_13, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_13), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP14] = { + .name = "CPU_GROUP_14", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_14, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_14), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU14), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_14, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_14), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_CPU_GROUP15] = { + .name = "CPU_GROUP_15", + .data = &((struct mod_css_clock_dev_config) { + .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, + .rate_table = rate_table_cpu_group_15, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_15), + .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK, + .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + CLOCK_PLL_IDX_CPU15), + .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL, + MOD_SYSTEM_PLL_API_TYPE_DEFAULT), + .member_table = rddaniel_member_table_cpu_group_15, + .member_count = FWK_ARRAY_SIZE(rddaniel_member_table_cpu_group_15), + .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK, + MOD_PIK_CLOCK_API_TYPE_CSS), + .initial_rate = 2600 * FWK_MHZ, + .modulation_supported = true, + }), + }, + [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *css_clock_get_element_table + (fwk_id_t module_id) +{ + return css_clock_element_table; +} + +const struct fwk_module_config config_css_clock = { + .get_element_table = css_clock_get_element_table, +}; diff --git a/product/rddaniel/scp_ramfw/config_log.c b/product/rddaniel/scp_ramfw/config_log.c new file mode 100644 index 00000000..193f1c21 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_log.c @@ -0,0 +1,58 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_banner.h> +#include <fwk_macros.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_log.h> +#include <mod_pl011.h> +#include <scp_rddaniel_mmap.h> + +/* + * PL011 module + */ +static const struct fwk_element pl011_element_desc_table[] = { + [0] = { + .name = "scp-uart1", + .data = &((struct mod_pl011_device_config) { + .reg_base = SCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + .clock_id = FWK_ID_NONE_INIT, + }), + }, + [1] = { 0 }, +}; + +static const struct fwk_element *get_pl011_table(fwk_id_t module_id) +{ + return pl011_element_desc_table; +} + +struct fwk_module_config config_pl011 = { + .get_element_table = get_pl011_table, +}; + +/* + * Log module + */ +static const struct mod_log_config log_data = { + .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0), + .log_groups = MOD_LOG_GROUP_ERROR | + MOD_LOG_GROUP_INFO | + MOD_LOG_GROUP_WARNING | + MOD_LOG_GROUP_DEBUG, + .banner = FWK_BANNER_SCP + FWK_BANNER_RAM_FIRMWARE + BUILD_VERSION_DESCRIBE_STRING "\n", +}; + +struct fwk_module_config config_log = { + .data = &log_data, +}; diff --git a/product/rddaniel/scp_ramfw/config_mhu2.c b/product/rddaniel/scp_ramfw/config_mhu2.c new file mode 100644 index 00000000..5b0f3bb5 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_mhu2.c @@ -0,0 +1,47 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_id.h> +#include <fwk_module.h> +#include <mod_mhu2.h> +#include <scp_rddaniel_irq.h> +#include <scp_rddaniel_mmap.h> +#include <scp_rddaniel_mhu.h> + +static const struct fwk_element mhu_element_table[] = { + [SCP_RDDANIEL_MHU_DEVICE_IDX_SCP_AP_S_CLUS0] = { + .name = "MHU_SCP_AP_S", + .sub_element_count = 1, + .data = &((struct mod_mhu2_channel_config) { + .irq = MHU_AP_SEC_IRQ, + .recv = SCP_MHU_SCP_AP_RCV_S_CLUS0, + .send = SCP_MHU_SCP_AP_SND_S_CLUS0, + .channel = 0, + }) + }, + [SCP_RDDANIEL_MHU_DEVICE_IDX_SCP_AP_NS_CLUS0] = { + .name = "MHU_SCP_AP_NS", + .sub_element_count = 1, + .data = &((struct mod_mhu2_channel_config) { + .irq = MHU_AP_NONSEC_IRQ, + .recv = SCP_MHU_SCP_AP_RCV_NS_CLUS0, + .send = SCP_MHU_SCP_AP_SND_NS_CLUS0, + .channel = 0, + }) + }, + [SCP_RDDANIEL_MHU_DEVICE_IDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *mhu_get_element_table(fwk_id_t module_id) +{ + return mhu_element_table; +} + +const struct fwk_module_config config_mhu2 = { + .get_element_table = mhu_get_element_table, +}; diff --git a/product/rddaniel/scp_ramfw/config_mock_psu.c b/product/rddaniel/scp_ramfw/config_mock_psu.c new file mode 100644 index 00000000..3c72b9ad --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_mock_psu.c @@ -0,0 +1,39 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_module.h> +#include <mod_mock_psu.h> + +static const struct fwk_element element_table[] = { + { + .name = "DVFS_GROUP0", + .data = + &(const struct mod_mock_psu_device_config){ + .default_enabled = true, + .default_voltage = 100, + }, + }, + { + .name = "DVFS_GROUP1", + .data = + &(const struct mod_mock_psu_device_config){ + .default_enabled = true, + .default_voltage = 100, + }, + }, + { 0 } +}; + +static const struct fwk_element *get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +const struct fwk_module_config config_mock_psu = { + .get_element_table = get_element_table, +}; diff --git a/product/rddaniel/scp_ramfw/config_pik_clock.c b/product/rddaniel/scp_ramfw/config_pik_clock.c new file mode 100644 index 00000000..a10fcfe7 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_pik_clock.c @@ -0,0 +1,519 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_id.h> +#include <fwk_macros.h> +#include <fwk_module.h> +#include <mod_pik_clock.h> +#include <rddaniel_pik_system.h> +#include <scp_rddaniel_pik.h> +#include <system_clock.h> +#include <config_clock.h> + +/* + * Rate lookup tables + */ + +static struct mod_pik_clock_rate rate_table_cpu_group_0[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_1[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_2[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_3[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; +static struct mod_pik_clock_rate rate_table_cpu_group_4[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_5[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_6[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_7[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_8[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_9[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_10[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_11[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_12[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_13[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_14[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static struct mod_pik_clock_rate rate_table_cpu_group_15[] = { + { + .rate = 2600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, /* Rate adjusted via CPU PLL */ + }, +}; + +static const struct mod_pik_clock_rate rate_table_sys_intclk[] = { + { + .rate = 2000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_INTCLK_SOURCE_INTPLL, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static const struct mod_pik_clock_rate rate_table_sys_dmcclk[] = { + { + .rate = 1600 * FWK_MHZ, + .source = MOD_PIK_CLOCK_DMCCLK_SOURCE_DDRPLL, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, + .divider = 1, + }, +}; + +static const struct mod_pik_clock_rate rate_table_scp[] = { + { + .rate = 250 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (250 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_gicclk[] = { + { + .rate = 1000 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (1000 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_pclkscp[] = { + { + .rate = 400 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (400 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_sysperclk[] = { + { + .rate = 500 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (500 * FWK_MHZ), + }, +}; + +static const struct mod_pik_clock_rate rate_table_uartclk[] = { + { + .rate = 250 * FWK_MHZ, + .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, + .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, + .divider = CLOCK_RATE_SYSPLLCLK / (250 * FWK_MHZ), + }, +}; + +static const struct fwk_element pik_clock_element_table[] = { + /* + * Cluster 0 CPUS + */ + [CLOCK_PIK_IDX_CLUS0_CPU0] = { + .name = "CLUS0_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(0)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(0)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(0)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_0, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0), + }), + }, + [CLOCK_PIK_IDX_CLUS1_CPU0] = { + .name = "CLUS1_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(1)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(1)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(0)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_0, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1), + }), + }, + [CLOCK_PIK_IDX_CLUS2_CPU0] = { + .name = "CLUS2_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(2)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(2)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(2)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_2, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_2), + }), + }, + [CLOCK_PIK_IDX_CLUS3_CPU0] = { + .name = "CLUS3_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(3)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(3)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(3)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_3, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_3), + }), + }, + [CLOCK_PIK_IDX_CLUS4_CPU0] = { + .name = "CLUS4_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(4)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(4)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(4)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_4, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_4), + }), + }, + [CLOCK_PIK_IDX_CLUS5_CPU0] = { + .name = "CLUS5_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(5)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(5)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(5)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_5, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_5), + }), + }, + [CLOCK_PIK_IDX_CLUS6_CPU0] = { + .name = "CLUS6_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(6)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(6)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(6)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_6, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_6), + }), + }, + [CLOCK_PIK_IDX_CLUS7_CPU0] = { + .name = "CLUS7_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(7)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(7)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(7)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_7, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_7), + }), + }, + [CLOCK_PIK_IDX_CLUS8_CPU0] = { + .name = "CLUS8_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(8)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(8)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(8)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_8, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_8), + }), + }, + [CLOCK_PIK_IDX_CLUS9_CPU0] = { + .name = "CLUS9_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(9)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(9)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(9)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_9, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_9), + }), + }, + [CLOCK_PIK_IDX_CLUS10_CPU0] = { + .name = "CLUS10_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(10)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(10)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(10)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_10, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_10), + }), + }, + [CLOCK_PIK_IDX_CLUS11_CPU0] = { + .name = "CLUS11_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(11)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(11)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(11)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_11, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_11), + }), + }, + [CLOCK_PIK_IDX_CLUS12_CPU0] = { + .name = "CLUS12_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(12)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(12)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(12)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_12, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_12), + }), + }, + [CLOCK_PIK_IDX_CLUS13_CPU0] = { + .name = "CLUS13_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(13)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(13)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(13)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_13, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_13), + }), + }, + [CLOCK_PIK_IDX_CLUS14_CPU0] = { + .name = "CLUS14_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(14)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(14)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(14)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_14, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_14), + }), + }, + [CLOCK_PIK_IDX_CLUS15_CPU0] = { + .name = "CLUS15_CPU0", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_CLUSTER, + .is_group_member = true, + .control_reg = &PIK_CLUSTER(15)->CORECLK[0].CTRL, + .divext_reg = &PIK_CLUSTER(15)->CORECLK[0].DIV, + .modulator_reg = &PIK_CLUSTER(15)->CORECLK[0].MOD, + .rate_table = rate_table_cpu_group_15, + .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_15), + }), + }, + [CLOCK_PIK_IDX_DMC] = { + .name = "DMC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->DMCCLK_CTRL, + .divext_reg = &PIK_SYSTEM->DMCCLK_DIV1, + .rate_table = rate_table_sys_dmcclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sys_dmcclk), + .initial_rate = 1600 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_INTERCONNECT] = { + .name = "INTERCONNECT", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->INTCLK_CTRL, + .divext_reg = &PIK_SYSTEM->INTCLK_DIV1, + .rate_table = rate_table_sys_intclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sys_intclk), + .initial_rate = 2000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_SCP] = { + .name = "SCP", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SCP->CORECLK_CTRL, + .divsys_reg = &PIK_SCP->CORECLK_DIV1, + .rate_table = rate_table_scp, + .rate_count = FWK_ARRAY_SIZE(rate_table_scp), + .initial_rate = 250 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_GIC] = { + .name = "GIC", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->GICCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->GICCLK_DIV1, + .rate_table = rate_table_gicclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk), + .initial_rate = 1000 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_PCLKSCP] = { + .name = "PCLKSCP", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->PCLKSCP_CTRL, + .divsys_reg = &PIK_SYSTEM->PCLKSCP_DIV1, + .rate_table = rate_table_pclkscp, + .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp), + .initial_rate = 400 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_SYSPERCLK] = { + .name = "SYSPERCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->SYSPERCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->SYSPERCLK_DIV1, + .rate_table = rate_table_sysperclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_sysperclk), + .initial_rate = 500 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_UARTCLK] = { + .name = "UARTCLK", + .data = &((struct mod_pik_clock_dev_config) { + .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, + .is_group_member = false, + .control_reg = &PIK_SYSTEM->UARTCLK_CTRL, + .divsys_reg = &PIK_SYSTEM->UARTCLK_DIV1, + .rate_table = rate_table_uartclk, + .rate_count = FWK_ARRAY_SIZE(rate_table_uartclk), + .initial_rate = 250 * FWK_MHZ, + }), + }, + [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *pik_clock_get_element_table + (fwk_id_t module_id) +{ + return pik_clock_element_table; +} + +const struct fwk_module_config config_pik_clock = { + .get_element_table = pik_clock_get_element_table, +}; diff --git a/product/rddaniel/scp_ramfw/config_power_domain.c b/product/rddaniel/scp_ramfw/config_power_domain.c new file mode 100644 index 00000000..4b533a4d --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_power_domain.c @@ -0,0 +1,414 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdio.h> +#include <stdint.h> +#include <string.h> +#include <fwk_element.h> +#include <fwk_macros.h> +#include <fwk_mm.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_system_power.h> +#include <mod_power_domain.h> +#include <mod_ppu_v1.h> +#include <rddaniel_power_domain.h> +#include <rddaniel_core.h> +#include <config_ppu_v0.h> +#include <config_power_domain.h> + +/* Maximum power domain name size including the null terminator */ +#define PD_NAME_SIZE 12 + +/* Mask of the allowed states for the systop power domain */ +static const uint32_t systop_allowed_state_mask_table[] = { + [0] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK | + (1 << MOD_SYSTEM_POWER_POWER_STATE_SLEEP0) | + (1 << MOD_SYSTEM_POWER_POWER_STATE_SLEEP1) +}; + +/* + * Mask of the allowed states for the top level power domains + * (but the cluster power domains) depending on the system states. + */ +static const uint32_t toplevel_allowed_state_mask_table[] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = MOD_PD_STATE_OFF_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP1] = MOD_PD_STATE_OFF_MASK +}; + +/* + * Mask of the allowed states for the cluster power domain depending on the + * system states. + * + * While the clusters may reach a SLEEP state, SLEEP does not appear in this + * table. This is because the PPU driver backing the clusters will not accept a + * manual SLEEP request, but will transition to it automatically when possible. + */ +static const uint32_t cluster_pd_allowed_state_mask_table[] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, + [MOD_PD_STATE_ON] = + RDDANIEL_CLUSTER_VALID_STATE_MASK & (~MOD_PD_STATE_SLEEP_MASK), + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = MOD_PD_STATE_OFF_MASK, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP1] = MOD_PD_STATE_OFF_MASK +}; + +/* Mask of the allowed states for a core depending on the cluster states. */ +static const uint32_t core_pd_allowed_state_mask_table[] = { + [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK, + [MOD_PD_STATE_ON] = RDDANIEL_CORE_VALID_STATE_MASK, + [MOD_PD_STATE_SLEEP] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK, + [RDDANIEL_POWER_DOMAIN_STATE_FUNC_RET] = RDDANIEL_CORE_VALID_STATE_MASK, + [RDDANIEL_POWER_DOMAIN_STATE_MEM_RET] = MOD_PD_STATE_OFF_MASK +}; + +/* Power module specific configuration data (none) */ +static const struct mod_power_domain_config + rddaniel_power_domain_config = { 0 }; + +static struct fwk_element rddaniel_power_domain_static_element_table[] = { + [PD_STATIC_DEV_IDX_CLUSTER0] = { + .name = "CLUS0", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER0, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER1] = { + .name = "CLUS1", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER1, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER2] = { + .name = "CLUS2", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER2, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER3] = { + .name = "CLUS3", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER3, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER4] = { + .name = "CLUS4", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER4, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER5] = { + .name = "CLUS5", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER5, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER6] = { + .name = "CLUS6", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER6, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER7] = { + .name = "CLUS7", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER7, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER8] = { + .name = "CLUS8", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER8, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER9] = { + .name = "CLUS9", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER9, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER10] = { + .name = "CLUS10", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER10, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER11] = { + .name = "CLUS11", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER11, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER12] = { + .name = "CLUS12", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER12, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER13] = { + .name = "CLUS13", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER13, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER14] = { + .name = "CLUS14", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER14, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_CLUSTER15] = { + .name = "CLUS15", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_CLUSTER, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_CLUSTER15, 0), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .allowed_state_mask_table = cluster_pd_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_DBGTOP] = { + .name = "DBGTOP", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_DEVICE_DEBUG, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_1, 0, 0, PD_STATIC_DEV_IDX_DBGTOP, 0), + .driver_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_PPU_V0, PPU_V0_ELEMENT_IDX_DBGTOP), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V0, 0), + .allowed_state_mask_table = toplevel_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(toplevel_allowed_state_mask_table) + }), + }, + [PD_STATIC_DEV_IDX_SYSTOP] = { + .name = "SYSTOP", + .data = &((struct mod_power_domain_element_config) { + .attributes.pd_type = MOD_PD_TYPE_SYSTEM, + .tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_2, 0, 0, 0, 0), + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), + .api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SYSTEM_POWER, + MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), + .allowed_state_mask_table = systop_allowed_state_mask_table, + .allowed_state_mask_table_size = + FWK_ARRAY_SIZE(systop_allowed_state_mask_table) + }), + }, +}; + +/* + * Function definitions with internal linkage + */ +static const struct fwk_element *rddaniel_power_domain_get_element_table + (fwk_id_t module_id) +{ + struct fwk_element *element_table, *element; + struct mod_power_domain_element_config *pd_config_table, *pd_config; + unsigned int core_idx; + unsigned int cluster_idx; + unsigned int core_count; + unsigned int cluster_count; + unsigned int core_element_count = 0; + + core_count = rddaniel_core_get_core_count(); + cluster_count = rddaniel_core_get_cluster_count(); + + element_table = fwk_mm_calloc( + core_count + + FWK_ARRAY_SIZE(rddaniel_power_domain_static_element_table) + + 1, /* Terminator */ + sizeof(struct fwk_element)); + if (element_table == NULL) + return NULL; + + pd_config_table = fwk_mm_calloc(core_count, + sizeof(struct mod_power_domain_element_config)); + if (pd_config_table == NULL) + return NULL; + + for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) { + for (core_idx = 0; + core_idx < rddaniel_core_get_core_per_cluster_count(cluster_idx); + core_idx++) { + + element = &element_table[core_element_count]; + pd_config = &pd_config_table[core_element_count]; + + element->name = fwk_mm_alloc(PD_NAME_SIZE, 1); + if (element->name == NULL) + return NULL; + + snprintf((char *)element->name, PD_NAME_SIZE, "CLUS%uCORE%u", + cluster_idx, core_idx); + + element->data = pd_config; + + pd_config->attributes.pd_type = MOD_PD_TYPE_CORE; + pd_config->tree_pos = MOD_PD_TREE_POS( + MOD_PD_LEVEL_0, 0, 0, cluster_idx, core_idx); + pd_config->driver_id = + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, + core_element_count); + pd_config->api_id = FWK_ID_API( + FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER); + pd_config->allowed_state_mask_table = + core_pd_allowed_state_mask_table; + pd_config->allowed_state_mask_table_size = + FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table); + core_element_count++; + } + + /* Define the driver id for the cluster */ + pd_config = (struct mod_power_domain_element_config *) + rddaniel_power_domain_static_element_table[cluster_idx].data; + pd_config->driver_id = + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, + (core_count + cluster_idx)); + } + + memcpy(element_table + core_count, + rddaniel_power_domain_static_element_table, + sizeof(rddaniel_power_domain_static_element_table)); + + return element_table; +} + +/* + * Power module configuration data + */ +const struct fwk_module_config config_power_domain = { + .get_element_table = rddaniel_power_domain_get_element_table, + .data = &rddaniel_power_domain_config, +}; diff --git a/product/rddaniel/scp_ramfw/config_power_domain.h b/product/rddaniel/scp_ramfw/config_power_domain.h new file mode 100644 index 00000000..6e9d20b4 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_power_domain.h @@ -0,0 +1,41 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_POWER_DOMAIN_H +#define CONFIG_POWER_DOMAIN_H + +/* + * Power domain indices for the statically defined domains used for: + * - Indexing the domains in the rddaniel_power_domain_static_element_table + * - Indexing the SYSTOP children in the power domain tree + * + * When calculating a power domain element index, use the formula: + * core_count + pd_static_dev_idx + */ +enum pd_static_dev_idx { + PD_STATIC_DEV_IDX_CLUSTER0, + PD_STATIC_DEV_IDX_CLUSTER1, + PD_STATIC_DEV_IDX_CLUSTER2, + PD_STATIC_DEV_IDX_CLUSTER3, + PD_STATIC_DEV_IDX_CLUSTER4, + PD_STATIC_DEV_IDX_CLUSTER5, + PD_STATIC_DEV_IDX_CLUSTER6, + PD_STATIC_DEV_IDX_CLUSTER7, + PD_STATIC_DEV_IDX_CLUSTER8, + PD_STATIC_DEV_IDX_CLUSTER9, + PD_STATIC_DEV_IDX_CLUSTER10, + PD_STATIC_DEV_IDX_CLUSTER11, + PD_STATIC_DEV_IDX_CLUSTER12, + PD_STATIC_DEV_IDX_CLUSTER13, + PD_STATIC_DEV_IDX_CLUSTER14, + PD_STATIC_DEV_IDX_CLUSTER15, + PD_STATIC_DEV_IDX_DBGTOP, + PD_STATIC_DEV_IDX_SYSTOP, + PD_STATIC_DEV_IDX_COUNT +}; + +#endif /* CONFIG_POWER_DOMAIN_H */ diff --git a/product/rddaniel/scp_ramfw/config_ppu_v0.c b/product/rddaniel/scp_ramfw/config_ppu_v0.c new file mode 100644 index 00000000..44c0d73b --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_ppu_v0.c @@ -0,0 +1,37 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_module.h> +#include <mod_ppu_v0.h> +#include <config_ppu_v0.h> +#include <scp_rddaniel_irq.h> +#include <scp_rddaniel_mmap.h> + +static struct fwk_element ppu_v0_element_table[] = { + [PPU_V0_ELEMENT_IDX_DBGTOP] = { + .name = "DBGTOP", + .data = &((struct mod_ppu_v0_pd_config) { + .pd_type = MOD_PD_TYPE_DEVICE_DEBUG, + .ppu.reg_base = SCP_PPU_DEBUG_BASE, + }), + }, + [PPU_V0_ELEMENT_IDX_COUNT] = { 0 }, /* Termination entry */ +}; + + +static const struct fwk_element *ppu_v0_get_element_table(fwk_id_t module_id) +{ + return ppu_v0_element_table; +} + +/* + * Power module configuration data + */ +const struct fwk_module_config config_ppu_v0 = { + .get_element_table = ppu_v0_get_element_table, +}; diff --git a/product/rddaniel/scp_ramfw/config_ppu_v0.h b/product/rddaniel/scp_ramfw/config_ppu_v0.h new file mode 100644 index 00000000..7858b2b1 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_ppu_v0.h @@ -0,0 +1,16 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONFIG_PPU_V0_H +#define CONFIG_PPU_V0_H + +enum ppu_v0_element_idx { + PPU_V0_ELEMENT_IDX_DBGTOP, + PPU_V0_ELEMENT_IDX_COUNT +}; + +#endif /* CONFIG_PPU_V0_H */ diff --git a/product/rddaniel/scp_ramfw/config_ppu_v1.c b/product/rddaniel/scp_ramfw/config_ppu_v1.c new file mode 100644 index 00000000..01e9080a --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_ppu_v1.c @@ -0,0 +1,162 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <string.h> +#include <stdio.h> +#include <fwk_assert.h> +#include <fwk_element.h> +#include <fwk_macros.h> +#include <fwk_mm.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_cmn_rhodes.h> +#include <mod_power_domain.h> +#include <mod_ppu_v1.h> +#include <rddaniel_core.h> +#include <scp_rddaniel_irq.h> +#include <scp_rddaniel_mmap.h> +#include <config_power_domain.h> + +/* Maximum PPU core name size including the null terminator */ +#define PPU_CORE_NAME_SIZE 12 + +/* Maximum PPU cluster name size including the null terminator */ +#define PPU_CLUS_NAME_SIZE 6 + +/* Lookup table for translating cluster indicies into CMN RHODES node IDs */ +static const unsigned int cluster_idx_to_node_id[] = {24, 140, 8, 156, 16, 148, 64, 100, 25, 141, 9, 157, 17, 149, 65, 101}; + +/* Module configuration data */ +static struct mod_ppu_v1_config ppu_v1_config_data = { + .pd_notification_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_POWER_DOMAIN, + MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), +}; + +static struct fwk_element ppu_v1_system_element_table[] = { + [0] = { + .name = "SYS0", + .data = &((struct mod_ppu_v1_pd_config) { + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = SCP_PPU_SYS0_BASE, + .observer_id = FWK_ID_NONE_INIT, + }), + }, + [1] = { + .name = "SYS1", + .data = &((struct mod_ppu_v1_pd_config) { + .pd_type = MOD_PD_TYPE_SYSTEM, + .ppu.reg_base = SCP_PPU_SYS1_BASE, + .observer_id = FWK_ID_NONE_INIT, + }), + }, +}; + +static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) +{ + struct fwk_element *element_table, *element; + struct mod_ppu_v1_pd_config *pd_config_table, *pd_config; + unsigned int core_idx; + unsigned int cluster_idx; + unsigned int core_count; + unsigned int cluster_count; + unsigned int core_element_count = 0; + + core_count = rddaniel_core_get_core_count(); + cluster_count = rddaniel_core_get_cluster_count(); + + assert(cluster_count == FWK_ARRAY_SIZE(cluster_idx_to_node_id)); + + /* + * Allocate element descriptors based on: + * Number of cores + * + Number of cluster descriptors + * + Number of system power domain descriptors + * + 1 terminator descriptor + */ + element_table = fwk_mm_calloc(core_count + cluster_count + + FWK_ARRAY_SIZE(ppu_v1_system_element_table) + 1, + sizeof(struct fwk_element)); + if (element_table == NULL) + return NULL; + + pd_config_table = fwk_mm_calloc(core_count + cluster_count, + sizeof(struct mod_ppu_v1_pd_config)); + if (pd_config_table == NULL) + return NULL; + + for (cluster_idx = 0; cluster_idx < cluster_count; cluster_idx++) { + for (core_idx = 0; + core_idx < rddaniel_core_get_core_per_cluster_count(cluster_idx); + core_idx++) { + element = &element_table[core_element_count]; + pd_config = &pd_config_table[core_element_count]; + + element->name = fwk_mm_alloc(PPU_CORE_NAME_SIZE, 1); + if (element->name == NULL) + return NULL; + + snprintf((char *)element->name, PPU_CORE_NAME_SIZE, "CLUS%uCORE%u", + cluster_idx, core_idx); + + element->data = pd_config; + + pd_config->pd_type = MOD_PD_TYPE_CORE; + pd_config->ppu.reg_base = SCP_PPU_CORE_BASE(cluster_idx, core_idx); + pd_config->ppu.irq = FWK_INTERRUPT_NONE; + pd_config->cluster_id = + FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, + (core_count + cluster_idx)); + pd_config->observer_id = FWK_ID_NONE; + core_element_count++; + } + + element = &element_table[core_count + cluster_idx]; + pd_config = &pd_config_table[core_count + cluster_idx]; + + element->name = fwk_mm_alloc(PPU_CLUS_NAME_SIZE, 1); + if (element->name == NULL) + return NULL; + + snprintf((char *)element->name, PPU_CLUS_NAME_SIZE, "CLUS%u", + cluster_idx); + + element->data = pd_config; + + pd_config->pd_type = MOD_PD_TYPE_CLUSTER; + pd_config->ppu.reg_base = SCP_PPU_CLUSTER_BASE(cluster_idx); + pd_config->ppu.irq = FWK_INTERRUPT_NONE; + pd_config->observer_id = fwk_module_id_cmn_rhodes; + pd_config->observer_api = FWK_ID_API(FWK_MODULE_IDX_CMN_RHODES, + MOD_CMN_RHODES_API_IDX_PPU_OBSERVER); + pd_config->no_cluter_power_domain = true ; + pd_config->post_ppu_on_param = + (void *)&cluster_idx_to_node_id[cluster_idx]; + } + + memcpy(&element_table[core_count + cluster_count], + ppu_v1_system_element_table, + sizeof(ppu_v1_system_element_table)); + + /* + * Configure pd_source_id with the SYSTOP identifier from the power domain + * module which is dynamically defined based on the number of cores. + */ + ppu_v1_config_data.pd_source_id = fwk_id_build_element_id( + fwk_module_id_power_domain, + core_count + PD_STATIC_DEV_IDX_SYSTOP); + + return element_table; +} + +/* + * Power module configuration data + */ +const struct fwk_module_config config_ppu_v1 = { + .get_element_table = ppu_v1_get_element_table, + .data = &ppu_v1_config_data, +}; diff --git a/product/rddaniel/scp_ramfw/config_psu.c b/product/rddaniel/scp_ramfw/config_psu.c new file mode 100644 index 00000000..8c5740e5 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_psu.c @@ -0,0 +1,41 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_mock_psu.h> +#include <mod_psu.h> + +static const struct fwk_element element_table[] = { + { + .name = "DVFS_GROUP0", + .data = &(const struct mod_psu_device_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, 0), + .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_PSU_DRIVER) + }, + }, + { + .name = "DVFS_GROUP1", + .data = &(const struct mod_psu_device_config){ + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, 1), + .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MOCK_PSU, + MOD_MOCK_PSU_API_IDX_PSU_DRIVER) + }, + }, + { 0 } +}; + +static const struct fwk_element *psu_get_element_table(fwk_id_t module_id) +{ + return element_table; +} + +const struct fwk_module_config config_psu = { + .get_element_table = psu_get_element_table, +}; diff --git a/product/rddaniel/scp_ramfw/config_scmi.c b/product/rddaniel/scp_ramfw/config_scmi.c new file mode 100644 index 00000000..e95db37c --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_scmi.c @@ -0,0 +1,77 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_id.h> +#include <fwk_macros.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <scp_rddaniel_scmi.h> +#include <mod_scmi.h> +#include <internal/scmi.h> +#include <mod_smt.h> + +static const struct fwk_element service_table[] = { + [SCP_RDDANIEL_SCMI_SERVICE_IDX_PSCI] = { + .name = "SERVICE0", + .data = &((struct mod_scmi_service_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SMT, + SCP_RDDANIEL_SCMI_SERVICE_IDX_PSCI), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_API_IDX_SCMI_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_ID_PSCI, + }), + }, + [SCP_RDDANIEL_SCMI_SERVICE_IDX_OSPM] = { + .name = "SERVICE1", + .data = &((struct mod_scmi_service_config) { + .transport_id = FWK_ID_ELEMENT_INIT( + FWK_MODULE_IDX_SMT, + SCP_RDDANIEL_SCMI_SERVICE_IDX_OSPM), + .transport_api_id = FWK_ID_API_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_API_IDX_SCMI_TRANSPORT), + .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( + FWK_MODULE_IDX_SMT, + MOD_SMT_NOTIFICATION_IDX_INITIALIZED), + .scmi_agent_id = SCP_SCMI_AGENT_ID_OSPM, + }), + }, + [SCP_RDDANIEL_SCMI_SERVICE_IDX_COUNT] = { 0 } +}; + +static const struct fwk_element *get_service_table(fwk_id_t module_id) +{ + return service_table; +} + +static struct mod_scmi_agent agent_table[] = { + [SCP_SCMI_AGENT_ID_OSPM] = { + .type = SCMI_AGENT_TYPE_OSPM, + .name = "OSPM", + }, + [SCP_SCMI_AGENT_ID_PSCI] = { + .type = SCMI_AGENT_TYPE_PSCI, + .name = "PSCI", + }, +}; + +const struct fwk_module_config config_scmi = { + .get_element_table = get_service_table, + .data = &((struct mod_scmi_config) { + .protocol_count_max = 9, + .agent_count = FWK_ARRAY_SIZE(agent_table) - 1, + .agent_table = agent_table, + .vendor_identifier = "arm", + .sub_vendor_identifier = "arm", + }), +}; diff --git a/product/rddaniel/scp_ramfw/config_scmi_apcore.c b/product/rddaniel/scp_ramfw/config_scmi_apcore.c new file mode 100644 index 00000000..995b988c --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_scmi_apcore.c @@ -0,0 +1,31 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <rddaniel_core.h> +#include <scp_rddaniel_pik.h> +#include <mod_scmi_apcore.h> +#include <fwk_element.h> +#include <fwk_macros.h> +#include <fwk_module.h> + +static const struct mod_scmi_apcore_reset_register_group + reset_reg_group_table[] = { + { + .base_register = + (uintptr_t)&PIK_CLUSTER(0)->STATIC_CONFIG[0].RVBARADDR_LW, + .register_count = RDDANIEL_CORE_PER_CLUSTER_MAX, + }, + }; + +const struct fwk_module_config config_scmi_apcore = { + .data = &((struct mod_scmi_apcore_config){ + .reset_register_width = MOD_SCMI_APCORE_REG_WIDTH_64, + .reset_register_group_count = + FWK_ARRAY_SIZE(reset_reg_group_table), + .reset_register_group_table = &reset_reg_group_table[0], + }), +}; diff --git a/product/rddaniel/scp_ramfw/config_scmi_system_power.c b/product/rddaniel/scp_ramfw/config_scmi_system_power.c new file mode 100644 index 00000000..a405c6f0 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_scmi_system_power.c @@ -0,0 +1,17 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_module.h> +#include <mod_scmi_system_power.h> +#include <mod_system_power.h> + +const struct fwk_module_config config_scmi_system_power = { + .data = &((struct mod_scmi_system_power_config) { + .system_view = MOD_SCMI_SYSTEM_VIEW_FULL, + .system_suspend_state = MOD_SYSTEM_POWER_POWER_STATE_SLEEP0 + }), +}; diff --git a/product/rddaniel/scp_ramfw/config_sds.c b/product/rddaniel/scp_ramfw/config_sds.c new file mode 100644 index 00000000..162ef37a --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_sds.c @@ -0,0 +1,102 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <fwk_assert.h> +#include <fwk_element.h> +#include <fwk_macros.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_sds.h> +#include <mod_sid.h> +#include <rddaniel_sds.h> +#include <scp_rddaniel_mmap.h> +#include <scp_rddaniel_pik.h> +#include <scp_software_mmap.h> +#include <scp_system_mmap.h> +#include <config_clock.h> + +static const uint32_t version_packed = FWK_BUILD_VERSION; +static const uint32_t feature_flags = 0x00000000; + +const struct mod_sds_config sds_module_config = { + .region_base_address = SCP_SDS_MEM_BASE, + .region_size = SCP_SDS_MEM_SIZE, + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT) +}; + +static struct fwk_element sds_element_table[] = { + { + .name = "CPU Info", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIEL_SDS_CPU_INFO, + .size = RDDANIEL_SDS_CPU_INFO_SIZE, + .finalize = true, + }), + }, + { + .name = "Firmware version", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIEL_SDS_FIRMWARE_VERSION, + .size = RDDANIEL_SDS_FIRMWARE_VERSION_SIZE, + .payload = &version_packed, + .finalize = true, + }), + }, + { + .name = "Reset Syndrome", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIEL_SDS_RESET_SYNDROME, + .size = RDDANIEL_SDS_RESET_SYNDROME_SIZE, + .payload = (void *)(&PIK_SCP->RESET_SYNDROME), + .finalize = true, + }), + }, + { + .name = "Feature Availability", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIEL_SDS_FEATURE_AVAILABILITY, + .size = RDDANIEL_SDS_FEATURE_AVAILABILITY_SIZE, + .payload = &feature_flags, + .finalize = true, + }), + }, +#ifdef BUILD_HAS_MOD_TEST + { + .name = "Boot Counters", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIEL_SDS_CPU_BOOTCTR, + .size = RDDANIEL_SDS_CPU_BOOTCTR_SIZE, + .finalize = true, + }), + }, + { + .name = "CPU Flags", + .data = &((struct mod_sds_structure_desc) { + .id = RDDANIEL_SDS_CPU_FLAGS, + .size = RDDANIEL_SDS_CPU_FLAGS_SIZE, + .finalize = true, + }), + }, +#endif + { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *sds_get_element_table(fwk_id_t module_id) +{ + static_assert(BUILD_VERSION_MAJOR < UINT8_MAX, "Invalid version size"); + static_assert(BUILD_VERSION_MINOR < UINT8_MAX, "Invalid version size"); + static_assert(BUILD_VERSION_PATCH < UINT16_MAX, "Invalid version size"); + + return sds_element_table; +} + +struct fwk_module_config config_sds = { + .get_element_table = sds_get_element_table, + .data = &sds_module_config, +}; diff --git a/product/rddaniel/scp_ramfw/config_sensor.c b/product/rddaniel/scp_ramfw/config_sensor.c new file mode 100644 index 00000000..3a1a0719 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_sensor.c @@ -0,0 +1,71 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_reg_sensor.h> +#include <mod_sensor.h> +#include <scp_system_mmap.h> + +enum REG_SENSOR_DEVICES { + REG_SENSOR_DEV_SOC_TEMP, + REG_SENSOR_DEV_COUNT, +}; + +/* + * Register Sensor driver config + */ +static struct mod_sensor_info info_soc_temperature = { + .type = MOD_SENSOR_TYPE_DEGREES_C, + .update_interval = 0, + .update_interval_multiplier = 0, + .unit_multiplier = 0, +}; + +static const struct fwk_element reg_sensor_element_table[] = { + [REG_SENSOR_DEV_SOC_TEMP] = { + .name = "Soc Temperature", + .data = &((struct mod_reg_sensor_dev_config) { + .reg = (uintptr_t)(SCP_SENSOR_SOC_TEMP), + .info = &info_soc_temperature, + }), + }, + [REG_SENSOR_DEV_COUNT] = { 0 }, +}; + +static const struct fwk_element *get_reg_sensor_element_table(fwk_id_t id) +{ + return reg_sensor_element_table; +} + +struct fwk_module_config config_reg_sensor = { + .get_element_table = get_reg_sensor_element_table, +}; + +/* + * Sensor module config + */ +static const struct fwk_element sensor_element_table[] = { + [0] = { + .name = "Soc Temperature", + .data = &((const struct mod_sensor_dev_config) { + .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_REG_SENSOR, + REG_SENSOR_DEV_SOC_TEMP), + }), + }, + [1] = { 0 }, +}; + +static const struct fwk_element *get_sensor_element_table(fwk_id_t module_id) +{ + return sensor_element_table; +} + +const struct fwk_module_config config_sensor = { + .get_element_table = get_sensor_element_table, +}; diff --git a/product/rddaniel/scp_ramfw/config_smt.c b/product/rddaniel/scp_ramfw/config_smt.c new file mode 100644 index 00000000..9cf966ce --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_smt.c @@ -0,0 +1,64 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> +#include <fwk_element.h> +#include <fwk_id.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_smt.h> +#include <rddaniel_core.h> +#include <scp_rddaniel_mhu.h> +#include <scp_rddaniel_scmi.h> +#include <scp_software_mmap.h> +#include <config_power_domain.h> + +static const struct fwk_element smt_element_table[] = { + [SCP_RDDANIEL_SCMI_SERVICE_IDX_PSCI] = { + .name = "PSCI", + .data = &((struct mod_smt_channel_config) { + .type = MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = MOD_SMT_POLICY_INIT_MAILBOX | MOD_SMT_POLICY_SECURE, + .mailbox_address = (uintptr_t)SCP_SCMI_PAYLOAD_S_A2P_BASE, + .mailbox_size = SCP_SCMI_PAYLOAD_SIZE, + .driver_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_MHU2, + SCP_RDDANIEL_MHU_DEVICE_IDX_SCP_AP_S_CLUS0, 0), + .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MHU2, 0), + }) + }, + [SCP_RDDANIEL_SCMI_SERVICE_IDX_OSPM] = { + .name = "OSPM", + .data = &((struct mod_smt_channel_config) { + .type = MOD_SMT_CHANNEL_TYPE_SLAVE, + .policies = MOD_SMT_POLICY_INIT_MAILBOX, + .mailbox_address = (uintptr_t)SCP_SCMI_PAYLOAD_NS_A2P_BASE, + .mailbox_size = SCP_SCMI_PAYLOAD_SIZE, + .driver_id = FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_MHU2, + SCP_RDDANIEL_MHU_DEVICE_IDX_SCP_AP_NS_CLUS0, 0), + .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MHU2, 0), + }) + }, + [SCP_RDDANIEL_SCMI_SERVICE_IDX_COUNT] = { 0 }, +}; + +static const struct fwk_element *smt_get_element_table(fwk_id_t module_id) +{ + unsigned int idx; + struct mod_smt_channel_config *config; + + for (idx = 0; idx < SCP_RDDANIEL_SCMI_SERVICE_IDX_COUNT; idx++) { + config = (struct mod_smt_channel_config *)(smt_element_table[idx].data); + config->pd_source_id = FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, + rddaniel_core_get_core_count() + PD_STATIC_DEV_IDX_SYSTOP); + } + + return smt_element_table; +} + +const struct fwk_module_config config_smt = { + .get_element_table = smt_get_element_table, +}; diff --git a/product/rddaniel/scp_ramfw/config_system_pll.c b/product/rddaniel/scp_ramfw/config_system_pll.c new file mode 100644 index 00000000..1b96a372 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_system_pll.c @@ -0,0 +1,258 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_id.h> +#include <fwk_macros.h> +#include <fwk_module.h> +#include <mod_system_pll.h> +#include <rddaniel_pik_scp.h> +#include <scp_rddaniel_pik.h> +#include <scp_system_mmap.h> +#include <config_clock.h> + +static const struct fwk_element system_pll_element_table[] = { + [CLOCK_PLL_IDX_CPU0] = { + .name = "CPU_PLL_0", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU0, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU1] = { + .name = "CPU_PLL_1", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU1, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(1), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU2] = { + .name = "CPU_PLL_2", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU2, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(2), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU3] = { + .name = "CPU_PLL_3", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU3, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(3), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU4] = { + .name = "CPU_PLL_4", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU4, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(4), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU5] = { + .name = "CPU_PLL_5", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU5, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(5), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU6] = { + .name = "CPU_PLL_6", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU6, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(6), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU7] = { + .name = "CPU_PLL_7", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU7, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(7), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU8] = { + .name = "CPU_PLL_8", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU8, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(8), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU9] = { + .name = "CPU_PLL_9", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU9, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(9), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU10] = { + .name = "CPU_PLL_10", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU10, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(10), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU11] = { + .name = "CPU_PLL_11", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU11, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(11), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU12] = { + .name = "CPU_PLL_12", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU12, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(12), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU13] = { + .name = "CPU_PLL_13", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU13, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(13), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU14] = { + .name = "CPU_PLL_14", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU14, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(14), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_CPU15] = { + .name = "CPU_PLL_15", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_CPU15, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[1], + .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(15), + .initial_rate = 2600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_SYS] = { + .name = "SYS_PLL", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_SYSPLL, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_DMC] = { + .name = "DMC_PLL", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_DMC, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_DDRPLLLOCK, + .initial_rate = 1600 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_INTERCONNECT] = { + .name = "INT_PLL", + .data = &((struct mod_system_pll_dev_config) { + .control_reg = (void *)SCP_PLL_INTERCONNECT, + .status_reg = (void *)&PIK_SCP->PLL_STATUS[0], + .lock_flag_mask = PLL_STATUS_0_INTPLLLOCK, + .initial_rate = 2000 * FWK_MHZ, + .min_rate = MOD_SYSTEM_PLL_MIN_RATE, + .max_rate = MOD_SYSTEM_PLL_MAX_RATE, + .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, + }), + }, + [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ +}; + +static const struct fwk_element *system_pll_get_element_table + (fwk_id_t module_id) +{ + return system_pll_element_table; +} + +const struct fwk_module_config config_system_pll = { + .get_element_table = system_pll_get_element_table, +}; diff --git a/product/rddaniel/scp_ramfw/config_system_power.c b/product/rddaniel/scp_ramfw/config_system_power.c new file mode 100644 index 00000000..b0cd0fb2 --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_system_power.c @@ -0,0 +1,88 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_id.h> +#include <fwk_macros.h> +#include <fwk_mm.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <scp_rddaniel_irq.h> +#include <mod_rddaniel_system.h> +#include <mod_system_power.h> +#include <mod_ppu_v1.h> +#include <rddaniel_core.h> + +static const uint8_t system_power_to_sys_ppu0_state[] = { + [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_OFF, + [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, +}; + +static const uint8_t system_power_to_sys_ppu1_state[] = { + [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, + [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_ON, + [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, +}; + +static struct fwk_element system_power_element_table[] = { + [0] = { + .name = "SYS-PPU-0", + .data = &((struct mod_system_power_dev_config) { + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .sys_state_table = system_power_to_sys_ppu0_state, + }), + }, + + [1] = { + .name = "SYS-PPU-1", + .data = &((struct mod_system_power_dev_config) { + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PPU_V1, + MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), + .sys_state_table = system_power_to_sys_ppu1_state, + }), + }, + + [2] = { 0 }, /* Termination description */ +}; + +static struct mod_system_power_config system_power_config = { + .soc_wakeup_irq = SOC_WAKEUP0_IRQ, + + /* System driver */ + .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_RDDANIEL_SYSTEM), + .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_RDDANIEL_SYSTEM, + MOD_RDDANIEL_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER), + + /* Initial system state */ + .initial_system_power_state = MOD_PD_STATE_OFF, +}; + +static const struct fwk_element *rddaniel_system_get_element_table( + fwk_id_t unused) +{ + struct mod_system_power_dev_config *dev_config_table; + unsigned int i; + + /* The system PPUs are placed after the core and cluster PPUs */ + unsigned int ppu_idx_base = rddaniel_core_get_core_count() + + rddaniel_core_get_cluster_count(); + + for (i = 0; i < (FWK_ARRAY_SIZE(system_power_element_table) - 1); i++) { + dev_config_table = (struct mod_system_power_dev_config *) + system_power_element_table[i].data; + dev_config_table->sys_ppu_id = + fwk_id_build_element_id(fwk_module_id_ppu_v1, ppu_idx_base + i); + } + + return system_power_element_table; +} + +const struct fwk_module_config config_system_power = { + .get_element_table = rddaniel_system_get_element_table, + .data = &system_power_config, +}; diff --git a/product/rddaniel/scp_ramfw/config_timer.c b/product/rddaniel/scp_ramfw/config_timer.c new file mode 100644 index 00000000..abfa8b1e --- /dev/null +++ b/product/rddaniel/scp_ramfw/config_timer.c @@ -0,0 +1,67 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_id.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_gtimer.h> +#include <mod_timer.h> +#include <scp_rddaniel_irq.h> +#include <scp_rddaniel_mmap.h> +#include <system_clock.h> +#include <config_clock.h> + +/* + * Generic timer driver config + */ +static const struct fwk_element gtimer_dev_table[] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_gtimer_dev_config) { + .hw_timer = SCP_REFCLK_CNTBASE0_BASE, + .hw_counter = SCP_REFCLK_CNTCTL_BASE, + .control = SCP_REFCLK_CNTCONTROL_BASE, + .frequency = CLOCK_RATE_REFCLK, + .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, + CLOCK_IDX_INTERCONNECT) + }) + }, + [1] = { 0 }, +}; + +static const struct fwk_element *gtimer_get_dev_table(fwk_id_t module_id) +{ + return gtimer_dev_table; +} + +const struct fwk_module_config config_gtimer = { + .get_element_table = gtimer_get_dev_table, +}; + +/* + * Timer HAL config + */ +static const struct fwk_element timer_dev_table[] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_timer_dev_config) { + .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), + .timer_irq = TIMREFCLK_IRQ, + }), + .sub_element_count = 8, /* Number of alarms */ + }, + [1] = { 0 }, +}; + +static const struct fwk_element *timer_get_dev_table(fwk_id_t module_id) +{ + return timer_dev_table; +} + +const struct fwk_module_config config_timer = { + .get_element_table = timer_get_dev_table, +}; diff --git a/product/rddaniel/scp_ramfw/firmware.mk b/product/rddaniel/scp_ramfw/firmware.mk new file mode 100644 index 00000000..fe76a657 --- /dev/null +++ b/product/rddaniel/scp_ramfw/firmware.mk @@ -0,0 +1,71 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := yes +BS_FIRMWARE_HAS_NOTIFICATION := yes +BS_FIRMWARE_MODULE_HEADERS_ONLY := + +BS_FIRMWARE_MODULES := \ + armv7m_mpu \ + sid \ + pcid \ + pl011 \ + log \ + cmn_rhodes \ + apcontext \ + power_domain \ + ppu_v0 \ + ppu_v1 \ + system_power \ + mhu2 \ + smt \ + scmi \ + sds \ + system_pll \ + pik_clock \ + css_clock \ + clock \ + gtimer \ + timer \ + sensor \ + reg_sensor \ + scmi_sensor \ + scmi_power_domain \ + scmi_system_power \ + scmi_apcore \ + mock_psu \ + psu \ + rddaniel_system + +BS_FIRMWARE_SOURCES := \ + config_system_power.c \ + config_sid.c \ + rtx_config.c \ + config_armv7m_mpu.c \ + config_log.c \ + config_power_domain.c \ + config_ppu_v0.c \ + config_ppu_v1.c \ + config_mhu2.c \ + config_smt.c \ + config_scmi.c \ + config_sds.c \ + config_timer.c \ + config_sensor.c \ + config_cmn_rhodes.c \ + config_scmi_system_power.c \ + config_system_pll.c \ + config_pik_clock.c \ + config_css_clock.c \ + config_clock.c \ + config_mock_psu.c \ + config_psu.c \ + config_scmi_apcore.c \ + config_apcontext.c + +include $(BS_DIR)/firmware.mk diff --git a/product/rddaniel/scp_ramfw/fmw_memory.ld.S b/product/rddaniel/scp_ramfw/fmw_memory.ld.S new file mode 100644 index 00000000..c80bdd29 --- /dev/null +++ b/product/rddaniel/scp_ramfw/fmw_memory.ld.S @@ -0,0 +1,32 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_LD_S +#define FMW_MEMORY_LD_S + +#include <scp_system_mmap_scp.h> + +#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FIRMWARE_MEM0_SIZE SCP_RAM0_SIZE +#define FIRMWARE_MEM0_BASE SCP_RAM0_BASE + +/* + * RAM data memory + */ +#define FIRMWARE_MEM1_SIZE SCP_RAM1_SIZE +#define FIRMWARE_MEM1_BASE SCP_RAM1_BASE + +#define FIRMWARE_STACK_SIZE (1 * 1024) + +#endif /* FMW_MEMORY_LD_S */ diff --git a/product/rddaniel/scp_ramfw/rtx_config.c b/product/rddaniel/scp_ramfw/rtx_config.c new file mode 100644 index 00000000..75f44c53 --- /dev/null +++ b/product/rddaniel/scp_ramfw/rtx_config.c @@ -0,0 +1,36 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <stdint.h> +#include <cmsis_compiler.h> +#include <rtx_os.h> +#include <system_clock.h> + +#include <rtx_lib.c> + +/* + * Required by RTX to configure the SysTick timer. + */ +uint32_t SystemCoreClock = CLOCK_RATE_REFCLK; + +/* + * Idle thread + */ +__NO_RETURN void osRtxIdleThread(void *argument) +{ + while (true) + __WFI(); +} + +/* + * OS error handler + */ +uint32_t osRtxErrorNotify(uint32_t code, void *object_id) +{ + osRtxIdleThread(object_id); +} diff --git a/product/rddaniel/scp_romfw/config_clock.c b/product/rddaniel/scp_romfw/config_clock.c new file mode 100644 index 00000000..a01a1d37 --- /dev/null +++ b/product/rddaniel/scp_romfw/config_clock.c @@ -0,0 +1,12 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_id.h> +#include <fwk_module.h> +#include <mod_clock.h> + +const struct fwk_module_config config_clock = { 0 }; diff --git a/product/rddaniel/scp_romfw/config_gtimer.c b/product/rddaniel/scp_romfw/config_gtimer.c new file mode 100644 index 00000000..8f56b27e --- /dev/null +++ b/product/rddaniel/scp_romfw/config_gtimer.c @@ -0,0 +1,38 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_id.h> +#include <fwk_module.h> +#include <mod_gtimer.h> +#include <scp_rddaniel_mmap.h> +#include <system_clock.h> + +/* + * Generic timer driver config + */ +static const struct fwk_element gtimer_dev_table[] = { + [0] = { + .name = "REFCLK", + .data = &((struct mod_gtimer_dev_config) { + .hw_timer = SCP_REFCLK_CNTBASE0_BASE, + .hw_counter = SCP_REFCLK_CNTCTL_BASE, + .control = SCP_REFCLK_CNTCONTROL_BASE, + .frequency = CLOCK_RATE_REFCLK, + .clock_id = FWK_ID_NONE_INIT, + }) + }, + [1] = { 0 }, +}; + +static const struct fwk_element *gtimer_get_dev_table(fwk_id_t module_id) +{ + return gtimer_dev_table; +} + +const struct fwk_module_config config_gtimer = { + .get_element_table = gtimer_get_dev_table, +}; diff --git a/product/rddaniel/scp_romfw/config_log.c b/product/rddaniel/scp_romfw/config_log.c new file mode 100644 index 00000000..eb59739e --- /dev/null +++ b/product/rddaniel/scp_romfw/config_log.c @@ -0,0 +1,58 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_banner.h> +#include <fwk_macros.h> +#include <fwk_module.h> +#include <fwk_module_idx.h> +#include <mod_log.h> +#include <mod_pl011.h> +#include <scp_system_mmap.h> + +/* + * PL011 module + */ +static const struct fwk_element pl011_element_desc_table[] = { + [0] = { + .name = "uart", + .data = &((struct mod_pl011_device_config) { + .reg_base = SCP_UART_BASE, + .baud_rate_bps = 115200, + .clock_rate_hz = 24 * FWK_MHZ, + .clock_id = FWK_ID_NONE_INIT, + }), + }, + [1] = { 0 }, +}; + +static const struct fwk_element *get_pl011_table(fwk_id_t module_id) +{ + return pl011_element_desc_table; +} + +struct fwk_module_config config_pl011 = { + .get_element_table = get_pl011_table, +}; + +/* + * Log module + */ +static const struct mod_log_config log_data = { + .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0), + .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0), + .log_groups = MOD_LOG_GROUP_ERROR | + MOD_LOG_GROUP_INFO | + MOD_LOG_GROUP_WARNING | + MOD_LOG_GROUP_DEBUG, + .banner = FWK_BANNER_SCP + FWK_BANNER_ROM_FIRMWARE + BUILD_VERSION_DESCRIBE_STRING "\n", +}; + +struct fwk_module_config config_log = { + .data = &log_data, +}; diff --git a/product/rddaniel/scp_romfw/config_rddaniel_rom.c b/product/rddaniel/scp_romfw/config_rddaniel_rom.c new file mode 100644 index 00000000..960021cf --- /dev/null +++ b/product/rddaniel/scp_romfw/config_rddaniel_rom.c @@ -0,0 +1,19 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_module.h> +#include <mod_rddaniel_rom.h> +#include <scp_software_mmap.h> +#include <scp_rddaniel_mmap_scp.h> + +const struct fwk_module_config config_rddaniel_rom = { + .data = &((struct rddaniel_rom_config) { + .ramfw_base = SCP_RAM0_BASE, + .nor_base = SCP_NOR_BASE, + .load_ram_size = SCP_IMAGE_SIZE, + }) +}; diff --git a/product/rddaniel/scp_romfw/firmware.mk b/product/rddaniel/scp_romfw/firmware.mk new file mode 100644 index 00000000..90b1f5f5 --- /dev/null +++ b/product/rddaniel/scp_romfw/firmware.mk @@ -0,0 +1,31 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := no +BS_FIRMWARE_HAS_NOTIFICATION := yes +BS_FIRMWARE_MODULE_HEADERS_ONLY := \ + power_domain \ + timer + +BS_FIRMWARE_MODULES := \ + sid \ + pcid \ + pl011 \ + log \ + rddaniel_rom \ + gtimer \ + clock + +BS_FIRMWARE_SOURCES := \ + config_sid.c \ + config_log.c \ + config_rddaniel_rom.c \ + config_gtimer.c \ + config_clock.c + +include $(BS_DIR)/firmware.mk diff --git a/product/rddaniel/scp_romfw/fmw_memory.ld.S b/product/rddaniel/scp_romfw/fmw_memory.ld.S new file mode 100644 index 00000000..6d3a33d3 --- /dev/null +++ b/product/rddaniel/scp_romfw/fmw_memory.ld.S @@ -0,0 +1,32 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * ROM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_LD_S +#define FMW_MEMORY_LD_S + +#include <scp_system_mmap_scp.h> + +#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * ROM memory + */ +#define FIRMWARE_MEM0_SIZE SCP_ROM_SIZE +#define FIRMWARE_MEM0_BASE SCP_ROM_BASE + +/* + * RAM memory + */ +#define FIRMWARE_MEM1_SIZE SCP_RAM1_SIZE +#define FIRMWARE_MEM1_BASE SCP_RAM1_BASE + +#define FIRMWARE_STACK_SIZE (1 * 1024) + +#endif /* FMW_MEMORY_LD_S */ diff --git a/product/rddaniel/src/config_sid.c b/product/rddaniel/src/config_sid.c new file mode 100644 index 00000000..5f23cbf1 --- /dev/null +++ b/product/rddaniel/src/config_sid.c @@ -0,0 +1,50 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <fwk_element.h> +#include <fwk_module.h> +#include <mod_sid.h> +#include <scp_rddaniel_mmap.h> + +static const struct fwk_element subsystem_table[] = { + { + .name = "RDDANIEL", + .data = &(struct mod_sid_subsystem_config) { + .part_number = 0x78a, + } + }, + { + .name = "Christensen", + .data = &(struct mod_sid_subsystem_config) { + .part_number = 0x785, + } + }, + { 0 }, +}; + +static const struct fwk_element *get_subsystem_table(fwk_id_t id) +{ + return subsystem_table; +} + +const struct fwk_module_config config_sid = { + .get_element_table = get_subsystem_table, + .data = &(struct mod_sid_config) { + .sid_base = SCP_SID_BASE, + .pcid_expected = { + .PID0 = 0xD2, + .PID1 = 0xB0, + .PID2 = 0x0B, + .PID3 = 0x00, + .PID4 = 0x04, + .CID0 = 0x0D, + .CID1 = 0xF0, + .CID2 = 0x05, + .CID3 = 0xB1, + }, + }, +}; |