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authorJun Nie <jun.nie@linaro.org>2018-12-26 16:52:14 +0800
committerJun Nie <jun.nie@linaro.org>2018-12-26 16:52:14 +0800
commit89af39033471cb21ed4db18f491ffb77e30e2a68 (patch)
treeed4545e4a069428ccf868b8288bc82ff36830106
parent644e5420ae01992e59c29f1417c9fd8445fab521 (diff)
arm: imx: add iMX7D PICO MBL board definitionlinaro-pico
This patch adds an OP-TEE port for the i.MX7D PICO for the MBED Linux OS boot flow. BootROM -> ATF/BL2 ATF -> FIP {u-boot, OPTEE} OPTEE -> {populates DTB overlay} u-boot -> FIT {DTB, Kernel, initramfs} Merges DTB and OPTEE DTB-overlay Linux CFG_NS_ENTRY_ADDR = 0x87800000 is the entry point of u-boot CFG_DT_OVERLAY = y adds DTB overlay fragments to the passed DTB make CROSS_COMPILE=arm-linux-gnueabihf- PLATFORM=imx \ PLATFORM_FLAVOR=mx7dpico_mbl ARCH=arm CFG_PAGEABLE_ADDR=0 \ CFG_TEE_CORE_NB_CORE=2 Signed-off-by: Jun Nie <jun.nie@linaro.org>
-rw-r--r--core/arch/arm/plat-imx/conf.mk12
-rw-r--r--core/arch/arm/plat-imx/imx-regs.h2
2 files changed, 14 insertions, 0 deletions
diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk
index d3d17518..9bb44c02 100644
--- a/core/arch/arm/plat-imx/conf.mk
+++ b/core/arch/arm/plat-imx/conf.mk
@@ -28,6 +28,7 @@ mx6s-flavorlist = \
mx7-flavorlist = \
mx7dsabresd \
+ mx7dpico_mbl \
mx7swarp7 \
mx7swarp7_mbl \
mx7dclsom \
@@ -81,6 +82,17 @@ CFG_DDR_SIZE ?= 0x40000000
CFG_UART_BASE ?= UART1_BASE
endif
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
+CFG_DDR_SIZE ?= 0x20000000
+CFG_NS_ENTRY_ADDR ?= 0x87800000
+CFG_DT_ADDR ?= 0x83100000
+CFG_UART_BASE ?= UART5_BASE
+CFG_BOOT_SECONDARY_REQUEST ?= n
+CFG_EXTERNAL_DTB_OVERLAY = y
+CFG_IMX_WDOG_EXT_RESET = y
+$(call force,CFG_TEE_CORE_NB_CORE,2)
+endif
+
ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
CFG_DDR_SIZE ?= 0x20000000
CFG_NS_ENTRY_ADDR ?= 0x80800000
diff --git a/core/arch/arm/plat-imx/imx-regs.h b/core/arch/arm/plat-imx/imx-regs.h
index 242cfc94..85500a5e 100644
--- a/core/arch/arm/plat-imx/imx-regs.h
+++ b/core/arch/arm/plat-imx/imx-regs.h
@@ -148,6 +148,8 @@
#define UART1_BASE 0x30860000
#define UART2_BASE 0x30890000
#define UART3_BASE 0x30880000
+#define UART4_BASE 0x30A60000
+#define UART5_BASE 0x30A70000
#define AIPS1_BASE 0x30000000
#define AIPS1_SIZE 0x400000