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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <asm.S>
#include <arm.h>
#include <arm32_macros.S>
#include <kernel/unwind.h>
FUNC plat_cpu_reset_late , :
UNWIND( .fnstart)
/* NSACR configuration */
read_nsacr r0
orr r0, r0, #NSACR_CP10
orr r0, r0, #NSACR_CP11
orr r0, r0, #NSACR_NS_SMP
write_nsacr r0
/* Enable SMP bit */
read_actlr r0
orr r0, r0, #ACTLR_SMP
#if defined(CFG_CORE_WORKAROUND_SPECTRE_BP) || \
defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC)
orr r0, r0, #ACTLR_CA15_ENABLE_INVALIDATE_BTB
#endif
write_actlr r0
bx lr
UNWIND( .fnend)
END_FUNC plat_cpu_reset_late
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