diff options
Diffstat (limited to 'core/arch/arm/plat-rzn1/main.c')
| -rw-r--r-- | core/arch/arm/plat-rzn1/main.c | 36 |
1 files changed, 33 insertions, 3 deletions
diff --git a/core/arch/arm/plat-rzn1/main.c b/core/arch/arm/plat-rzn1/main.c index 87b1c9ec..cdda545a 100644 --- a/core/arch/arm/plat-rzn1/main.c +++ b/core/arch/arm/plat-rzn1/main.c @@ -51,9 +51,12 @@ #include <rzn1_tz.h> #define SYSCTRL_BASE 0x4000C000 -#define SYSCTRL_REG_RSTEN (SYSCTRL_BASE + 0x120) -#define SYSCTRL_REG_RSTCTRL (SYSCTRL_BASE + 0x198) -#define SYSCTRL_BOOTADDR_REG (SYSCTRL_BASE + 0x204) +#define SYSCTRL_REG_RSTEN (SYSCTRL_BASE + 0x120) +#define SYSCTRL_PWRCTRL_CM3 (SYSCTRL_BASE + 0x174) +#define SYSCTRL_PWRSTAT_CM3 (SYSCTRL_BASE + 0x178) +#define SYSCTRL_REG_RSTCTRL (SYSCTRL_BASE + 0x198) +#define SYSCTRL_BOOTADDR_REG (SYSCTRL_BASE + 0x204) + #define SYSCTRL_REG_RSTEN_MRESET_EN 0 #define SYSCTRL_REG_RSTEN_SWRST_EN 6 @@ -61,6 +64,9 @@ void rzn1_init(void); static void rzn1_tz_init(void); +#ifdef CFG_BOOT_CM3 +static void rzn1_cm3_start(void); +#endif static struct rzn1_ns16550_data console_data; static struct gic_data gic_data; @@ -258,7 +264,31 @@ static void rzn1_tz_init(void) TZ_TARG_UA_SEC); } +#ifdef CFG_BOOT_CM3 +static void rzn1_cm3_start(void) +{ + vaddr_t cm3_pwrctrl_reg = core_mmu_get_va(SYSCTRL_PWRCTRL_CM3, MEM_AREA_IO_SEC); + vaddr_t cm3_pwrstat_reg = core_mmu_get_va(SYSCTRL_PWRSTAT_CM3, MEM_AREA_IO_SEC); + + IMSG("Starting Cortex-M3"); + // Master Idle Request to the interconnect for CM3. + io_clrbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_MIREQ_A); + + // Wait for Master Idle Request Acknowledge for CM3 + while (io_read32(cm3_pwrstat_reg) & SYSCTRL_PWRSTAT_CM3_MIRACK_A) { + // wait + } + + // Clock Enable for CM3_HCLK & Active low Reset to CM3 + io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_CLKEN_A); + io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_RSTN_A); +} +#endif + void rzn1_init(void) { rzn1_tz_init(); +#ifdef CFG_BOOT_CM3 + rzn1_cm3_start(); +#endif } |