diff options
| author | Kumar Gala <kumar.gala@linaro.org> | 2017-04-27 13:25:20 -0500 |
|---|---|---|
| committer | Kumar Gala <kumar.gala@linaro.org> | 2017-04-28 15:26:40 -0500 |
| commit | f6284cfbece5500c1dc770d59553cc9431fe914c (patch) | |
| tree | c14a12589db95de66ff8ae18f1aa8f8355fc399a | |
| parent | 749e02f6ea7b9453f1cb10fe3e17fe79475ba660 (diff) | |
arm: dts: ti_lm3s6965: Add Device Tree Support
Introduce a simple device tree for the TI lm3s6965 SoC and QEMU
Cortex-M3 board port. We get flash and memory base addresses and sizes
from the device tree as well as the ARM NVIC number of priority bits.
Change-Id: I4452b5543de7be55518997e54837ccbfd4f121df
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
| -rw-r--r-- | arch/arm/soc/ti_lm3s6965/Kconfig.defconfig | 10 | ||||
| -rw-r--r-- | boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig | 3 | ||||
| -rw-r--r-- | dts/arm/Makefile | 1 | ||||
| -rw-r--r-- | dts/arm/qemu_cortex_m3.dts | 13 | ||||
| -rw-r--r-- | dts/arm/qemu_cortex_m3.fixup | 1 | ||||
| -rw-r--r-- | dts/arm/ti/lm3s6965.dtsi | 25 |
6 files changed, 41 insertions, 12 deletions
diff --git a/arch/arm/soc/ti_lm3s6965/Kconfig.defconfig b/arch/arm/soc/ti_lm3s6965/Kconfig.defconfig index a7d0e0089..9c3adf300 100644 --- a/arch/arm/soc/ti_lm3s6965/Kconfig.defconfig +++ b/arch/arm/soc/ti_lm3s6965/Kconfig.defconfig @@ -11,16 +11,6 @@ if SOC_TI_LM3S6965 config SOC default ti_lm3s6965 -config SRAM_BASE_ADDRESS - default 0x20000000 - -config FLASH_BASE_ADDRESS - default 0x00000000 - -config NUM_IRQ_PRIO_BITS - int - default 3 - config NUM_IRQS int # must be >= the highest interrupt number used diff --git a/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig b/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig index 3ca4c75b6..a1646590f 100644 --- a/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig +++ b/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig @@ -6,6 +6,5 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_CORTEX_M_SYSTICK=y -CONFIG_FLASH_SIZE=256 -CONFIG_SRAM_SIZE=64 CONFIG_UART_STELLARIS=y +CONFIG_HAS_DTS=y diff --git a/dts/arm/Makefile b/dts/arm/Makefile index 16b2af214..392b1ee74 100644 --- a/dts/arm/Makefile +++ b/dts/arm/Makefile @@ -28,6 +28,7 @@ dtb-$(CONFIG_BOARD_CURIE_BLE) = curie_ble.dts_compiled dtb-$(CONFIG_BOARD_NRF51_BLENANO) = nrf51_blenano.dts_compiled dtb-$(CONFIG_BOARD_NRF51_PCA10028) = nrf51_pca10028.dts_compiled dtb-$(CONFIG_BOARD_QUARK_SE_C1000_BLE) = quark_se_c1000_ble.dts_compiled +dtb-$(CONFIG_BOARD_QEMU_CORTEX_M3) = qemu_cortex_m3.dts_compiled always := $(dtb-y) endif diff --git a/dts/arm/qemu_cortex_m3.dts b/dts/arm/qemu_cortex_m3.dts new file mode 100644 index 000000000..cc7b45cf3 --- /dev/null +++ b/dts/arm/qemu_cortex_m3.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include <ti/lm3s6965.dtsi> + +/ { + model = "QEMU Cortex-M3"; + compatible = "ti,lm3s6965evb-qemu", "ti,lm3s6965"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; diff --git a/dts/arm/qemu_cortex_m3.fixup b/dts/arm/qemu_cortex_m3.fixup new file mode 100644 index 000000000..af1312e9d --- /dev/null +++ b/dts/arm/qemu_cortex_m3.fixup @@ -0,0 +1 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS diff --git a/dts/arm/ti/lm3s6965.dtsi b/dts/arm/ti/lm3s6965.dtsi new file mode 100644 index 000000000..308694cb8 --- /dev/null +++ b/dts/arm/ti/lm3s6965.dtsi @@ -0,0 +1,25 @@ +#include <arm/armv7-m.dtsi> + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-m3"; + }; + }; + + sram0: memory { + compatible = "sram"; + reg = <0x20000000 (64*1024)>; + }; + + flash0: flash { + reg = <0x00000000 (256*1024)>; + }; + + soc { + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; |