diff options
| author | Kumar Gala <kumar.gala@linaro.org> | 2017-04-28 15:37:23 -0500 |
|---|---|---|
| committer | Kumar Gala <kumar.gala@linaro.org> | 2017-04-28 15:39:05 -0500 |
| commit | 3d3adc8578f19a6f6449b3101e25639c5794037f (patch) | |
| tree | e67c86482124bf5e337e828f6b6564f0c67f3677 /ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h | |
| parent | cc93aceb83642a83105a634cf4847d5d563bd2b2 (diff) | |
| parent | ac0bb050ddef753741ff9e05932aad1b6c43ed22 (diff) | |
Merge arm branch into master
Main changes:
- Converted Nordic SoC & Boards to device tree
- Converted TI LM3S6965 SoC & QEMU Cortex M3 board to device tree
- Add support for TI CC3220 SF SoC & CC3220SF-LAUNCHXL board
- Add support for ST DISCO L475 IOT1 board
- Add support for NXP FRDM-KL25Z board
- Converted all dts to use 'current-speed' instead of 'baud-rate'
- Various code cleanups
----------------------------------------------------------------
Erwan Gouriou (12):
ext: stm32cube: update stm32f1xx cube version
dts: Align uart "baud-rate" property to device tree spec "current-speed"
drivers: clock control: Provide LL based clock control for stm32f4 series
drivers: dma_stm32f4x: make driver compatible with LL Clock Driver
boards: stm32f4: Provide config for LL Clock control
soc: stm32f4: Enable LL based clock control
stm32f4: Clean references to stm32f4 specific clock control
driver: uart: clock control code refactoring
driver: clock control stm32: align f4 factor names on l4
soc: stm32l4xx: add support for STM32L475XG
board: Add support for board disco_l475_iot1
boards: disco_l475_iot: Configuration for HTS221 sample
Florian Vaussard (2):
arm: stm32f4: Reorder Kconfig options
pinmux: stm32f4: Clean-up pinmux header
Gil Pitney (7):
cc3200: Make use of mem.h file in soc dtsi file.
cc3220sf: Add support for the TI CC3220SF SoC
boards: Add support for the CC3220SF_LAUNCHXL board
MAINTAINERS: Update maintainer for TI CC3220SF LaunchXL board
cc3220sf: Update "baud-rate" dts property to "current-speed"
cc3200: Set warning to deprecate board in Zephyr v1.8
cc3220sf: Minor board documentation updates
Gustavo Denardin (1):
arm: Support for new ARM board FRDM-KL25Z
Jon Medhurst (2):
i2c: bitbang: Add library for software driven I2C
i2c: i2c_gpio: Driver for software driven I2C using GPIO lines
Kumar Gala (13):
serial: mcux: Shim driver for LPSCI UART on KL25Z
arm: nxp: kl2x: Move to using UART_MCUX_LPSCI for UART0
arm: ti: dts: fixup building CC3200 dts
arm: soc: ti_lm3s6965: remove dead code
arm: linker: remove unused linker sections
arm: dts: nrf: Add Device Tree Support for nRF52832 SoC based boards
arm: dts: nrf: Fixup nRF52840-QIAA SoC support for device tree
arm: dts: nrf: Add Device Tree Support for nRF52840 SoC & boards
arm: dts: nrf: Add Device Tree Support for nRF51822 SoC & boards
arm: dts: nrf: Remove !HAS_DTS Kconfig bits
serial: uart_stellaris: remove export of uart_stellaris_isr
arm: dts: ti_lm3s6965: Add Device Tree Support
arm: dts: ti_lm3s6965: Add device tree support for Stellaris UART
.gitreview | 1 +
MAINTAINERS | 2 +-
.../nrf51/Kconfig.defconfig.nrf51822_QFAA | 6 -
.../nrf51/Kconfig.defconfig.nrf51822_QFAB | 6 -
.../nrf51/Kconfig.defconfig.nrf51822_QFAC | 6 -
.../soc/nordic_nrf5/nrf51/Kconfig.defconfig.series | 10 -
.../nrf52/Kconfig.defconfig.nrf52832_QFAA | 8 -
.../nrf52/Kconfig.defconfig.nrf52840_QIAA | 6 -
.../soc/nordic_nrf5/nrf52/Kconfig.defconfig.series | 12 -
arch/arm/soc/nxp_kinetis/Kconfig | 6 +
.../soc/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 | 2 +-
arch/arm/soc/nxp_kinetis/kl2x/Kconfig.soc | 1 +
arch/arm/soc/nxp_kinetis/kl2x/soc.c | 6 +-
.../soc/st_stm32/stm32f4/Kconfig.defconfig.series | 2 +-
arch/arm/soc/st_stm32/stm32f4/Kconfig.soc | 6 +-
arch/arm/soc/st_stm32/stm32f4/flash_registers.h | 107 -
arch/arm/soc/st_stm32/stm32f4/rcc_registers.h | 159 -
arch/arm/soc/st_stm32/stm32f4/soc.c | 6 +
arch/arm/soc/st_stm32/stm32f4/soc.h | 7 +
arch/arm/soc/st_stm32/stm32f4/soc_gpio.c | 6 +-
arch/arm/soc/st_stm32/stm32f4/soc_registers.h | 1 -
.../st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg | 18 +
arch/arm/soc/st_stm32/stm32l4/Kconfig.soc | 4 +
arch/arm/soc/ti_lm3s6965/Kconfig.defconfig | 30 -
arch/arm/soc/ti_lm3s6965/Makefile | 1 -
arch/arm/soc/ti_lm3s6965/scp.c | 44 -
arch/arm/soc/ti_lm3s6965/scp.h | 164 -
arch/arm/soc/ti_lm3s6965/soc.h | 12 -
.../cc32xx/Kconfig.defconfig.cc3220sf | 43 +
arch/arm/soc/ti_simplelink/cc32xx/Kconfig.soc | 15 +
arch/arm/soc/ti_simplelink/cc32xx/README | 10 +-
arch/arm/soc/ti_simplelink/cc32xx/soc.c | 6 +-
boards/arm/96b_carbon/96b_carbon_defconfig | 23 +-
boards/arm/96b_nitrogen/96b_nitrogen_defconfig | 3 +
.../arm/arduino_101_ble/arduino_101_ble_defconfig | 3 +
boards/arm/bbc_microbit/bbc_microbit_defconfig | 3 +
boards/arm/cc3200_launchxl/Kconfig.defconfig | 3 +
boards/arm/cc3220sf_launchxl/Kconfig.board | 6 +
boards/arm/cc3220sf_launchxl/Kconfig.defconfig | 9 +
boards/arm/cc3220sf_launchxl/Makefile | 4 +
boards/arm/cc3220sf_launchxl/board.h | 25 +
.../cc3220sf_launchxl/cc3220sf_launchxl_defconfig | 28 +
boards/arm/cc3220sf_launchxl/dbghdr.c | 24 +
.../cc3220sf_launchxl/doc/cc3220sf_launchxl.rst | 222 +
boards/arm/cc3220sf_launchxl/pinmux.c | 121 +
.../arm/cc3220sf_launchxl/support/CC3220SF.ccxml | 14 +
.../cc3220sf_launchxl/support/cc3220_xds110.cfg | 45 +
.../arm/cc3220sf_launchxl/support/gdbinit_xds110 | 16 +
boards/arm/curie_ble/curie_ble_defconfig | 3 +
boards/arm/disco_l475_iot1/Kconfig.board | 10 +
boards/arm/disco_l475_iot1/Kconfig.defconfig | 90 +
boards/arm/disco_l475_iot1/Makefile | 2 +
boards/arm/disco_l475_iot1/board.h | 41 +
.../arm/disco_l475_iot1/disco_l475_iot1_defconfig | 58 +
boards/arm/disco_l475_iot1/doc/disco_l475_iot1.rst | 245 +
.../disco_l475_iot1/doc/img/disco_l475_iot1.jpg | Bin 0 -> 1471155 bytes
boards/arm/frdm_kl25z/Kconfig.board | 11 +
boards/arm/frdm_kl25z/Kconfig.defconfig | 108 +
boards/arm/frdm_kl25z/Makefile | 10 +
boards/arm/frdm_kl25z/board.h | 44 +
boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg | Bin 0 -> 15127 bytes
boards/arm/frdm_kl25z/doc/frdm_kl25z.rst | 173 +
boards/arm/frdm_kl25z/frdm_kl25z_defconfig | 12 +
boards/arm/frdm_kl25z/pinmux.c | 70 +
boards/arm/nrf51_blenano/nrf51_blenano_defconfig | 3 +
boards/arm/nrf51_pca10028/nrf51_pca10028_defconfig | 3 +
.../nrf52840_pca10056/nrf52840_pca10056_defconfig | 3 +
boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig | 3 +
boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig | 3 +
boards/arm/nucleo_f401re/nucleo_f401re_defconfig | 24 +-
boards/arm/nucleo_f411re/nucleo_f411re_defconfig | 25 +-
boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig | 3 +-
.../quark_se_c1000_ble_defconfig | 3 +
drivers/clock_control/Kconfig | 2 -
drivers/clock_control/Kconfig.stm32 | 46 +
drivers/clock_control/Kconfig.stm32f4x | 141 -
drivers/clock_control/Makefile | 2 +-
drivers/clock_control/stm32_ll_clock.c | 9 +
drivers/clock_control/stm32_ll_clock.h | 1 +
drivers/clock_control/stm32f3x_ll_clock.c | 8 +
drivers/clock_control/stm32f4x_clock.c | 350 --
drivers/clock_control/stm32f4x_ll_clock.c | 52 +
drivers/clock_control/stm32l4x_ll_clock.c | 8 +
drivers/dma/dma_stm32f4x.c | 11 +-
drivers/gpio/gpio_stm32.c | 35 +-
drivers/gpio/gpio_stm32.h | 6 +-
drivers/i2c/Kconfig | 8 +
drivers/i2c/Kconfig.gpio | 158 +
drivers/i2c/Makefile | 2 +
drivers/i2c/i2c_bitbang.c | 279 ++
drivers/i2c/i2c_bitbang.h | 57 +
drivers/i2c/i2c_gpio.c | 149 +
drivers/pinmux/Makefile | 1 +
.../pinmux/stm32/pinmux_board_disco_l475_iot1.c | 64 +
drivers/pinmux/stm32/pinmux_stm32.c | 21 +-
drivers/pinmux/stm32/pinmux_stm32f4.h | 14 +-
drivers/pwm/pwm_stm32.c | 43 +-
drivers/pwm/pwm_stm32.h | 4 -
drivers/serial/Kconfig | 2 +
drivers/serial/Kconfig.mcux_lpsci | 32 +
drivers/serial/Kconfig.stellaris | 48 -
drivers/serial/Makefile | 1 +
drivers/serial/uart_cc32xx.c | 2 +-
drivers/serial/uart_mcux_lpsci.c | 308 ++
drivers/serial/uart_stellaris.c | 34 +-
drivers/serial/uart_stellaris.h | 16 -
drivers/serial/uart_stm32.c | 21 +-
drivers/serial/uart_stm32.h | 4 -
dts/arm/96b_carbon.dts | 4 +-
dts/arm/96b_carbon.fixup | 5 +-
dts/arm/96b_nitrogen.dts | 26 +
dts/arm/96b_nitrogen.fixup | 3 +
dts/arm/Makefile | 14 +
dts/arm/arduino_101_ble.dts | 25 +
dts/arm/arduino_101_ble.fixup | 3 +
dts/arm/bbc_microbit.dts | 24 +
dts/arm/bbc_microbit.fixup | 3 +
dts/arm/cc3200_launchxl.dts | 5 +-
dts/arm/cc3220sf_launchxl.dts | 23 +
dts/arm/cc3220sf_launchxl.fixup | 1 +
dts/arm/curie_ble.dts | 25 +
dts/arm/curie_ble.fixup | 3 +
dts/arm/disco_l475_iot1.dts | 24 +
dts/arm/disco_l475_iot1.fixup | 32 +
dts/arm/frdm_k64f.dts | 4 +-
dts/arm/frdm_k64f.fixup | 12 +-
dts/arm/frdm_kl25z.dts | 23 +
dts/arm/frdm_kl25z.fixup | 1 +
dts/arm/frdm_kw41z.dts | 1 +
dts/arm/frdm_kw41z.fixup | 2 +-
dts/arm/hexiwear_k64.dts | 4 +-
dts/arm/hexiwear_k64.fixup | 12 +-
dts/arm/hexiwear_kw40z.dts | 2 +-
dts/arm/hexiwear_kw40z.fixup | 2 +-
dts/arm/nordic/nrf51822.dtsi | 31 +
dts/arm/nordic/nrf52840.dtsi | 38 +
dts/arm/nrf51_blenano.dts | 25 +
dts/arm/nrf51_blenano.fixup | 3 +
dts/arm/nrf51_pca10028.dts | 25 +
dts/arm/nrf51_pca10028.fixup | 3 +
dts/arm/nrf52840_pca10056.dts | 26 +
dts/arm/nrf52840_pca10056.fixup | 3 +
dts/arm/nrf52_blenano2.dts | 26 +
dts/arm/nrf52_blenano2.fixup | 3 +
dts/arm/nrf52_pca10040.dts | 26 +
dts/arm/nrf52_pca10040.fixup | 3 +
dts/arm/nucleo_f103rb.dts | 2 +-
dts/arm/nucleo_f103rb.fixup | 2 +-
dts/arm/nucleo_f334r8.dts | 2 +-
dts/arm/nucleo_f334r8.fixup | 2 +-
dts/arm/nucleo_f401re.dts | 4 +-
dts/arm/nucleo_f401re.fixup | 5 +-
dts/arm/nucleo_f411re.dts | 4 +-
dts/arm/nucleo_f411re.fixup | 5 +-
dts/arm/nucleo_l476rg.dts | 2 +-
dts/arm/nucleo_l476rg.fixup | 10 +-
dts/arm/nxp/nxp_kl25z.dtsi | 32 +
dts/arm/nxp/nxp_kw41z.dtsi | 1 -
dts/arm/olimexino_stm32.dts | 2 +-
dts/arm/olimexino_stm32.fixup | 6 +-
dts/arm/qemu_cortex_m3.dts | 34 +
dts/arm/qemu_cortex_m3.fixup | 1 +
dts/arm/quark_se_c1000_ble.dts | 25 +
dts/arm/quark_se_c1000_ble.fixup | 3 +
dts/arm/st/mem.h | 3 +
dts/arm/st/stm32l475.dtsi | 59 +
dts/arm/st/stm32l476.dtsi | 54 +-
dts/arm/stm3210c_eval.dts | 2 +-
dts/arm/stm3210c_eval.fixup | 2 +-
dts/arm/stm32373c_eval.dts | 2 +-
dts/arm/stm32373c_eval.fixup | 2 +-
dts/arm/stm32_mini_a15.dts | 2 +-
dts/arm/stm32_mini_a15.fixup | 2 +-
dts/arm/ti/{cc32xx_launchxl.dtsi => cc32xx.dtsi} | 15 +-
dts/arm/ti/lm3s6965.dtsi | 45 +
dts/arm/ti/mem.h | 19 +
dts/arm/v2m_beetle.dts | 4 +-
dts/arm/v2m_beetle.fixup | 4 +-
dts/arm/yaml/nxp,kinetis-lpsci.yaml | 31 +
dts/arm/yaml/ti,stellaris-uart.yaml | 30 +
dts/common/yaml/uart.yaml | 2 +-
ext/hal/nxp/mcux/drivers/Makefile | 1 +
ext/hal/st/stm32cube/Kbuild | 1 +
ext/hal/st/stm32cube/stm32f1xx/README | 6 +-
.../drivers/include/Legacy/stm32_hal_legacy.h | 254 +-
.../drivers/include/stm32_assert_template.h | 75 +
.../stm32f1xx/drivers/include/stm32f1xx_hal.h | 67 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_adc.h | 148 +-
.../drivers/include/stm32f1xx_hal_adc_ex.h | 127 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_can.h | 445 +-
.../drivers/include/stm32f1xx_hal_can_ex.h | 13 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_cec.h | 325 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_conf.h | 144 +-
.../drivers/include/stm32f1xx_hal_cortex.h | 266 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_crc.h | 14 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_dac.h | 42 +-
.../drivers/include/stm32f1xx_hal_dac_ex.h | 20 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_def.h | 54 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_dma.h | 259 +-
.../drivers/include/stm32f1xx_hal_dma_ex.h | 51 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_eth.h | 946 ++--
.../drivers/include/stm32f1xx_hal_flash.h | 40 +-
.../drivers/include/stm32f1xx_hal_flash_ex.h | 304 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_gpio.h | 178 +-
.../drivers/include/stm32f1xx_hal_gpio_ex.h | 85 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_hcd.h | 22 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_i2c.h | 600 +--
.../stm32f1xx/drivers/include/stm32f1xx_hal_i2s.h | 254 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_irda.h | 366 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_iwdg.h | 235 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_mmc.h | 718 +++
.../stm32f1xx/drivers/include/stm32f1xx_hal_nand.h | 249 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_nor.h | 18 +-
.../drivers/include/stm32f1xx_hal_pccard.h | 29 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_pcd.h | 120 +-
.../drivers/include/stm32f1xx_hal_pcd_ex.h | 4 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_pwr.h | 20 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_rcc.h | 494 +-
.../drivers/include/stm32f1xx_hal_rcc_ex.h | 152 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_rtc.h | 52 +-
.../drivers/include/stm32f1xx_hal_rtc_ex.h | 104 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_sd.h | 646 +--
.../drivers/include/stm32f1xx_hal_smartcard.h | 458 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_spi.h | 483 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_sram.h | 14 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_tim.h | 362 +-
.../drivers/include/stm32f1xx_hal_tim_ex.h | 47 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_uart.h | 504 ++-
.../drivers/include/stm32f1xx_hal_usart.h | 400 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_wwdg.h | 177 +-
.../stm32f1xx/drivers/include/stm32f1xx_ll_adc.h | 3950 ++++++++++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_bus.h | 1033 +++++
.../drivers/include/stm32f1xx_ll_cortex.h | 658 +++
.../stm32f1xx/drivers/include/stm32f1xx_ll_crc.h | 212 +
.../stm32f1xx/drivers/include/stm32f1xx_ll_dac.h | 1349 ++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_dma.h | 1978 ++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_exti.h | 906 ++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_fsmc.h | 812 ++--
.../stm32f1xx/drivers/include/stm32f1xx_ll_gpio.h | 2381 ++++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_i2c.h | 1802 ++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h | 329 ++
.../stm32f1xx/drivers/include/stm32f1xx_ll_pwr.h | 458 ++
.../stm32f1xx/drivers/include/stm32f1xx_ll_rcc.h | 2309 ++++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_rtc.h | 1021 +++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_sdmmc.h | 467 +-
.../stm32f1xx/drivers/include/stm32f1xx_ll_spi.h | 1922 ++++++++
.../drivers/include/stm32f1xx_ll_system.h | 592 +++
.../stm32f1xx/drivers/include/stm32f1xx_ll_tim.h | 3837 ++++++++++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_usart.h | 2589 +++++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_usb.h | 4 +-
.../stm32f1xx/drivers/include/stm32f1xx_ll_utils.h | 284 ++
.../stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h | 342 ++
.../stm32f1xx/drivers/src/stm32f1xx_hal.c | 106 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_adc.c | 52 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_adc_ex.c | 104 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_can.c | 988 ++--
.../stm32f1xx/drivers/src/stm32f1xx_hal_cec.c | 722 +--
.../stm32f1xx/drivers/src/stm32f1xx_hal_cortex.c | 199 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_crc.c | 15 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_dac.c | 12 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_dac_ex.c | 16 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_dma.c | 734 +--
.../stm32f1xx/drivers/src/stm32f1xx_hal_eth.c | 347 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_flash.c | 170 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_flash_ex.c | 77 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_gpio.c | 130 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_gpio_ex.c | 4 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c | 125 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c | 4184 +++++++++++------
.../stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c | 986 ++--
.../stm32f1xx/drivers/src/stm32f1xx_hal_irda.c | 1708 ++++---
.../stm32f1xx/drivers/src/stm32f1xx_hal_iwdg.c | 316 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c | 2598 +++++++++++
.../drivers/src/stm32f1xx_hal_msp_template.c | 4 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_nand.c | 1075 ++++-
.../stm32f1xx/drivers/src/stm32f1xx_hal_nor.c | 38 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_pccard.c | 54 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c | 258 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_pcd_ex.c | 30 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_pwr.c | 33 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_rcc.c | 109 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_rcc_ex.c | 139 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_rtc.c | 210 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_rtc_ex.c | 31 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_sd.c | 4762 +++++++++-----------
.../drivers/src/stm32f1xx_hal_smartcard.c | 1853 +++++---
.../stm32f1xx/drivers/src/stm32f1xx_hal_spi.c | 3632 +++++++++------
.../stm32f1xx/drivers/src/stm32f1xx_hal_spi_ex.c | 54 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_sram.c | 16 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_tim.c | 236 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_tim_ex.c | 46 +-
.../stm32f1xx_hal_timebase_rtc_alarm_template.c | 307 ++
.../src/stm32f1xx_hal_timebase_tim_template.c | 184 +
.../stm32f1xx/drivers/src/stm32f1xx_hal_uart.c | 1703 ++++---
.../stm32f1xx/drivers/src/stm32f1xx_hal_usart.c | 1265 ++++--
.../stm32f1xx/drivers/src/stm32f1xx_hal_wwdg.c | 390 +-
.../stm32f1xx/drivers/src/stm32f1xx_ll_adc.c | 903 ++++
.../stm32f1xx/drivers/src/stm32f1xx_ll_crc.c | 126 +
.../stm32f1xx/drivers/src/stm32f1xx_ll_dac.c | 274 ++
.../stm32f1xx/drivers/src/stm32f1xx_ll_dma.c | 331 ++
.../stm32f1xx/drivers/src/stm32f1xx_ll_exti.c | 232 +
.../stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c | 362 +-
.../stm32f1xx/drivers/src/stm32f1xx_ll_gpio.c | 265 ++
.../stm32f1xx/drivers/src/stm32f1xx_ll_i2c.c | 239 +
.../stm32f1xx/drivers/src/stm32f1xx_ll_pwr.c | 103 +
.../stm32f1xx/drivers/src/stm32f1xx_ll_rcc.c | 507 +++
.../stm32f1xx/drivers/src/stm32f1xx_ll_rtc.c | 558 +++
.../stm32f1xx/drivers/src/stm32f1xx_ll_sdmmc.c | 1184 ++++-
.../stm32f1xx/drivers/src/stm32f1xx_ll_spi.c | 562 +++
.../stm32f1xx/drivers/src/stm32f1xx_ll_tim.c | 1216 +++++
.../stm32f1xx/drivers/src/stm32f1xx_ll_usart.c | 451 ++
.../stm32f1xx/drivers/src/stm32f1xx_ll_usb.c | 167 +-
.../stm32f1xx/drivers/src/stm32f1xx_ll_utils.c | 623 +++
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xb.h | 962 ++--
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xe.h | 1032 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101x6.h | 839 +---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h | 847 +---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xe.h | 966 ++--
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xg.h | 1045 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102x6.h | 1187 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102xb.h | 1191 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103x6.h | 1215 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xb.h | 1235 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xe.h | 1348 ++----
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xg.h | 1370 ++----
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f105xc.h | 989 ++--
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f107xc.h | 1135 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f1xx.h | 12 +-
.../st/stm32cube/stm32f1xx/soc/system_stm32f1xx.c | 112 +-
.../st/stm32cube/stm32f1xx/soc/system_stm32f1xx.h | 10 +-
include/arch/arm/cortex_m/scripts/linker.ld | 35 +-
.../drivers/clock_control/stm32_clock_control.h | 2 -
.../drivers/clock_control/stm32f4_clock_control.h | 134 -
include/section_tags.h | 1 -
include/sections.h | 2 -
scripts/sanity_chk/arches/arm.ini | 3 +-
tests/kernel/xip/testcase.ini | 2 +-
337 files changed, 69436 insertions(+), 29054 deletions(-)
delete mode 100644 arch/arm/soc/st_stm32/stm32f4/rcc_registers.h
create mode 100644 arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg
delete mode 100644 arch/arm/soc/ti_lm3s6965/scp.c
delete mode 100644 arch/arm/soc/ti_lm3s6965/scp.h
create mode 100644 arch/arm/soc/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf
create mode 100644 boards/arm/cc3220sf_launchxl/Kconfig.board
create mode 100644 boards/arm/cc3220sf_launchxl/Kconfig.defconfig
create mode 100644 boards/arm/cc3220sf_launchxl/Makefile
create mode 100644 boards/arm/cc3220sf_launchxl/board.h
create mode 100644 boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig
create mode 100644 boards/arm/cc3220sf_launchxl/dbghdr.c
create mode 100644 boards/arm/cc3220sf_launchxl/doc/cc3220sf_launchxl.rst
create mode 100644 boards/arm/cc3220sf_launchxl/pinmux.c
create mode 100644 boards/arm/cc3220sf_launchxl/support/CC3220SF.ccxml
create mode 100644 boards/arm/cc3220sf_launchxl/support/cc3220_xds110.cfg
create mode 100644 boards/arm/cc3220sf_launchxl/support/gdbinit_xds110
create mode 100644 boards/arm/disco_l475_iot1/Kconfig.board
create mode 100644 boards/arm/disco_l475_iot1/Kconfig.defconfig
create mode 100644 boards/arm/disco_l475_iot1/Makefile
create mode 100644 boards/arm/disco_l475_iot1/board.h
create mode 100644 boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig
create mode 100644 boards/arm/disco_l475_iot1/doc/disco_l475_iot1.rst
create mode 100644 boards/arm/disco_l475_iot1/doc/img/disco_l475_iot1.jpg
create mode 100644 boards/arm/frdm_kl25z/Kconfig.board
create mode 100644 boards/arm/frdm_kl25z/Kconfig.defconfig
create mode 100644 boards/arm/frdm_kl25z/Makefile
create mode 100644 boards/arm/frdm_kl25z/board.h
create mode 100644 boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg
create mode 100644 boards/arm/frdm_kl25z/doc/frdm_kl25z.rst
create mode 100644 boards/arm/frdm_kl25z/frdm_kl25z_defconfig
create mode 100644 boards/arm/frdm_kl25z/pinmux.c
delete mode 100644 drivers/clock_control/Kconfig.stm32f4x
delete mode 100644 drivers/clock_control/stm32f4x_clock.c
create mode 100644 drivers/clock_control/stm32f4x_ll_clock.c
create mode 100644 drivers/i2c/Kconfig.gpio
create mode 100644 drivers/i2c/i2c_bitbang.c
create mode 100644 drivers/i2c/i2c_bitbang.h
create mode 100644 drivers/i2c/i2c_gpio.c
create mode 100644 drivers/pinmux/stm32/pinmux_board_disco_l475_iot1.c
create mode 100644 drivers/serial/Kconfig.mcux_lpsci
create mode 100644 drivers/serial/uart_mcux_lpsci.c
delete mode 100644 drivers/serial/uart_stellaris.h
create mode 100644 dts/arm/96b_nitrogen.dts
create mode 100644 dts/arm/96b_nitrogen.fixup
create mode 100644 dts/arm/arduino_101_ble.dts
create mode 100644 dts/arm/arduino_101_ble.fixup
create mode 100644 dts/arm/bbc_microbit.dts
create mode 100644 dts/arm/bbc_microbit.fixup
create mode 100644 dts/arm/cc3220sf_launchxl.dts
create mode 100644 dts/arm/cc3220sf_launchxl.fixup
create mode 100644 dts/arm/curie_ble.dts
create mode 100644 dts/arm/curie_ble.fixup
create mode 100644 dts/arm/disco_l475_iot1.dts
create mode 100644 dts/arm/disco_l475_iot1.fixup
create mode 100644 dts/arm/frdm_kl25z.dts
create mode 100644 dts/arm/frdm_kl25z.fixup
create mode 100644 dts/arm/nordic/nrf51822.dtsi
create mode 100644 dts/arm/nordic/nrf52840.dtsi
create mode 100644 dts/arm/nrf51_blenano.dts
create mode 100644 dts/arm/nrf51_blenano.fixup
create mode 100644 dts/arm/nrf51_pca10028.dts
create mode 100644 dts/arm/nrf51_pca10028.fixup
create mode 100644 dts/arm/nrf52840_pca10056.dts
create mode 100644 dts/arm/nrf52840_pca10056.fixup
create mode 100644 dts/arm/nrf52_blenano2.dts
create mode 100644 dts/arm/nrf52_blenano2.fixup
create mode 100644 dts/arm/nrf52_pca10040.dts
create mode 100644 dts/arm/nrf52_pca10040.fixup
create mode 100644 dts/arm/nxp/nxp_kl25z.dtsi
create mode 100644 dts/arm/qemu_cortex_m3.dts
create mode 100644 dts/arm/qemu_cortex_m3.fixup
create mode 100644 dts/arm/quark_se_c1000_ble.dts
create mode 100644 dts/arm/quark_se_c1000_ble.fixup
create mode 100644 dts/arm/st/stm32l475.dtsi
rename dts/arm/ti/{cc32xx_launchxl.dtsi => cc32xx.dtsi} (78%)
create mode 100644 dts/arm/ti/lm3s6965.dtsi
create mode 100644 dts/arm/ti/mem.h
create mode 100644 dts/arm/yaml/nxp,kinetis-lpsci.yaml
create mode 100644 dts/arm/yaml/ti,stellaris-uart.yaml
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32_assert_template.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_mmc.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_adc.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_bus.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_cortex.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_crc.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dac.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dma.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_gpio.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_i2c.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_pwr.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_rcc.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_rtc.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_spi.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_system.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_tim.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usart.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_utils.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_rtc_alarm_template.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_tim_template.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_adc.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_crc.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_dac.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_dma.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_exti.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_gpio.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_i2c.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_pwr.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_rcc.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_rtc.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_spi.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_tim.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usart.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_utils.c
delete mode 100644 include/drivers/clock_control/stm32f4_clock_control.h
Change-Id: I0a465f75ff94c33373c03951b4d7468476bc3b41
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Diffstat (limited to 'ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h')
| -rw-r--r-- | ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h | 906 |
1 files changed, 906 insertions, 0 deletions
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h new file mode 100644 index 000000000..38e337815 --- /dev/null +++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h @@ -0,0 +1,906 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_exti.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_EXTI_H +#define __STM32F1xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#if defined(EXTI_IMR_IM19) +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#endif +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#if defined(EXTI_IMR_IM23) +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#endif +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |