diff options
| author | Kumar Gala <kumar.gala@linaro.org> | 2017-04-28 15:37:23 -0500 |
|---|---|---|
| committer | Kumar Gala <kumar.gala@linaro.org> | 2017-04-28 15:39:05 -0500 |
| commit | 3d3adc8578f19a6f6449b3101e25639c5794037f (patch) | |
| tree | e67c86482124bf5e337e828f6b6564f0c67f3677 /ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h | |
| parent | cc93aceb83642a83105a634cf4847d5d563bd2b2 (diff) | |
| parent | ac0bb050ddef753741ff9e05932aad1b6c43ed22 (diff) | |
Merge arm branch into master
Main changes:
- Converted Nordic SoC & Boards to device tree
- Converted TI LM3S6965 SoC & QEMU Cortex M3 board to device tree
- Add support for TI CC3220 SF SoC & CC3220SF-LAUNCHXL board
- Add support for ST DISCO L475 IOT1 board
- Add support for NXP FRDM-KL25Z board
- Converted all dts to use 'current-speed' instead of 'baud-rate'
- Various code cleanups
----------------------------------------------------------------
Erwan Gouriou (12):
ext: stm32cube: update stm32f1xx cube version
dts: Align uart "baud-rate" property to device tree spec "current-speed"
drivers: clock control: Provide LL based clock control for stm32f4 series
drivers: dma_stm32f4x: make driver compatible with LL Clock Driver
boards: stm32f4: Provide config for LL Clock control
soc: stm32f4: Enable LL based clock control
stm32f4: Clean references to stm32f4 specific clock control
driver: uart: clock control code refactoring
driver: clock control stm32: align f4 factor names on l4
soc: stm32l4xx: add support for STM32L475XG
board: Add support for board disco_l475_iot1
boards: disco_l475_iot: Configuration for HTS221 sample
Florian Vaussard (2):
arm: stm32f4: Reorder Kconfig options
pinmux: stm32f4: Clean-up pinmux header
Gil Pitney (7):
cc3200: Make use of mem.h file in soc dtsi file.
cc3220sf: Add support for the TI CC3220SF SoC
boards: Add support for the CC3220SF_LAUNCHXL board
MAINTAINERS: Update maintainer for TI CC3220SF LaunchXL board
cc3220sf: Update "baud-rate" dts property to "current-speed"
cc3200: Set warning to deprecate board in Zephyr v1.8
cc3220sf: Minor board documentation updates
Gustavo Denardin (1):
arm: Support for new ARM board FRDM-KL25Z
Jon Medhurst (2):
i2c: bitbang: Add library for software driven I2C
i2c: i2c_gpio: Driver for software driven I2C using GPIO lines
Kumar Gala (13):
serial: mcux: Shim driver for LPSCI UART on KL25Z
arm: nxp: kl2x: Move to using UART_MCUX_LPSCI for UART0
arm: ti: dts: fixup building CC3200 dts
arm: soc: ti_lm3s6965: remove dead code
arm: linker: remove unused linker sections
arm: dts: nrf: Add Device Tree Support for nRF52832 SoC based boards
arm: dts: nrf: Fixup nRF52840-QIAA SoC support for device tree
arm: dts: nrf: Add Device Tree Support for nRF52840 SoC & boards
arm: dts: nrf: Add Device Tree Support for nRF51822 SoC & boards
arm: dts: nrf: Remove !HAS_DTS Kconfig bits
serial: uart_stellaris: remove export of uart_stellaris_isr
arm: dts: ti_lm3s6965: Add Device Tree Support
arm: dts: ti_lm3s6965: Add device tree support for Stellaris UART
.gitreview | 1 +
MAINTAINERS | 2 +-
.../nrf51/Kconfig.defconfig.nrf51822_QFAA | 6 -
.../nrf51/Kconfig.defconfig.nrf51822_QFAB | 6 -
.../nrf51/Kconfig.defconfig.nrf51822_QFAC | 6 -
.../soc/nordic_nrf5/nrf51/Kconfig.defconfig.series | 10 -
.../nrf52/Kconfig.defconfig.nrf52832_QFAA | 8 -
.../nrf52/Kconfig.defconfig.nrf52840_QIAA | 6 -
.../soc/nordic_nrf5/nrf52/Kconfig.defconfig.series | 12 -
arch/arm/soc/nxp_kinetis/Kconfig | 6 +
.../soc/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 | 2 +-
arch/arm/soc/nxp_kinetis/kl2x/Kconfig.soc | 1 +
arch/arm/soc/nxp_kinetis/kl2x/soc.c | 6 +-
.../soc/st_stm32/stm32f4/Kconfig.defconfig.series | 2 +-
arch/arm/soc/st_stm32/stm32f4/Kconfig.soc | 6 +-
arch/arm/soc/st_stm32/stm32f4/flash_registers.h | 107 -
arch/arm/soc/st_stm32/stm32f4/rcc_registers.h | 159 -
arch/arm/soc/st_stm32/stm32f4/soc.c | 6 +
arch/arm/soc/st_stm32/stm32f4/soc.h | 7 +
arch/arm/soc/st_stm32/stm32f4/soc_gpio.c | 6 +-
arch/arm/soc/st_stm32/stm32f4/soc_registers.h | 1 -
.../st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg | 18 +
arch/arm/soc/st_stm32/stm32l4/Kconfig.soc | 4 +
arch/arm/soc/ti_lm3s6965/Kconfig.defconfig | 30 -
arch/arm/soc/ti_lm3s6965/Makefile | 1 -
arch/arm/soc/ti_lm3s6965/scp.c | 44 -
arch/arm/soc/ti_lm3s6965/scp.h | 164 -
arch/arm/soc/ti_lm3s6965/soc.h | 12 -
.../cc32xx/Kconfig.defconfig.cc3220sf | 43 +
arch/arm/soc/ti_simplelink/cc32xx/Kconfig.soc | 15 +
arch/arm/soc/ti_simplelink/cc32xx/README | 10 +-
arch/arm/soc/ti_simplelink/cc32xx/soc.c | 6 +-
boards/arm/96b_carbon/96b_carbon_defconfig | 23 +-
boards/arm/96b_nitrogen/96b_nitrogen_defconfig | 3 +
.../arm/arduino_101_ble/arduino_101_ble_defconfig | 3 +
boards/arm/bbc_microbit/bbc_microbit_defconfig | 3 +
boards/arm/cc3200_launchxl/Kconfig.defconfig | 3 +
boards/arm/cc3220sf_launchxl/Kconfig.board | 6 +
boards/arm/cc3220sf_launchxl/Kconfig.defconfig | 9 +
boards/arm/cc3220sf_launchxl/Makefile | 4 +
boards/arm/cc3220sf_launchxl/board.h | 25 +
.../cc3220sf_launchxl/cc3220sf_launchxl_defconfig | 28 +
boards/arm/cc3220sf_launchxl/dbghdr.c | 24 +
.../cc3220sf_launchxl/doc/cc3220sf_launchxl.rst | 222 +
boards/arm/cc3220sf_launchxl/pinmux.c | 121 +
.../arm/cc3220sf_launchxl/support/CC3220SF.ccxml | 14 +
.../cc3220sf_launchxl/support/cc3220_xds110.cfg | 45 +
.../arm/cc3220sf_launchxl/support/gdbinit_xds110 | 16 +
boards/arm/curie_ble/curie_ble_defconfig | 3 +
boards/arm/disco_l475_iot1/Kconfig.board | 10 +
boards/arm/disco_l475_iot1/Kconfig.defconfig | 90 +
boards/arm/disco_l475_iot1/Makefile | 2 +
boards/arm/disco_l475_iot1/board.h | 41 +
.../arm/disco_l475_iot1/disco_l475_iot1_defconfig | 58 +
boards/arm/disco_l475_iot1/doc/disco_l475_iot1.rst | 245 +
.../disco_l475_iot1/doc/img/disco_l475_iot1.jpg | Bin 0 -> 1471155 bytes
boards/arm/frdm_kl25z/Kconfig.board | 11 +
boards/arm/frdm_kl25z/Kconfig.defconfig | 108 +
boards/arm/frdm_kl25z/Makefile | 10 +
boards/arm/frdm_kl25z/board.h | 44 +
boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg | Bin 0 -> 15127 bytes
boards/arm/frdm_kl25z/doc/frdm_kl25z.rst | 173 +
boards/arm/frdm_kl25z/frdm_kl25z_defconfig | 12 +
boards/arm/frdm_kl25z/pinmux.c | 70 +
boards/arm/nrf51_blenano/nrf51_blenano_defconfig | 3 +
boards/arm/nrf51_pca10028/nrf51_pca10028_defconfig | 3 +
.../nrf52840_pca10056/nrf52840_pca10056_defconfig | 3 +
boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig | 3 +
boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig | 3 +
boards/arm/nucleo_f401re/nucleo_f401re_defconfig | 24 +-
boards/arm/nucleo_f411re/nucleo_f411re_defconfig | 25 +-
boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig | 3 +-
.../quark_se_c1000_ble_defconfig | 3 +
drivers/clock_control/Kconfig | 2 -
drivers/clock_control/Kconfig.stm32 | 46 +
drivers/clock_control/Kconfig.stm32f4x | 141 -
drivers/clock_control/Makefile | 2 +-
drivers/clock_control/stm32_ll_clock.c | 9 +
drivers/clock_control/stm32_ll_clock.h | 1 +
drivers/clock_control/stm32f3x_ll_clock.c | 8 +
drivers/clock_control/stm32f4x_clock.c | 350 --
drivers/clock_control/stm32f4x_ll_clock.c | 52 +
drivers/clock_control/stm32l4x_ll_clock.c | 8 +
drivers/dma/dma_stm32f4x.c | 11 +-
drivers/gpio/gpio_stm32.c | 35 +-
drivers/gpio/gpio_stm32.h | 6 +-
drivers/i2c/Kconfig | 8 +
drivers/i2c/Kconfig.gpio | 158 +
drivers/i2c/Makefile | 2 +
drivers/i2c/i2c_bitbang.c | 279 ++
drivers/i2c/i2c_bitbang.h | 57 +
drivers/i2c/i2c_gpio.c | 149 +
drivers/pinmux/Makefile | 1 +
.../pinmux/stm32/pinmux_board_disco_l475_iot1.c | 64 +
drivers/pinmux/stm32/pinmux_stm32.c | 21 +-
drivers/pinmux/stm32/pinmux_stm32f4.h | 14 +-
drivers/pwm/pwm_stm32.c | 43 +-
drivers/pwm/pwm_stm32.h | 4 -
drivers/serial/Kconfig | 2 +
drivers/serial/Kconfig.mcux_lpsci | 32 +
drivers/serial/Kconfig.stellaris | 48 -
drivers/serial/Makefile | 1 +
drivers/serial/uart_cc32xx.c | 2 +-
drivers/serial/uart_mcux_lpsci.c | 308 ++
drivers/serial/uart_stellaris.c | 34 +-
drivers/serial/uart_stellaris.h | 16 -
drivers/serial/uart_stm32.c | 21 +-
drivers/serial/uart_stm32.h | 4 -
dts/arm/96b_carbon.dts | 4 +-
dts/arm/96b_carbon.fixup | 5 +-
dts/arm/96b_nitrogen.dts | 26 +
dts/arm/96b_nitrogen.fixup | 3 +
dts/arm/Makefile | 14 +
dts/arm/arduino_101_ble.dts | 25 +
dts/arm/arduino_101_ble.fixup | 3 +
dts/arm/bbc_microbit.dts | 24 +
dts/arm/bbc_microbit.fixup | 3 +
dts/arm/cc3200_launchxl.dts | 5 +-
dts/arm/cc3220sf_launchxl.dts | 23 +
dts/arm/cc3220sf_launchxl.fixup | 1 +
dts/arm/curie_ble.dts | 25 +
dts/arm/curie_ble.fixup | 3 +
dts/arm/disco_l475_iot1.dts | 24 +
dts/arm/disco_l475_iot1.fixup | 32 +
dts/arm/frdm_k64f.dts | 4 +-
dts/arm/frdm_k64f.fixup | 12 +-
dts/arm/frdm_kl25z.dts | 23 +
dts/arm/frdm_kl25z.fixup | 1 +
dts/arm/frdm_kw41z.dts | 1 +
dts/arm/frdm_kw41z.fixup | 2 +-
dts/arm/hexiwear_k64.dts | 4 +-
dts/arm/hexiwear_k64.fixup | 12 +-
dts/arm/hexiwear_kw40z.dts | 2 +-
dts/arm/hexiwear_kw40z.fixup | 2 +-
dts/arm/nordic/nrf51822.dtsi | 31 +
dts/arm/nordic/nrf52840.dtsi | 38 +
dts/arm/nrf51_blenano.dts | 25 +
dts/arm/nrf51_blenano.fixup | 3 +
dts/arm/nrf51_pca10028.dts | 25 +
dts/arm/nrf51_pca10028.fixup | 3 +
dts/arm/nrf52840_pca10056.dts | 26 +
dts/arm/nrf52840_pca10056.fixup | 3 +
dts/arm/nrf52_blenano2.dts | 26 +
dts/arm/nrf52_blenano2.fixup | 3 +
dts/arm/nrf52_pca10040.dts | 26 +
dts/arm/nrf52_pca10040.fixup | 3 +
dts/arm/nucleo_f103rb.dts | 2 +-
dts/arm/nucleo_f103rb.fixup | 2 +-
dts/arm/nucleo_f334r8.dts | 2 +-
dts/arm/nucleo_f334r8.fixup | 2 +-
dts/arm/nucleo_f401re.dts | 4 +-
dts/arm/nucleo_f401re.fixup | 5 +-
dts/arm/nucleo_f411re.dts | 4 +-
dts/arm/nucleo_f411re.fixup | 5 +-
dts/arm/nucleo_l476rg.dts | 2 +-
dts/arm/nucleo_l476rg.fixup | 10 +-
dts/arm/nxp/nxp_kl25z.dtsi | 32 +
dts/arm/nxp/nxp_kw41z.dtsi | 1 -
dts/arm/olimexino_stm32.dts | 2 +-
dts/arm/olimexino_stm32.fixup | 6 +-
dts/arm/qemu_cortex_m3.dts | 34 +
dts/arm/qemu_cortex_m3.fixup | 1 +
dts/arm/quark_se_c1000_ble.dts | 25 +
dts/arm/quark_se_c1000_ble.fixup | 3 +
dts/arm/st/mem.h | 3 +
dts/arm/st/stm32l475.dtsi | 59 +
dts/arm/st/stm32l476.dtsi | 54 +-
dts/arm/stm3210c_eval.dts | 2 +-
dts/arm/stm3210c_eval.fixup | 2 +-
dts/arm/stm32373c_eval.dts | 2 +-
dts/arm/stm32373c_eval.fixup | 2 +-
dts/arm/stm32_mini_a15.dts | 2 +-
dts/arm/stm32_mini_a15.fixup | 2 +-
dts/arm/ti/{cc32xx_launchxl.dtsi => cc32xx.dtsi} | 15 +-
dts/arm/ti/lm3s6965.dtsi | 45 +
dts/arm/ti/mem.h | 19 +
dts/arm/v2m_beetle.dts | 4 +-
dts/arm/v2m_beetle.fixup | 4 +-
dts/arm/yaml/nxp,kinetis-lpsci.yaml | 31 +
dts/arm/yaml/ti,stellaris-uart.yaml | 30 +
dts/common/yaml/uart.yaml | 2 +-
ext/hal/nxp/mcux/drivers/Makefile | 1 +
ext/hal/st/stm32cube/Kbuild | 1 +
ext/hal/st/stm32cube/stm32f1xx/README | 6 +-
.../drivers/include/Legacy/stm32_hal_legacy.h | 254 +-
.../drivers/include/stm32_assert_template.h | 75 +
.../stm32f1xx/drivers/include/stm32f1xx_hal.h | 67 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_adc.h | 148 +-
.../drivers/include/stm32f1xx_hal_adc_ex.h | 127 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_can.h | 445 +-
.../drivers/include/stm32f1xx_hal_can_ex.h | 13 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_cec.h | 325 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_conf.h | 144 +-
.../drivers/include/stm32f1xx_hal_cortex.h | 266 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_crc.h | 14 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_dac.h | 42 +-
.../drivers/include/stm32f1xx_hal_dac_ex.h | 20 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_def.h | 54 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_dma.h | 259 +-
.../drivers/include/stm32f1xx_hal_dma_ex.h | 51 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_eth.h | 946 ++--
.../drivers/include/stm32f1xx_hal_flash.h | 40 +-
.../drivers/include/stm32f1xx_hal_flash_ex.h | 304 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_gpio.h | 178 +-
.../drivers/include/stm32f1xx_hal_gpio_ex.h | 85 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_hcd.h | 22 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_i2c.h | 600 +--
.../stm32f1xx/drivers/include/stm32f1xx_hal_i2s.h | 254 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_irda.h | 366 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_iwdg.h | 235 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_mmc.h | 718 +++
.../stm32f1xx/drivers/include/stm32f1xx_hal_nand.h | 249 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_nor.h | 18 +-
.../drivers/include/stm32f1xx_hal_pccard.h | 29 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_pcd.h | 120 +-
.../drivers/include/stm32f1xx_hal_pcd_ex.h | 4 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_pwr.h | 20 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_rcc.h | 494 +-
.../drivers/include/stm32f1xx_hal_rcc_ex.h | 152 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_rtc.h | 52 +-
.../drivers/include/stm32f1xx_hal_rtc_ex.h | 104 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_sd.h | 646 +--
.../drivers/include/stm32f1xx_hal_smartcard.h | 458 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_spi.h | 483 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_sram.h | 14 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_tim.h | 362 +-
.../drivers/include/stm32f1xx_hal_tim_ex.h | 47 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_uart.h | 504 ++-
.../drivers/include/stm32f1xx_hal_usart.h | 400 +-
.../stm32f1xx/drivers/include/stm32f1xx_hal_wwdg.h | 177 +-
.../stm32f1xx/drivers/include/stm32f1xx_ll_adc.h | 3950 ++++++++++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_bus.h | 1033 +++++
.../drivers/include/stm32f1xx_ll_cortex.h | 658 +++
.../stm32f1xx/drivers/include/stm32f1xx_ll_crc.h | 212 +
.../stm32f1xx/drivers/include/stm32f1xx_ll_dac.h | 1349 ++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_dma.h | 1978 ++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_exti.h | 906 ++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_fsmc.h | 812 ++--
.../stm32f1xx/drivers/include/stm32f1xx_ll_gpio.h | 2381 ++++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_i2c.h | 1802 ++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h | 329 ++
.../stm32f1xx/drivers/include/stm32f1xx_ll_pwr.h | 458 ++
.../stm32f1xx/drivers/include/stm32f1xx_ll_rcc.h | 2309 ++++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_rtc.h | 1021 +++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_sdmmc.h | 467 +-
.../stm32f1xx/drivers/include/stm32f1xx_ll_spi.h | 1922 ++++++++
.../drivers/include/stm32f1xx_ll_system.h | 592 +++
.../stm32f1xx/drivers/include/stm32f1xx_ll_tim.h | 3837 ++++++++++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_usart.h | 2589 +++++++++++
.../stm32f1xx/drivers/include/stm32f1xx_ll_usb.h | 4 +-
.../stm32f1xx/drivers/include/stm32f1xx_ll_utils.h | 284 ++
.../stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h | 342 ++
.../stm32f1xx/drivers/src/stm32f1xx_hal.c | 106 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_adc.c | 52 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_adc_ex.c | 104 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_can.c | 988 ++--
.../stm32f1xx/drivers/src/stm32f1xx_hal_cec.c | 722 +--
.../stm32f1xx/drivers/src/stm32f1xx_hal_cortex.c | 199 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_crc.c | 15 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_dac.c | 12 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_dac_ex.c | 16 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_dma.c | 734 +--
.../stm32f1xx/drivers/src/stm32f1xx_hal_eth.c | 347 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_flash.c | 170 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_flash_ex.c | 77 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_gpio.c | 130 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_gpio_ex.c | 4 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c | 125 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c | 4184 +++++++++++------
.../stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c | 986 ++--
.../stm32f1xx/drivers/src/stm32f1xx_hal_irda.c | 1708 ++++---
.../stm32f1xx/drivers/src/stm32f1xx_hal_iwdg.c | 316 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c | 2598 +++++++++++
.../drivers/src/stm32f1xx_hal_msp_template.c | 4 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_nand.c | 1075 ++++-
.../stm32f1xx/drivers/src/stm32f1xx_hal_nor.c | 38 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_pccard.c | 54 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c | 258 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_pcd_ex.c | 30 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_pwr.c | 33 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_rcc.c | 109 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_rcc_ex.c | 139 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_rtc.c | 210 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_rtc_ex.c | 31 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_sd.c | 4762 +++++++++-----------
.../drivers/src/stm32f1xx_hal_smartcard.c | 1853 +++++---
.../stm32f1xx/drivers/src/stm32f1xx_hal_spi.c | 3632 +++++++++------
.../stm32f1xx/drivers/src/stm32f1xx_hal_spi_ex.c | 54 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_sram.c | 16 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_tim.c | 236 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_tim_ex.c | 46 +-
.../stm32f1xx_hal_timebase_rtc_alarm_template.c | 307 ++
.../src/stm32f1xx_hal_timebase_tim_template.c | 184 +
.../stm32f1xx/drivers/src/stm32f1xx_hal_uart.c | 1703 ++++---
.../stm32f1xx/drivers/src/stm32f1xx_hal_usart.c | 1265 ++++--
.../stm32f1xx/drivers/src/stm32f1xx_hal_wwdg.c | 390 +-
.../stm32f1xx/drivers/src/stm32f1xx_ll_adc.c | 903 ++++
.../stm32f1xx/drivers/src/stm32f1xx_ll_crc.c | 126 +
.../stm32f1xx/drivers/src/stm32f1xx_ll_dac.c | 274 ++
.../stm32f1xx/drivers/src/stm32f1xx_ll_dma.c | 331 ++
.../stm32f1xx/drivers/src/stm32f1xx_ll_exti.c | 232 +
.../stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c | 362 +-
.../stm32f1xx/drivers/src/stm32f1xx_ll_gpio.c | 265 ++
.../stm32f1xx/drivers/src/stm32f1xx_ll_i2c.c | 239 +
.../stm32f1xx/drivers/src/stm32f1xx_ll_pwr.c | 103 +
.../stm32f1xx/drivers/src/stm32f1xx_ll_rcc.c | 507 +++
.../stm32f1xx/drivers/src/stm32f1xx_ll_rtc.c | 558 +++
.../stm32f1xx/drivers/src/stm32f1xx_ll_sdmmc.c | 1184 ++++-
.../stm32f1xx/drivers/src/stm32f1xx_ll_spi.c | 562 +++
.../stm32f1xx/drivers/src/stm32f1xx_ll_tim.c | 1216 +++++
.../stm32f1xx/drivers/src/stm32f1xx_ll_usart.c | 451 ++
.../stm32f1xx/drivers/src/stm32f1xx_ll_usb.c | 167 +-
.../stm32f1xx/drivers/src/stm32f1xx_ll_utils.c | 623 +++
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xb.h | 962 ++--
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xe.h | 1032 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101x6.h | 839 +---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h | 847 +---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xe.h | 966 ++--
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xg.h | 1045 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102x6.h | 1187 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102xb.h | 1191 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103x6.h | 1215 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xb.h | 1235 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xe.h | 1348 ++----
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xg.h | 1370 ++----
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f105xc.h | 989 ++--
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f107xc.h | 1135 ++---
ext/hal/st/stm32cube/stm32f1xx/soc/stm32f1xx.h | 12 +-
.../st/stm32cube/stm32f1xx/soc/system_stm32f1xx.c | 112 +-
.../st/stm32cube/stm32f1xx/soc/system_stm32f1xx.h | 10 +-
include/arch/arm/cortex_m/scripts/linker.ld | 35 +-
.../drivers/clock_control/stm32_clock_control.h | 2 -
.../drivers/clock_control/stm32f4_clock_control.h | 134 -
include/section_tags.h | 1 -
include/sections.h | 2 -
scripts/sanity_chk/arches/arm.ini | 3 +-
tests/kernel/xip/testcase.ini | 2 +-
337 files changed, 69436 insertions(+), 29054 deletions(-)
delete mode 100644 arch/arm/soc/st_stm32/stm32f4/rcc_registers.h
create mode 100644 arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg
delete mode 100644 arch/arm/soc/ti_lm3s6965/scp.c
delete mode 100644 arch/arm/soc/ti_lm3s6965/scp.h
create mode 100644 arch/arm/soc/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf
create mode 100644 boards/arm/cc3220sf_launchxl/Kconfig.board
create mode 100644 boards/arm/cc3220sf_launchxl/Kconfig.defconfig
create mode 100644 boards/arm/cc3220sf_launchxl/Makefile
create mode 100644 boards/arm/cc3220sf_launchxl/board.h
create mode 100644 boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig
create mode 100644 boards/arm/cc3220sf_launchxl/dbghdr.c
create mode 100644 boards/arm/cc3220sf_launchxl/doc/cc3220sf_launchxl.rst
create mode 100644 boards/arm/cc3220sf_launchxl/pinmux.c
create mode 100644 boards/arm/cc3220sf_launchxl/support/CC3220SF.ccxml
create mode 100644 boards/arm/cc3220sf_launchxl/support/cc3220_xds110.cfg
create mode 100644 boards/arm/cc3220sf_launchxl/support/gdbinit_xds110
create mode 100644 boards/arm/disco_l475_iot1/Kconfig.board
create mode 100644 boards/arm/disco_l475_iot1/Kconfig.defconfig
create mode 100644 boards/arm/disco_l475_iot1/Makefile
create mode 100644 boards/arm/disco_l475_iot1/board.h
create mode 100644 boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig
create mode 100644 boards/arm/disco_l475_iot1/doc/disco_l475_iot1.rst
create mode 100644 boards/arm/disco_l475_iot1/doc/img/disco_l475_iot1.jpg
create mode 100644 boards/arm/frdm_kl25z/Kconfig.board
create mode 100644 boards/arm/frdm_kl25z/Kconfig.defconfig
create mode 100644 boards/arm/frdm_kl25z/Makefile
create mode 100644 boards/arm/frdm_kl25z/board.h
create mode 100644 boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg
create mode 100644 boards/arm/frdm_kl25z/doc/frdm_kl25z.rst
create mode 100644 boards/arm/frdm_kl25z/frdm_kl25z_defconfig
create mode 100644 boards/arm/frdm_kl25z/pinmux.c
delete mode 100644 drivers/clock_control/Kconfig.stm32f4x
delete mode 100644 drivers/clock_control/stm32f4x_clock.c
create mode 100644 drivers/clock_control/stm32f4x_ll_clock.c
create mode 100644 drivers/i2c/Kconfig.gpio
create mode 100644 drivers/i2c/i2c_bitbang.c
create mode 100644 drivers/i2c/i2c_bitbang.h
create mode 100644 drivers/i2c/i2c_gpio.c
create mode 100644 drivers/pinmux/stm32/pinmux_board_disco_l475_iot1.c
create mode 100644 drivers/serial/Kconfig.mcux_lpsci
create mode 100644 drivers/serial/uart_mcux_lpsci.c
delete mode 100644 drivers/serial/uart_stellaris.h
create mode 100644 dts/arm/96b_nitrogen.dts
create mode 100644 dts/arm/96b_nitrogen.fixup
create mode 100644 dts/arm/arduino_101_ble.dts
create mode 100644 dts/arm/arduino_101_ble.fixup
create mode 100644 dts/arm/bbc_microbit.dts
create mode 100644 dts/arm/bbc_microbit.fixup
create mode 100644 dts/arm/cc3220sf_launchxl.dts
create mode 100644 dts/arm/cc3220sf_launchxl.fixup
create mode 100644 dts/arm/curie_ble.dts
create mode 100644 dts/arm/curie_ble.fixup
create mode 100644 dts/arm/disco_l475_iot1.dts
create mode 100644 dts/arm/disco_l475_iot1.fixup
create mode 100644 dts/arm/frdm_kl25z.dts
create mode 100644 dts/arm/frdm_kl25z.fixup
create mode 100644 dts/arm/nordic/nrf51822.dtsi
create mode 100644 dts/arm/nordic/nrf52840.dtsi
create mode 100644 dts/arm/nrf51_blenano.dts
create mode 100644 dts/arm/nrf51_blenano.fixup
create mode 100644 dts/arm/nrf51_pca10028.dts
create mode 100644 dts/arm/nrf51_pca10028.fixup
create mode 100644 dts/arm/nrf52840_pca10056.dts
create mode 100644 dts/arm/nrf52840_pca10056.fixup
create mode 100644 dts/arm/nrf52_blenano2.dts
create mode 100644 dts/arm/nrf52_blenano2.fixup
create mode 100644 dts/arm/nrf52_pca10040.dts
create mode 100644 dts/arm/nrf52_pca10040.fixup
create mode 100644 dts/arm/nxp/nxp_kl25z.dtsi
create mode 100644 dts/arm/qemu_cortex_m3.dts
create mode 100644 dts/arm/qemu_cortex_m3.fixup
create mode 100644 dts/arm/quark_se_c1000_ble.dts
create mode 100644 dts/arm/quark_se_c1000_ble.fixup
create mode 100644 dts/arm/st/stm32l475.dtsi
rename dts/arm/ti/{cc32xx_launchxl.dtsi => cc32xx.dtsi} (78%)
create mode 100644 dts/arm/ti/lm3s6965.dtsi
create mode 100644 dts/arm/ti/mem.h
create mode 100644 dts/arm/yaml/nxp,kinetis-lpsci.yaml
create mode 100644 dts/arm/yaml/ti,stellaris-uart.yaml
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32_assert_template.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_mmc.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_adc.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_bus.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_cortex.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_crc.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dac.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dma.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_gpio.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_i2c.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_pwr.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_rcc.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_rtc.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_spi.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_system.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_tim.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usart.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_utils.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_rtc_alarm_template.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_tim_template.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_adc.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_crc.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_dac.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_dma.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_exti.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_gpio.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_i2c.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_pwr.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_rcc.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_rtc.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_spi.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_tim.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usart.c
create mode 100644 ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_utils.c
delete mode 100644 include/drivers/clock_control/stm32f4_clock_control.h
Change-Id: I0a465f75ff94c33373c03951b4d7468476bc3b41
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Diffstat (limited to 'ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h')
| -rw-r--r-- | ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h | 847 |
1 files changed, 207 insertions, 640 deletions
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h index 2909876c1..4e0ddf25d 100644 --- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h +++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f101xb.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@ /**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -134,7 +134,6 @@ typedef enum RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -512,65 +511,65 @@ typedef struct */
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
-
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
@@ -582,44 +581,44 @@ typedef struct * @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -690,14 +689,24 @@ typedef struct #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -862,9 +871,9 @@ typedef struct #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -873,9 +882,9 @@ typedef struct #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -886,15 +895,15 @@ typedef struct #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -904,11 +913,11 @@ typedef struct #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -918,11 +927,11 @@ typedef struct #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -931,10 +940,10 @@ typedef struct #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -953,10 +962,10 @@ typedef struct #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1008,11 +1017,11 @@ typedef struct #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1280,10 +1289,10 @@ typedef struct #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1853,7 +1862,7 @@ typedef struct #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -1908,7 +1917,7 @@ typedef struct #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -1947,7 +1956,7 @@ typedef struct #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -1962,7 +1971,7 @@ typedef struct #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -1977,7 +1986,7 @@ typedef struct #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -1995,7 +2004,7 @@ typedef struct #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2020,7 +2029,7 @@ typedef struct #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2047,7 +2056,7 @@ typedef struct #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2068,7 +2077,7 @@ typedef struct #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2089,7 +2098,7 @@ typedef struct #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2110,7 +2119,7 @@ typedef struct #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2145,7 +2154,7 @@ typedef struct #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2166,7 +2175,7 @@ typedef struct #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2187,7 +2196,7 @@ typedef struct #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2208,7 +2217,7 @@ typedef struct #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2243,7 +2252,7 @@ typedef struct #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2264,7 +2273,7 @@ typedef struct #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2285,7 +2294,7 @@ typedef struct #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2306,7 +2315,7 @@ typedef struct #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2341,7 +2350,7 @@ typedef struct #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2362,7 +2371,7 @@ typedef struct #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2383,7 +2392,7 @@ typedef struct #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2404,7 +2413,7 @@ typedef struct #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2430,440 +2439,6 @@ typedef struct /******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -2926,9 +2501,6 @@ typedef struct #define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -2950,8 +2522,8 @@ typedef struct #define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3010,9 +2582,6 @@ typedef struct #define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3034,7 +2603,6 @@ typedef struct #define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3094,9 +2662,6 @@ typedef struct #define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3118,7 +2683,6 @@ typedef struct #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3178,9 +2742,6 @@ typedef struct #define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3202,7 +2763,6 @@ typedef struct #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3262,9 +2822,6 @@ typedef struct #define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3286,7 +2843,6 @@ typedef struct #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3346,9 +2902,6 @@ typedef struct #define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3370,7 +2923,6 @@ typedef struct #define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4220,10 +3772,6 @@ typedef struct #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -4568,9 +4116,6 @@ typedef struct #define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -4674,8 +4219,6 @@ typedef struct #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5421,8 +4964,8 @@ typedef struct #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -5467,6 +5010,11 @@ typedef struct #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -6053,6 +5601,9 @@ typedef struct #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -6067,6 +5618,8 @@ typedef struct ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) 0U
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -6137,7 +5690,7 @@ typedef struct ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) 0U
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM2) && \
@@ -6158,14 +5711,14 @@ typedef struct ((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) 0U
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) 0U
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
@@ -6182,7 +5735,17 @@ typedef struct ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) 0U
+
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/
@@ -6241,10 +5804,14 @@ typedef struct +#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
|