1 files changed, 46 insertions, 0 deletions
diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32
index 293aaed01..2e9c3ea9b 100644
--- a/drivers/clock_control/Kconfig.stm32
+++ b/drivers/clock_control/Kconfig.stm32
@@ -110,6 +110,52 @@ config CLOCK_STM32_PLL_MULTIPLIER
 
 endif # SOC_SERIES_STM32F3X
 
+if SOC_SERIES_STM32F4X
+
+config CLOCK_STM32_PLL_M_DIVISOR
+	int "Division factor for PLL VCO input clock"
+	depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
+	default 8
+	range 2 63
+	help
+	 PLLM division factor needs to be set correctly to ensure that the VCO
+	 input frequency ranges from 1 to 2 MHz. It is recommended to select a
+	 frequency of 2 MHz to limit PLL jitter.
+	 Allowed values: 2-63
+
+config CLOCK_STM32_PLL_N_MULTIPLIER
+	int "Multiplier factor for PLL VCO output clock"
+	depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
+	default 336
+	range 192 432 if SOC_STM32F401XE
+	range 50 432
+	help
+	 PLLN multiplier factor needs to be set correctly to ensure that the
+	 VCO output frequency is between 100 and 432 MHz, except on STM32F401
+	 where the frequency must be between 192 and 432 MHz.
+	 Allowed values: 50-432 (STM32F401: 192-432)
+
+config CLOCK_STM32_PLL_P_DIVISOR
+	int "PLL division factor for main system clock"
+	depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
+	default 4
+	range 2 8
+	help
+	 PLLP division factor needs to be set correctly to not exceed 84MHz.
+	 Allowed values: 2, 4, 6, 8
+
+config CLOCK_STM32_PLL_Q_DIVISOR
+	int "Division factor for OTG FS, SDIO and RNG clocks"
+	depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL
+	default 7
+	range 2 15
+	help
+	 The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG
+	 need a frequency lower than or equal to 48 MHz to work correctly.
+	 Allowed values: 2-15
+
+endif # SOC_SERIES_STM32F4X
+
 if SOC_SERIES_STM32L4X
 
 config CLOCK_STM32_PLL_M_DIVISOR