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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
/ {
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory {
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
status = "disabled";
};
usart3: uart@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
status = "disabled";
};
uart4: uart@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
interrupts = <52 0>;
status = "disabled";
};
uart5: uart@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
interrupts = <53 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
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