diff options
| author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-03-22 23:46:19 +0800 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-04-03 20:25:24 +0800 |
| commit | 806a98af2fa0784a9c3756d0329ad9381fc975b1 (patch) | |
| tree | d8b8d371fd68619a54d970cb56478e2300af082f /drivers | |
| parent | 45387e17ff74efbc7f6fd39149d18dd7bf439517 (diff) | |
clk: hi3xxx: set clkgate reset as optional
There are not reset registers for all Hi3620 clock gate. So set reset
registers as optional.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/clk-hi3xxx.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/drivers/clk/clk-hi3xxx.c b/drivers/clk/clk-hi3xxx.c index ac1520b4972..11dfb1b6e02 100644 --- a/drivers/clk/clk-hi3xxx.c +++ b/drivers/clk/clk-hi3xxx.c @@ -94,8 +94,10 @@ static int hi3620_clkgate_prepare(struct clk_hw *hw) if (pclk->lock) spin_lock_irqsave(pclk->lock, flags); writel_relaxed(pclk->ebits, pclk->enable + HI3620_DISABLE_OFF); - writel_relaxed(pclk->rbits, pclk->reset + HI3620_DISABLE_OFF); - readl_relaxed(pclk->reset + HI3620_STATUS_OFF); + if (pclk->reset) { + writel_relaxed(pclk->rbits, pclk->reset + HI3620_DISABLE_OFF); + readl_relaxed(pclk->reset + HI3620_STATUS_OFF); + } if (pclk->lock) spin_unlock_irqrestore(pclk->lock, flags); return 0; @@ -149,9 +151,6 @@ static void __init hi3620_clkgate_setup(struct device_node *np) if (of_property_read_string(np, "clock-output-names", &clk_name)) return; - if (of_property_read_u32_array(np, "hisilicon,hi3620-clkreset", - &rdata[0], 2)) - return; if (of_property_read_u32_array(np, "hisilicon,hi3620-clkgate", &gdata[0], 2)) return; @@ -175,8 +174,14 @@ static void __init hi3620_clkgate_setup(struct device_node *np) init->parent_names = parent_names; init->num_parents = 1; - pclk->reset = hs_clk.sctrl + rdata[0]; - pclk->rbits = rdata[1]; + if (of_property_read_u32_array(np, "hisilicon,hi3620-clkreset", + &rdata[0], 2)) { + pclk->reset = 0; + pclk->rbits = 0; + } else { + pclk->reset = hs_clk.sctrl + rdata[0]; + pclk->rbits = rdata[1]; + } pclk->enable = hs_clk.sctrl + gdata[0]; pclk->ebits = gdata[1]; pclk->lock = &hs_clk.lock; |