diff options
| author | Sricharan R <sricharan@codeaurora.org> | 2015-08-08 11:50:30 +0530 |
|---|---|---|
| committer | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2015-09-01 11:30:08 +0100 |
| commit | 6ff0cebeafab549d07a3111e632098e576b61157 (patch) | |
| tree | 3f5078510eeab646a0403099394387b8c5c3cf0d | |
| parent | 056182d136542fccdbb410ef966b6ff6f84b9fba (diff) | |
dts: apq8064: Add generic iommu master bindings data for gfx and mdplegacy/tracking-qcomlt-dt
The gfx and mdp devices are behind iommu-v0 and the driver for
the same is adapted to use generic iommu bindings. So updating the
DT nodes for those device here.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8064.dtsi | 45 |
1 files changed, 13 insertions, 32 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 67e75019a492..e02f41a73e95 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1050,7 +1050,6 @@ gpu: qcom,adreno-3xx@4300000 { compatible = "qcom,adreno-3xx"; - #stream-id-cells = <16>; reg = <0x04300000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = <GIC_SPI 80 0>; @@ -1066,6 +1065,12 @@ <&mmcc GFX3D_AXI_CLK>, <&mmcc MMSS_IMEM_AHB_CLK>; qcom,chipid = <0x03020002>; + + iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 + &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; + qcom,gpu-pwrlevels { compatible = "qcom,gpu-pwrlevels"; qcom,gpu-pwrlevel@0 { @@ -1079,7 +1084,6 @@ mdp: qcom,mdp@5100000 { compatible = "qcom,mdp"; - #stream-id-cells = <2>; reg = <0x05100000 0xf0000>; interrupts = <GIC_SPI 75 0>; connectors = <&hdmi>; @@ -1100,96 +1104,73 @@ <&mmcc HDMI_TV_CLK>, <&mmcc MDP_TV_CLK>, <&mmcc MDP_AXI_CLK>; + + iommus = <&mdp_port0 0 2 + &mdp_port1 0 2>; }; mdp_port0: qcom,iommu@7500000 { compatible = "qcom,iommu-v0"; + #iommu-cells = <2>; clock-names = "smmu_pclk", "iommu_clk"; clocks = <&mmcc SMMU_AHB_CLK>, <&mmcc MDP_AXI_CLK>; - reg-names = "physbase"; reg = <0x07500000 0x100000>; - interrupt-names = - "secure_irq", - "nonsecure_irq"; interrupts = <GIC_SPI 63 0>, <GIC_SPI 64 0>; ncb = <2>; - mmu-masters = <&mdp 0 2>; }; mdp_port1: qcom,iommu@7600000 { compatible = "qcom,iommu"; + #iommu-cells = <2>; clock-names = "smmu_pclk", "iommu_clk"; clocks = <&mmcc SMMU_AHB_CLK>, <&mmcc MDP_AXI_CLK>; - reg-names = "physbase"; reg = <0x07600000 0x100000>; - interrupt-names = - "secure_irq", - "nonsecure_irq"; interrupts = <GIC_SPI 61 0>, <GIC_SPI 62 0>; ncb = <2>; - mmu-masters = <&mdp 0 2>; }; gfx3d: qcom,iommu@7c00000 { compatible = "qcom,iommu-v0"; + #iommu-cells = <16>; clock-names = "smmu_pclk", "iommu_clk"; clocks = <&mmcc SMMU_AHB_CLK>, <&mmcc GFX3D_AXI_CLK>; - reg-names = "physbase"; reg = <0x07c00000 0x100000>; - interrupt-names = - "secure_irq", - "nonsecure_irq"; interrupts = <GIC_SPI 69 0>, <GIC_SPI 70 0>; ncb = <3>; - ttbr-split = <1>; - mmu-masters = - /* gfx3d_user: */ - <&gpu 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>, - /* gfx3d_priv: */ - <&gpu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; }; gfx3d1: qcom,iommu@7d00000 { compatible = "qcom,iommu-v0"; + #iommu-cells = <16>; clock-names = "smmu_pclk", "iommu_clk"; clocks = <&mmcc SMMU_AHB_CLK>, <&mmcc GFX3D_AXI_CLK>; - reg-names = "physbase"; reg = <0x07d00000 0x100000>; - interrupt-names = - "secure_irq", - "nonsecure_irq"; interrupts = <GIC_SPI 210 0>, <GIC_SPI 211 0>; ncb = <3>; - ttbr-split = <1>; - mmu-masters = - /* gfx3d_user: */ - <&gpu 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>, - /* gfx3d_priv: */ - <&gpu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; }; }; }; |