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-rw-r--r--drivers/gpu/msm/adreno_a5xx.c8
-rw-r--r--drivers/gpu/msm/adreno_a6xx.c25
-rw-r--r--drivers/gpu/msm/adreno_a6xx_gmu.c3
-rw-r--r--drivers/gpu/msm/adreno_a6xx_snapshot.c74
4 files changed, 97 insertions, 13 deletions
diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c
index 6c0ba1a5af34..ad16d09f33bb 100644
--- a/drivers/gpu/msm/adreno_a5xx.c
+++ b/drivers/gpu/msm/adreno_a5xx.c
@@ -2843,11 +2843,11 @@ static void a5xx_gpmu_int_callback(struct adreno_device *adreno_dev, int bit)
}
/*
- * a5x_gpc_err_int_callback() - Isr for GPC error interrupts
+ * a5xx_gpc_err_int_callback() - Isr for GPC error interrupts
* @adreno_dev: Pointer to device
* @bit: Interrupt bit
*/
-void a5x_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)
+static void a5xx_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -2857,7 +2857,7 @@ void a5x_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)
* with help of register dump.
*/
- dev_crit(device->dev, "RBBM: GPC error\n");
+ dev_crit_ratelimited(device->dev, "RBBM: GPC error\n");
adreno_irqctrl(adreno_dev, 0);
/* Trigger a fault in the dispatcher - this will effect a restart */
@@ -2895,7 +2895,7 @@ static struct adreno_irq_funcs a5xx_irq_funcs[32] = {
ADRENO_IRQ_CALLBACK(a5xx_err_callback),
/* 6 - RBBM_ATB_ASYNC_OVERFLOW */
ADRENO_IRQ_CALLBACK(a5xx_err_callback),
- ADRENO_IRQ_CALLBACK(a5x_gpc_err_int_callback), /* 7 - GPC_ERR */
+ ADRENO_IRQ_CALLBACK(a5xx_gpc_err_int_callback), /* 7 - GPC_ERR */
ADRENO_IRQ_CALLBACK(a5xx_preempt_callback),/* 8 - CP_SW */
ADRENO_IRQ_CALLBACK(a5xx_cp_hw_err_callback), /* 9 - CP_HW_ERROR */
/* 10 - CP_CCU_FLUSH_DEPTH_TS */
diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c
index d1821a7c9076..1a94e7df4e30 100644
--- a/drivers/gpu/msm/adreno_a6xx.c
+++ b/drivers/gpu/msm/adreno_a6xx.c
@@ -1362,6 +1362,29 @@ static void a6xx_cp_callback(struct adreno_device *adreno_dev, int bit)
adreno_dispatcher_schedule(device);
}
+/*
+ * a6xx_gpc_err_int_callback() - Isr for GPC error interrupts
+ * @adreno_dev: Pointer to device
+ * @bit: Interrupt bit
+ */
+static void a6xx_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+
+ /*
+ * GPC error is typically the result of mistake SW programming.
+ * Force GPU fault for this interrupt so that we can debug it
+ * with help of register dump.
+ */
+
+ dev_crit_ratelimited(device->dev, "RBBM: GPC error\n");
+ adreno_irqctrl(adreno_dev, 0);
+
+ /* Trigger a fault in the dispatcher - this will effect a restart */
+ adreno_set_gpu_fault(adreno_dev, ADRENO_SOFT_FAULT);
+ adreno_dispatcher_schedule(device);
+}
+
#define A6XX_INT_MASK \
((1 << A6XX_INT_CP_AHB_ERROR) | \
(1 << A6XX_INT_ATB_ASYNCFIFO_OVERFLOW) | \
@@ -1387,7 +1410,7 @@ static struct adreno_irq_funcs a6xx_irq_funcs[32] = {
ADRENO_IRQ_CALLBACK(NULL), /* 5 - UNUSED */
/* 6 - RBBM_ATB_ASYNC_OVERFLOW */
ADRENO_IRQ_CALLBACK(a6xx_err_callback),
- ADRENO_IRQ_CALLBACK(NULL), /* 7 - GPC_ERR */
+ ADRENO_IRQ_CALLBACK(a6xx_gpc_err_int_callback), /* 7 - GPC_ERR */
ADRENO_IRQ_CALLBACK(a6xx_preemption_callback),/* 8 - CP_SW */
ADRENO_IRQ_CALLBACK(a6xx_cp_hw_err_callback), /* 9 - CP_HW_ERROR */
ADRENO_IRQ_CALLBACK(NULL), /* 10 - CP_CCU_FLUSH_DEPTH_TS */
diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c
index c580165ab7f9..e46118ac548d 100644
--- a/drivers/gpu/msm/adreno_a6xx_gmu.c
+++ b/drivers/gpu/msm/adreno_a6xx_gmu.c
@@ -829,6 +829,9 @@ static bool a6xx_gmu_cx_is_on(struct kgsl_device *device)
{
unsigned int val;
+ if (ADRENO_QUIRK(ADRENO_DEVICE(device), ADRENO_QUIRK_CX_GDSC))
+ return regulator_is_enabled(KGSL_GMU_DEVICE(device)->cx_gdsc);
+
gmu_core_regread(device, A6XX_GPU_CC_CX_GDSCR, &val);
return (val & BIT(31));
}
diff --git a/drivers/gpu/msm/adreno_a6xx_snapshot.c b/drivers/gpu/msm/adreno_a6xx_snapshot.c
index 715750b18005..4e444b7a0e2d 100644
--- a/drivers/gpu/msm/adreno_a6xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a6xx_snapshot.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#include "adreno.h"
@@ -621,6 +621,49 @@ static struct a6xx_shader_block a6xx_shader_blocks[] = {
{A6XX_HLSQ_INDIRECT_META, 0x40,}
};
+static struct a6xx_shader_block a615_shader_blocks[] = {
+ {A6XX_TP0_TMO_DATA, 0x200},
+ {A6XX_TP0_SMO_DATA, 0x80,},
+ {A6XX_TP0_MIPMAP_BASE_DATA, 0x3C0},
+ {A6XX_TP1_TMO_DATA, 0x200},
+ {A6XX_TP1_SMO_DATA, 0x80,},
+ {A6XX_TP1_MIPMAP_BASE_DATA, 0x3C0},
+ {A6XX_SP_LB_0_DATA, 0x800},
+ {A6XX_SP_LB_1_DATA, 0x800},
+ {A6XX_SP_LB_2_DATA, 0x800},
+ {A6XX_SP_LB_3_DATA, 0x800},
+ {A6XX_SP_LB_4_DATA, 0x800},
+ {A6XX_SP_LB_5_DATA, 0x200},
+ {A6XX_SP_CB_BINDLESS_DATA, 0x800},
+ {A6XX_SP_CB_LEGACY_DATA, 0x280,},
+ {A6XX_SP_UAV_DATA, 0x80,},
+ {A6XX_SP_CB_BINDLESS_TAG, 0x80,},
+ {A6XX_SP_TMO_UMO_TAG, 0x80,},
+ {A6XX_SP_SMO_TAG, 0x80},
+ {A6XX_SP_STATE_DATA, 0x3F},
+ {A6XX_HLSQ_CHUNK_CVS_RAM, 0x1C0},
+ {A6XX_HLSQ_CHUNK_CPS_RAM, 0x280},
+ {A6XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40,},
+ {A6XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40,},
+ {A6XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x4,},
+ {A6XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x4,},
+ {A6XX_HLSQ_CVS_MISC_RAM, 0x1C0},
+ {A6XX_HLSQ_CPS_MISC_RAM, 0x580},
+ {A6XX_HLSQ_INST_RAM, 0x800},
+ {A6XX_HLSQ_GFX_CVS_CONST_RAM, 0x800},
+ {A6XX_HLSQ_GFX_CPS_CONST_RAM, 0x800},
+ {A6XX_HLSQ_CVS_MISC_RAM_TAG, 0x8,},
+ {A6XX_HLSQ_CPS_MISC_RAM_TAG, 0x4,},
+ {A6XX_HLSQ_INST_RAM_TAG, 0x80,},
+ {A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0xC,},
+ {A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10},
+ {A6XX_HLSQ_PWR_REST_RAM, 0x28},
+ {A6XX_HLSQ_PWR_REST_TAG, 0x14},
+ {A6XX_HLSQ_DATAPATH_META, 0x40,},
+ {A6XX_HLSQ_FRONTEND_META, 0x40},
+ {A6XX_HLSQ_INDIRECT_META, 0x40,}
+};
+
static struct kgsl_memdesc a6xx_capturescript;
static struct kgsl_memdesc a6xx_crashdump_registers;
static bool crash_dump_valid;
@@ -2093,10 +2136,18 @@ void a6xx_crashdump_init(struct adreno_device *adreno_dev)
* read the data) and then a block specific number of bytes to hold
* the data
*/
- for (i = 0; i < ARRAY_SIZE(a6xx_shader_blocks); i++) {
- script_size += 32 * A6XX_NUM_SHADER_BANKS;
- data_size += a6xx_shader_blocks[i].sz * sizeof(unsigned int) *
- A6XX_NUM_SHADER_BANKS;
+ if (adreno_is_a615_family(adreno_dev)) {
+ for (i = 0; i < ARRAY_SIZE(a615_shader_blocks); i++) {
+ script_size += 32 * A6XX_NUM_SHADER_BANKS;
+ data_size += a615_shader_blocks[i].sz *
+ sizeof(unsigned int) * A6XX_NUM_SHADER_BANKS;
+ }
+ } else {
+ for (i = 0; i < ARRAY_SIZE(a6xx_shader_blocks); i++) {
+ script_size += 32 * A6XX_NUM_SHADER_BANKS;
+ data_size += a6xx_shader_blocks[i].sz *
+ sizeof(unsigned int) * A6XX_NUM_SHADER_BANKS;
+ }
}
/* Calculate the script and data size for MVC registers */
@@ -2202,9 +2253,16 @@ void a6xx_crashdump_init(struct adreno_device *adreno_dev)
}
/* Program each shader block */
- for (i = 0; i < ARRAY_SIZE(a6xx_shader_blocks); i++) {
- ptr += _a6xx_crashdump_init_shader(&a6xx_shader_blocks[i], ptr,
- &offset);
+ if (adreno_is_a615_family(adreno_dev)) {
+ for (i = 0; i < ARRAY_SIZE(a615_shader_blocks); i++)
+ ptr += _a6xx_crashdump_init_shader(
+ &a615_shader_blocks[i], ptr,
+ &offset);
+ } else {
+ for (i = 0; i < ARRAY_SIZE(a6xx_shader_blocks); i++)
+ ptr += _a6xx_crashdump_init_shader(
+ &a6xx_shader_blocks[i], ptr,
+ &offset);
}
/* Program the capturescript for the MVC regsiters */
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-24 12:52:07 +0000