1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
|
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&soc {
cam_csiphy0: qcom,csiphy@ac65000 {
cell-index = <0>;
compatible = "qcom,csiphy-v1.0", "qcom,csiphy";
reg = <0x0ac65000 0x1000>;
reg-names = "csiphy";
reg-cam-base = <0x65000>;
interrupts = <0 477 0>;
interrupt-names = "csiphy";
regulator-names = "gdscr", "refgen";
gdscr-supply = <&titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-voltage = <1200000>;
mipi-csi-vdd-supply = <&pm8998_l1>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY0_CLK>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;
clock-names = "camnoc_axi_clk",
"soc_ahb_clk",
"slow_ahb_src_clk",
"cpas_ahb_clk",
"cphy_rx_clk_src",
"csiphy0_clk",
"csi0phytimer_clk_src",
"csi0phytimer_clk";
clock-cntl-level = "turbo";
clock-rates =
<0 0 0 0 384000000 0 269333333 0>;
status = "ok";
};
cam_csiphy1: qcom,csiphy@ac66000{
cell-index = <1>;
compatible = "qcom,csiphy-v1.0", "qcom,csiphy";
reg = <0xac66000 0x1000>;
reg-names = "csiphy";
reg-cam-base = <0x66000>;
interrupts = <0 478 0>;
interrupt-names = "csiphy";
regulator-names = "gdscr", "refgen";
gdscr-supply = <&titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-voltage = <1200000>;
mipi-csi-vdd-supply = <&pm8998_l1>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY1_CLK>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;
clock-names = "camnoc_axi_clk",
"soc_ahb_clk",
"slow_ahb_src_clk",
"cpas_ahb_clk",
"cphy_rx_clk_src",
"csiphy1_clk",
"csi1phytimer_clk_src",
"csi1phytimer_clk";
clock-cntl-level = "turbo";
clock-rates =
<0 0 0 0 384000000 0 269333333 0>;
status = "ok";
};
cam_csiphy2: qcom,csiphy@ac67000 {
cell-index = <2>;
compatible = "qcom,csiphy-v1.0", "qcom,csiphy";
reg = <0xac67000 0x1000>;
reg-names = "csiphy";
reg-cam-base = <0x67000>;
interrupts = <0 479 0>;
interrupt-names = "csiphy";
regulator-names = "gdscr", "refgen";
gdscr-supply = <&titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-voltage = <1200000>;
mipi-csi-vdd-supply = <&pm8998_l1>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY2_CLK>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;
clock-names = "camnoc_axi_clk",
"soc_ahb_clk",
"slow_ahb_src_clk",
"cpas_ahb_clk",
"cphy_rx_clk_src",
"csiphy2_clk",
"csi2phytimer_clk_src",
"csi2phytimer_clk";
clock-cntl-level = "turbo";
clock-rates =
<0 0 0 0 384000000 0 269333333 0>;
status = "ok";
};
cam_csiphy3: qcom,csiphy@ac68000 {
cell-index = <3>;
compatible = "qcom,csiphy-v1.0", "qcom,csiphy";
reg = <0xac68000 0x1000>;
reg-names = "csiphy";
reg-cam-base = <0x68000>;
interrupts = <0 448 0>;
interrupt-names = "csiphy";
regulator-names = "gdscr", "refgen";
gdscr-supply = <&titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-voltage = <1200000>;
mipi-csi-vdd-supply = <&pm8998_l1>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY3_CLK>,
<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>;
clock-names = "camnoc_axi_clk",
"soc_ahb_clk",
"slow_ahb_src_clk",
"cpas_ahb_clk",
"cphy_rx_clk_src",
"csiphy3_clk",
"csi3phytimer_clk_src",
"csi3phytimer_clk";
clock-cntl-level = "turbo";
clock-rates =
<0 0 0 0 384000000 0 269333333 0>;
status = "ok";
};
qcom,cam_smmu {
compatible = "qcom,msm-cam-smmu";
status = "ok";
non-fatal-fault-disabled;
msm_cam_smmu_lrme {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x1038 0x0>,
<&apps_smmu 0x1058 0x0>;
label = "lrme";
lrme_iova_mem_map: iova-mem-map {
iova-mem-region-shared {
/* Shared region is 100MB long */
iova-region-name = "shared";
iova-region-start = <0x7400000>;
iova-region-len = <0x6400000>;
iova-region-id = <0x1>;
status = "ok";
};
/* IO region is approximately 3.3 GB */
iova-mem-region-io {
iova-region-name = "io";
iova-region-start = <0xd800000>;
iova-region-len = <0xd2800000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_ife {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x808 0x0>,
<&apps_smmu 0x810 0x8>,
<&apps_smmu 0xc08 0x0>,
<&apps_smmu 0xc10 0x8>;
label = "ife";
ife_iova_mem_map: iova-mem-map {
/* IO region is approximately 3.4 GB */
iova-mem-region-io {
iova-region-name = "io";
iova-region-start = <0x7400000>;
iova-region-len = <0xd8c00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_icp_fw {
compatible = "qcom,msm-cam-smmu-fw-dev";
label="icp";
memory-region = <&pil_camera_mem>;
};
msm_cam_smmu_icp {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x107A 0x2>,
<&apps_smmu 0x1020 0x8>,
<&apps_smmu 0x1040 0x8>,
<&apps_smmu 0x1030 0x0>,
<&apps_smmu 0x1050 0x0>;
label = "icp";
icp_iova_mem_map: iova-mem-map {
iova-mem-region-firmware {
/* Firmware region is 5MB */
iova-region-name = "firmware";
iova-region-start = <0x0>;
iova-region-len = <0x500000>;
iova-region-id = <0x0>;
status = "ok";
};
iova-mem-region-shared {
/* Shared region is 100MB long */
iova-region-name = "shared";
iova-region-start = <0x7400000>;
iova-region-len = <0x6400000>;
iova-region-id = <0x1>;
iova-granularity = <0x15>;
status = "ok";
};
iova-mem-region-secondary-heap {
/* Secondary heap region is 1MB long */
iova-region-name = "secheap";
iova-region-start = <0xd800000>;
iova-region-len = <0x100000>;
iova-region-id = <0x4>;
status = "ok";
};
iova-mem-region-io {
/* IO region is approximately 3 GB */
iova-region-name = "io";
iova-region-start = <0xd911000>;
iova-region-len = <0xd26ef000>;
iova-region-id = <0x3>;
status = "ok";
};
iova-mem-qdss-region {
/* qdss region is approximately 64K */
iova-region-name = "qdss";
iova-region-start = <0xd900000>;
iova-region-len = <0x10000>;
iova-region-id = <0x5>;
qdss-phy-addr = <0x16790000>;
status = "ok";
};
};
};
msm_cam_smmu_cpas_cdm {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x1000 0x0>;
label = "cpas-cdm0";
cpas_cdm_iova_mem_map: iova-mem-map {
iova-mem-region-io {
/* IO region is approximately 3.4 GB */
iova-region-name = "io";
iova-region-start = <0x7400000>;
iova-region-len = <0xd8c00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_secure {
compatible = "qcom,msm-cam-smmu-cb";
label = "cam-secure";
qcom,secure-cb;
};
};
qcom,cam-cpas@ac40000 {
cell-index = <0>;
compatible = "qcom,cam-cpas";
label = "cpas";
arch-compat = "cpas_top";
status = "ok";
reg-names = "cam_cpas_top", "cam_camnoc";
reg = <0xac40000 0x1000>,
<0xac42000 0x5000>;
reg-cam-base = <0x40000 0x42000>;
interrupt-names = "cpas_camnoc";
interrupts = <0 459 0>;
qcom,cpas-hw-ver = <0x170110>; /* Titan v170 v1.1.0 */
camnoc-axi-min-ib-bw = <3000000000>;
regulator-names = "camss-vdd";
camss-vdd-supply = <&titan_top_gdsc>;
clock-names = "gcc_ahb_clk",
"gcc_axi_clk",
"soc_ahb_clk",
"slow_ahb_clk_src",
"cpas_ahb_clk",
"camnoc_axi_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
<&clock_gcc GCC_CAMERA_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CAMNOC_AXI_CLK>;
src-clock-name = "slow_ahb_clk_src";
clock-rates = <0 0 0 0 0 0>,
<0 0 0 19200000 0 0>,
<0 0 0 80000000 0 0>,
<0 0 0 80000000 0 0>,
<0 0 0 80000000 0 0>,
<0 0 0 80000000 0 0>,
<0 0 0 80000000 0 0>;
clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
"svs_l1", "nominal", "turbo";
qcom,msm-bus,name = "cam_ahb";
qcom,msm-bus,num-cases = <7>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 76500>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 76500>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
<MSM_BUS_MASTER_AMPSS_M0
MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
vdd-corners = <RPMH_REGULATOR_LEVEL_OFF
RPMH_REGULATOR_LEVEL_RETENTION
RPMH_REGULATOR_LEVEL_MIN_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_SVS
RPMH_REGULATOR_LEVEL_SVS_L1
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_NOM_L1
RPMH_REGULATOR_LEVEL_NOM_L2
RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_TURBO_L1>;
vdd-corner-ahb-mapping = "suspend", "suspend",
"minsvs", "lowsvs", "svs", "svs_l1",
"nominal", "nominal", "nominal",
"turbo", "turbo";
client-id-based;
client-names =
"csiphy0", "csiphy1", "csiphy2", "csiphy3", "cci0",
"csid0", "csid1", "csid2",
"ife0", "ife1", "ife2", "ipe0",
"ipe1", "cam-cdm-intf0", "cpas-cdm0", "bps0",
"icp0", "jpeg-dma0", "jpeg-enc0", "fd0", "lrmecpas0";
client-axi-port-names =
"cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_hf_2",
"cam_sf_1", "cam_hf_1", "cam_hf_2", "cam_hf_2",
"cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1",
"cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1",
"cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1",
"cam_sf_1";
client-bus-camnoc-based;
qcom,axi-port-list {
qcom,axi-port1 {
qcom,axi-port-name = "cam_hf_1";
qcom,axi-port-mnoc {
qcom,msm-bus,name = "cam_hf_1_mnoc";
qcom,msm-bus-vector-dyn-vote;
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_CAMNOC_HF0
MSM_BUS_SLAVE_EBI_CH0 0 0>,
<MSM_BUS_MASTER_CAMNOC_HF0
MSM_BUS_SLAVE_EBI_CH0 0 0>;
};
qcom,axi-port-camnoc {
qcom,msm-bus,name = "cam_hf_1_camnoc";
qcom,msm-bus-vector-dyn-vote;
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
<MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
};
};
qcom,axi-port2 {
qcom,axi-port-name = "cam_hf_2";
qcom,axi-port-mnoc {
qcom,msm-bus,name = "cam_hf_2_mnoc";
qcom,msm-bus-vector-dyn-vote;
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_CAMNOC_HF1
MSM_BUS_SLAVE_EBI_CH0 0 0>,
<MSM_BUS_MASTER_CAMNOC_HF1
MSM_BUS_SLAVE_EBI_CH0 0 0>;
};
qcom,axi-port-camnoc {
qcom,msm-bus,name = "cam_hf_2_camnoc";
qcom,msm-bus-vector-dyn-vote;
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_CAMNOC_HF1_UNCOMP
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
<MSM_BUS_MASTER_CAMNOC_HF1_UNCOMP
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
};
};
qcom,axi-port3 {
qcom,axi-port-name = "cam_sf_1";
qcom,axi-port-mnoc {
qcom,msm-bus,name = "cam_sf_1_mnoc";
qcom,msm-bus-vector-dyn-vote;
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_CAMNOC_SF
MSM_BUS_SLAVE_EBI_CH0 0 0>,
<MSM_BUS_MASTER_CAMNOC_SF
MSM_BUS_SLAVE_EBI_CH0 0 0>;
};
qcom,axi-port-camnoc {
qcom,msm-bus,name = "cam_sf_1_camnoc";
qcom,msm-bus-vector-dyn-vote;
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_CAMNOC_SF_UNCOMP
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
<MSM_BUS_MASTER_CAMNOC_SF_UNCOMP
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
};
};
};
};
qcom,cam-lrme {
compatible = "qcom,cam-lrme";
arch-compat = "lrme";
status = "ok";
};
cam_lrme: qcom,lrme@ac6b000 {
cell-index = <0>;
compatible = "qcom,lrme";
reg-names = "lrme";
reg = <0xac6b000 0xa00>;
reg-cam-base = <0x6b000>;
interrupt-names = "lrme";
interrupts = <0 476 0>;
regulator-names = "camss";
camss-supply = <&titan_top_gdsc>;
clock-names = "camera_ahb",
"camera_axi",
"soc_ahb_clk",
"cpas_ahb_clk",
"camnoc_axi_clk",
"lrme_clk_src",
"lrme_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
<&clock_gcc GCC_CAMERA_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_LRME_CLK_SRC>,
<&clock_camcc CAM_CC_LRME_CLK>;
clock-rates = <0 0 0 0 0 200000000 200000000>,
<0 0 0 0 0 269000000 269000000>,
<0 0 0 0 0 320000000 320000000>,
<0 0 0 0 0 400000000 400000000>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
src-clock-name = "lrme_clk_src";
status = "ok";
};
};
|
