diff options
| author | Daniel Lezcano <daniel.lezcano@linaro.org> | 2017-10-30 19:05:56 +0100 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2017-10-30 19:05:56 +0100 |
| commit | 6f6238698283d767186abfbdba4a87a32c65a7da (patch) | |
| tree | ea50af16c5b1b1672d4ea7851082876091a7abcb | |
Initial import
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| -rw-r--r-- | 96boards.lib | 103 | ||||
| -rw-r--r-- | 96boards.pretty/Draft_DIP_Header_Socket_20x2.wrl | 6484 | ||||
| -rw-r--r-- | 96boards.pretty/Hole_2.5MM.kicad_mod | 9 | ||||
| -rw-r--r-- | 96boards.pretty/Pin_Header_SMD_2x20_Pitch2mm.kicad_mod | 61 | ||||
| -rw-r--r-- | 96boards.pretty/Pin_Header_Straight_2x20_Pitch2mm.kicad_mod | 67 | ||||
| -rw-r--r-- | 96boards.pretty/Socket_Strip_SMD_2x20_Pitch2mm.kicad_mod | 59 | ||||
| -rw-r--r-- | 96boards.pretty/Socket_Strip_Straight_2x20_Pitch2mm.kicad_mod | 67 | ||||
| -rw-r--r-- | COPYING | 23 | ||||
| -rw-r--r-- | fp-lib-table | 4 | ||||
| -rw-r--r-- | meta/brd.png | bin | 0 -> 43906 bytes | |||
| -rw-r--r-- | meta/icon.png | bin | 0 -> 15814 bytes | |||
| -rw-r--r-- | meta/info.html | 22 | ||||
| -rw-r--r-- | mezza-cache.lib | 281 | ||||
| -rw-r--r-- | mezza.bak | 969 | ||||
| -rw-r--r-- | mezza.kicad_pcb | 535 | ||||
| -rw-r--r-- | mezza.pro | 73 | ||||
| -rw-r--r-- | mezza.sch | 969 | ||||
| -rw-r--r-- | pmw-fan.bak | 48 | ||||
| -rw-r--r-- | pmw-fan.bck | 3 | ||||
| -rw-r--r-- | pmw-fan.dcm | 3 | ||||
| -rw-r--r-- | pmw-fan.lib | 48 | ||||
| -rw-r--r-- | pmw-fan.pretty/TC654.kicad_mod | 18 | ||||
| -rw-r--r-- | readme.md | 69 |
23 files changed, 9915 insertions, 0 deletions
diff --git a/96boards.lib b/96boards.lib new file mode 100644 index 0000000..e0169a1 --- /dev/null +++ b/96boards.lib @@ -0,0 +1,103 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 + +# +# CONN_02X20 +# +DEF CONN_02X20 P 0 1 Y N 1 F N +F0 "P" 0 1050 50 H V C CNN +F1 "CONN_02X20" 0 0 50 V V C CNN +F2 "" 0 -950 60 H V C CNN +F3 "" 0 -950 60 H V C CNN +$FPLIST + Pin_Header_Straight_2X20 + Pin_Header_Angled_2X20 + Socket_Strip_Straight_2X20 + Socket_Strip_Angled_2X20 +$ENDFPLIST +DRAW +S -100 -945 -50 -955 0 1 0 N +S -100 -845 -50 -855 0 1 0 N +S -100 -745 -50 -755 0 1 0 N +S -100 -645 -50 -655 0 1 0 N +S -100 -545 -50 -555 0 1 0 N +S -100 -445 -50 -455 0 1 0 N +S -100 -345 -50 -355 0 1 0 N +S -100 -245 -50 -255 0 1 0 N +S -100 -145 -50 -155 0 1 0 N +S -100 -45 -50 -55 0 1 0 N +S -100 55 -50 45 0 1 0 N +S -100 155 -50 145 0 1 0 N +S -100 255 -50 245 0 1 0 N +S -100 355 -50 345 0 1 0 N +S -100 455 -50 445 0 1 0 N +S -100 555 -50 545 0 1 0 N +S -100 655 -50 645 0 1 0 N +S -100 755 -50 745 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50 50 1 1 P +X P29 29 -250 -450 150 R 50 50 1 1 P +X P39 39 -250 -950 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/96boards.pretty/Draft_DIP_Header_Socket_20x2.wrl b/96boards.pretty/Draft_DIP_Header_Socket_20x2.wrl new file mode 100644 index 0000000..7c9fe29 --- /dev/null +++ b/96boards.pretty/Draft_DIP_Header_Socket_20x2.wrl @@ -0,0 +1,6484 @@ +#VRML V2.0 utf8 +#Exported from Wings 3D 1.5.4 +DEF STL_object Transform { + children [ + Shape { + appearance Appearance { + material DEF default Material { + diffuseColor 0.7898538076923077 0.8133333333333334 0.6940444444444445 + emissiveColor 0.0 0.0 0.0 + specularColor 0.0 0.0 0.0 + ambientIntensity 0.765743861823362 + transparency 0.0 + shininess 0.0 + } + } + geometry IndexedFaceSet { + normalPerVertex TRUE + colorPerVertex TRUE + coord Coordinate { point [ + -1.0 -0.75 0.0, + -1.0 -0.75 3.5, + -1.0 3.25 0.0, + -1.0 3.25 3.5, + -0.669549822807312 -0.669549822807312 3.5, + -0.669549822807312 1.169549822807312 3.5, + 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b/96boards.pretty/Hole_2.5MM.kicad_mod @@ -0,0 +1,9 @@ +(module Hole_2.5MM (layer F.Cu) (tedit 55C6917D) + (fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Hole_2.5MM (at 0 -0.5) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.5) (layers *.Cu *.Mask)) +) diff --git a/96boards.pretty/Pin_Header_SMD_2x20_Pitch2mm.kicad_mod b/96boards.pretty/Pin_Header_SMD_2x20_Pitch2mm.kicad_mod new file mode 100644 index 0000000..999e234 --- /dev/null +++ b/96boards.pretty/Pin_Header_SMD_2x20_Pitch2mm.kicad_mod @@ -0,0 +1,61 @@ +(module Pin_Header_SMD_2x20_Pitch2mm (layer F.Cu) (tedit 55F9A19C) + (descr "Double row SMD 2mm pin header, 2x20 contacts") + (attr smd) + (fp_text reference REF** (at -1 -2) (layer F.SilkS) + (effects (font (size 0.7 0.7) (thickness 0.15))) + ) + (fp_text value CONN_02X20 (at -1 -4) (layer F.Fab) + (effects (font (size 1.016 1.016) (thickness 0.2032))) + ) + (fp_line (start -4.95 -0.6) (end -4.95 38.7) (layer F.SilkS) (width 0.15)) + (fp_line (start -4.95 38.7) (end 2.95 38.7) (layer F.SilkS) (width 0.15)) + (fp_line (start -4.95 -0.6) (end 2.95 -0.6) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.95 -0.6) (end 2.95 38.7) (layer F.SilkS) (width 0.15)) + (pad "" np_thru_hole circle (at -1 37 270) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask F.SilkS)) + (pad 1 smd rect (at 1.25 0 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -3.25 -0.01 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad "" np_thru_hole circle (at -1 1 270) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask F.SilkS)) + (pad 4 smd rect (at -3.25 2 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at -3.25 4 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd rect (at -3.25 6 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd rect (at -3.25 8 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd rect (at -3.25 10 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd rect (at -3.25 12 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd rect (at -3.25 14 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd rect (at -3.25 16 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at -3.25 18 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd rect (at -3.25 20 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd rect (at -3.25 22 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd rect (at -3.25 24 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd rect (at -3.25 26 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at -3.25 28 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd rect (at -3.25 30 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd rect (at -3.25 32 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 36 smd rect (at -3.25 34 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 38 smd rect (at -3.25 36 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 40 smd rect (at -3.25 38 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at 1.25 2 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at 1.25 4 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at 1.25 6 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd rect (at 1.25 8 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd rect (at 1.25 10 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd rect (at 1.25 12 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd rect (at 1.25 14 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd rect (at 1.25 16 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at 1.25 18 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd rect (at 1.25 20 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 23 smd rect (at 1.25 22 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd rect (at 1.25 24 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd rect (at 1.25 26 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd rect (at 1.25 28 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd rect (at 1.25 30 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd rect (at 1.25 32 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 35 smd rect (at 1.25 34 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 37 smd rect (at 1.25 36 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (pad 39 smd rect (at 1.25 38 270) (size 0.89 3) (layers F.Cu F.Paste F.Mask)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_2x20.wrl + (at (xyz -0.0394 -0.749 0.015760)) + (scale (xyz 0.787 0.787 0.5)) + (rotate (xyz 0 0 90)) + ) +) diff --git a/96boards.pretty/Pin_Header_Straight_2x20_Pitch2mm.kicad_mod b/96boards.pretty/Pin_Header_Straight_2x20_Pitch2mm.kicad_mod new file mode 100644 index 0000000..5172214 --- /dev/null +++ b/96boards.pretty/Pin_Header_Straight_2x20_Pitch2mm.kicad_mod @@ -0,0 +1,67 @@ +(module Pin_Header_Straight_2x20_Pitch2mm (layer F.Cu) (tedit 56949A25) + (descr "Double row through-hole 2mm pin header, 2x20 contacts") + (tags CONN) + (fp_text reference REF** (at -1 -2) (layer F.SilkS) + (effects (font (size 0.7 0.7) (thickness 0.15))) + ) + (fp_text value CONN_02X20 (at -1 -4) (layer F.Fab) + (effects (font (size 1.016 1.016) (thickness 0.2032))) + ) + (fp_line (start 1.2 -1.2) (end 0 -1.2) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.2 -1.2) (end 1.2 0) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.5 -1.5) (end 1.5 39.5) (layer F.CrtYd) (width 0.15)) + (fp_line (start 1.5 39.5) (end -3.5 39.5) (layer F.CrtYd) (width 0.15)) + (fp_line (start -3.5 39.5) (end -3.5 -1.5) (layer F.CrtYd) (width 0.15)) + (fp_line (start -3.5 -1.5) (end 1.5 -1.5) (layer F.CrtYd) (width 0.15)) + (fp_line (start 1 1) (end -1 1) (layer F.SilkS) (width 0.15)) + (fp_line (start 1 1) (end 1 39) (layer F.SilkS) (width 0.15)) + (fp_line (start -3 39) (end 1 39) (layer F.SilkS) (width 0.15)) + (fp_line (start -3 39) (end -3 -1) (layer F.SilkS) (width 0.15)) + (fp_line (start -1 -1) (end -3 -1) (layer F.SilkS) (width 0.15)) + (fp_line (start -1 -1) (end -1 1) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 2 thru_hole circle (at -2 0 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 3 thru_hole circle (at 0 2 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 4 thru_hole circle (at -2 2 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 5 thru_hole circle (at 0 4 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 6 thru_hole circle (at -2 4 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 7 thru_hole circle (at 0 6 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 8 thru_hole circle (at -2 6 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 9 thru_hole circle (at 0 8 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 10 thru_hole circle (at -2 8 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 11 thru_hole circle (at 0 10 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 12 thru_hole circle (at -2 10 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 13 thru_hole circle (at 0 12 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 14 thru_hole circle (at -2 12 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 15 thru_hole circle (at 0 14 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 16 thru_hole circle (at -2 14 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 17 thru_hole circle (at 0 16 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 18 thru_hole circle (at -2 16 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 19 thru_hole circle (at 0 18 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 20 thru_hole circle (at -2 18 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 21 thru_hole circle (at 0 20 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 22 thru_hole circle (at -2 20 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 23 thru_hole circle (at 0 22 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 24 thru_hole circle (at -2 22 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 25 thru_hole circle (at 0 24 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 26 thru_hole circle (at -2 24 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 27 thru_hole circle (at 0 26 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 28 thru_hole circle (at -2 26 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 29 thru_hole circle (at 0 28 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 30 thru_hole circle (at -2 28 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 31 thru_hole circle (at 0 30 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 32 thru_hole circle (at -2 30 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 33 thru_hole circle (at 0 32 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 34 thru_hole circle (at -2 32 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 35 thru_hole circle (at 0 34 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 36 thru_hole circle (at -2 34 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 37 thru_hole circle (at 0 36 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 38 thru_hole circle (at -2 36 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 39 thru_hole circle (at 0 38 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 40 thru_hole circle (at -2 38 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_2x20.wrl + (at (xyz -0.0394 -0.749 0.01576)) + (scale (xyz 0.787 0.787 0.5)) + (rotate (xyz 0 0 90)) + ) +) diff --git a/96boards.pretty/Socket_Strip_SMD_2x20_Pitch2mm.kicad_mod b/96boards.pretty/Socket_Strip_SMD_2x20_Pitch2mm.kicad_mod new file mode 100644 index 0000000..a1bd31a --- /dev/null +++ b/96boards.pretty/Socket_Strip_SMD_2x20_Pitch2mm.kicad_mod @@ -0,0 +1,59 @@ +(module Socket_Strip_SMD_2x20_Pitch2mm (layer F.Cu) (tedit 55F865FA) + (descr "Double row SMD 2mm socket strip, 2x20 contacts") + (attr smd) + (fp_text reference REF** (at 1 -2) (layer F.SilkS) + (effects (font (size 0.7 0.7) (thickness 0.15))) + ) + (fp_text value CONN_02X20 (at 1 -4) (layer F.Fab) + (effects (font (size 1.016 1.016) (thickness 0.2032))) + ) + (fp_line (start -3 -0.75) (end -3 38.75) (layer F.SilkS) (width 0.15)) + (fp_line (start 5 38.75) (end 5 -0.75) (layer F.SilkS) (width 0.15)) + (fp_line (start 5 -0.75) (end -3 -0.75) (layer F.SilkS) (width 0.15)) + (fp_line (start 5 38.75) (end -3 38.75) (layer F.SilkS) (width 0.15)) + (pad 5 smd rect (at -1.65 4 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -1.65 2 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at 3.65 2 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 3.65 -0.01 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -1.65 -0.01 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at -1.65 6 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd rect (at -1.65 8 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd rect (at -1.65 10 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd rect (at -1.65 12 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd rect (at -1.65 14 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd rect (at -1.65 16 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at -1.65 18 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd rect (at -1.65 20 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 23 smd rect (at -1.65 22 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd rect (at -1.65 24 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd rect (at -1.65 26 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd rect (at -1.65 28 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd rect (at -1.65 30 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd rect (at -1.65 32 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 35 smd rect (at -1.65 34 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 37 smd rect (at -1.65 36 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 39 smd rect (at -1.65 38 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at 3.65 4 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd rect (at 3.65 6 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd rect (at 3.65 8 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd rect (at 3.65 10 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd rect (at 3.65 12 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd rect (at 3.65 14 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd rect (at 3.65 16 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at 3.65 18 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd rect (at 3.65 20 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd rect (at 3.65 22 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd rect (at 3.65 24 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd rect (at 3.65 26 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at 3.65 28 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd rect (at 3.65 30 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd rect (at 3.65 32 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 36 smd rect (at 3.65 34 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 38 smd rect (at 3.65 36 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (pad 40 smd rect (at 3.65 38 270) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask)) + (model Socket_Strips.3dshapes/Socket_Strip_Straight_2x20.wrl + (at (xyz 0.0394 -0.749 0.015760)) + (scale (xyz 0.787 0.787 0.5)) + (rotate (xyz 0 0 90)) + ) +) diff --git a/96boards.pretty/Socket_Strip_Straight_2x20_Pitch2mm.kicad_mod b/96boards.pretty/Socket_Strip_Straight_2x20_Pitch2mm.kicad_mod new file mode 100644 index 0000000..c9268b2 --- /dev/null +++ b/96boards.pretty/Socket_Strip_Straight_2x20_Pitch2mm.kicad_mod @@ -0,0 +1,67 @@ +(module Socket_Strip_Straight_2x20_Pitch2mm (layer F.Cu) (tedit 56949A3C) + (descr "Double row through-hole 2mm socket strip, 2x20 contacts") + (tags CONN) + (fp_text reference REF** (at 1 -2) (layer F.SilkS) + (effects (font (size 0.7 0.7) (thickness 0.15))) + ) + (fp_text value CONN_02X20 (at 1 -4) (layer F.Fab) + (effects (font (size 1.016 1.016) (thickness 0.2032))) + ) + (fp_line (start 0 -1.2) (end -1.2 -1.2) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.2 -1.2) (end -1.2 0) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.5 -1.5) (end 3.5 39.5) (layer F.CrtYd) (width 0.15)) + (fp_line (start 3.5 39.5) (end -1.5 39.5) (layer F.CrtYd) (width 0.15)) + (fp_line (start -1.5 39.5) (end -1.5 -1.5) (layer F.CrtYd) (width 0.15)) + (fp_line (start -1.5 -1.5) (end 3.5 -1.5) (layer F.CrtYd) (width 0.15)) + (fp_line (start 1 1) (end -1 1) (layer F.SilkS) (width 0.15)) + (fp_line (start -1 1) (end -1 39) (layer F.SilkS) (width 0.15)) + (fp_line (start -1 39) (end 3 39) (layer F.SilkS) (width 0.15)) + (fp_line (start 3 39) (end 3 -1) (layer F.SilkS) (width 0.15)) + (fp_line (start 3 -1) (end 1 -1) (layer F.SilkS) (width 0.15)) + (fp_line (start 1 -1) (end 1 1) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 2 thru_hole circle (at 2 0 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 3 thru_hole circle (at 0 2 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 4 thru_hole circle (at 2 2 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 5 thru_hole circle (at 0 4 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 6 thru_hole circle (at 2 4 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 7 thru_hole circle (at 0 6 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 8 thru_hole circle (at 2 6 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 9 thru_hole circle (at 0 8 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 10 thru_hole circle (at 2 8 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 11 thru_hole circle (at 0 10 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 12 thru_hole circle (at 2 10 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 13 thru_hole circle (at 0 12 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 14 thru_hole circle (at 2 12 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 15 thru_hole circle (at 0 14 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 16 thru_hole circle (at 2 14 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 17 thru_hole circle (at 0 16 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 18 thru_hole circle (at 2 16 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 19 thru_hole circle (at 0 18 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 20 thru_hole circle (at 2 18 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 21 thru_hole circle (at 0 20 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 22 thru_hole circle (at 2 20 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 23 thru_hole circle (at 0 22 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 24 thru_hole circle (at 2 22 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 25 thru_hole circle (at 0 24 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 26 thru_hole circle (at 2 24 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 27 thru_hole circle (at 0 26 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 28 thru_hole circle (at 2 26 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 29 thru_hole circle (at 0 28 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 30 thru_hole circle (at 2 28 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 31 thru_hole circle (at 0 30 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 32 thru_hole circle (at 2 30 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 33 thru_hole circle (at 0 32 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 34 thru_hole circle (at 2 32 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 35 thru_hole circle (at 0 34 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 36 thru_hole circle (at 2 34 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 37 thru_hole circle (at 0 36 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 38 thru_hole circle (at 2 36 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 39 thru_hole circle (at 0 38 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (pad 40 thru_hole circle (at 2 38 270) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)) + (model Socket_Strips.3dshapes/Socket_Strip_Straight_2x20.wrl + (at (xyz 0.0394 -0.749 0.01576)) + (scale (xyz 0.787 0.787 0.5)) + (rotate (xyz 0 0 90)) + ) +) @@ -0,0 +1,23 @@ +Copyright (c) 2015, Linaro, Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\ No newline at end of file diff --git a/fp-lib-table b/fp-lib-table new file mode 100644 index 0000000..8dfa8af --- /dev/null +++ b/fp-lib-table @@ -0,0 +1,4 @@ +(fp_lib_table + (lib (name 96boards)(type KiCad)(uri "$(KIPRJMOD)/96boards.pretty")(options "")(descr "")) + (lib (name pwm-fan)(type KiCad)(uri "$(KIPRJMOD)/pmw-fan.pretty")(options "")(descr "")) +) diff --git a/meta/brd.png b/meta/brd.png Binary files differnew file mode 100644 index 0000000..7e640d6 --- /dev/null +++ b/meta/brd.png diff --git a/meta/icon.png b/meta/icon.png Binary files differnew file mode 100644 index 0000000..33720c9 --- /dev/null +++ b/meta/icon.png diff --git a/meta/info.html b/meta/info.html new file mode 100644 index 0000000..4d8117b --- /dev/null +++ b/meta/info.html @@ -0,0 +1,22 @@ +<!DOCTYPE HTML> +<HTML> +<HEAD> +<META content="text/html"> +<TITLE>Mezzanine Boards Template</TITLE> +<h1>96Boards</h1> +<h2>Mezzanine Board Template</h2> + +<p>This is a project template for developing a 96Boards Mezzanine board <a href="https://www.96boards.org/products/ce/">(compatible with these boards)</a>. </p> + +<p>This project's <em>schematic</em> only contains the necessary connectors needed for a mezzanine board. The current connectors are <em>surface mounted</em>, which can be easily changed to <em>through hole</em>. This is noted in the schematic.</p> + +<p>The <em>PCB</em> includes the connectors, and mounting holes. The <em>connectors and holes</em> have been positioned so that the boards are aligned when mounted. The <em>edge cuts</em> also aligns with the base board. All the mezzanine board <em>IO</em> is connected to the header pins.</p> + +<p>The board outline looks like the following:</p> +<p><img src="brd.png"></p> +<br> +<br> +<br> +<p>Copyright (c) 2016, Linaro, Inc.</p> +</BODY> +</HTML>
\ No newline at end of file diff --git a/mezza-cache.lib b/mezza-cache.lib new file mode 100644 index 0000000..b0fef71 --- /dev/null +++ b/mezza-cache.lib @@ -0,0 +1,281 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# +1V8 +# +DEF +1V8 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "+1V8" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +1V8 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# +5V +# +DEF +5V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "+5V" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +5V 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# BS170 +# +DEF BS170 Q 0 0 Y Y 1 F N +F0 "Q" 200 75 50 H V L CNN +F1 "BS170" 200 0 50 H V L CNN +F2 "TO-92" 200 -75 50 H V L CIN +F3 "" 0 0 50 H V L CNN +$FPLIST + TO-92* +$ENDFPLIST +DRAW +C 50 0 111 0 1 10 N +C 100 -50 5 0 1 0 N +C 100 50 5 0 1 0 N +P 2 0 1 20 25 -40 25 -65 N +P 2 0 1 20 25 15 25 -15 N +P 2 0 1 20 25 65 25 40 N +P 2 0 1 0 120 15 115 10 N +P 2 0 1 0 120 15 140 15 N +P 2 0 1 0 140 15 145 20 N +P 3 0 1 10 0 60 0 -60 0 -60 N +P 4 0 1 0 30 -50 100 -50 100 -100 100 -100 N +P 4 0 1 0 30 50 100 50 100 100 100 100 N +P 4 0 1 0 100 50 130 50 130 -50 100 -50 N +P 4 0 1 0 130 15 120 -10 140 -10 130 15 F +P 5 0 1 0 30 0 50 0 100 0 100 -50 100 -50 N +P 6 0 1 0 35 0 75 15 75 -15 35 0 40 0 40 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 -50 200 R 50 50 1 1 I +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# CONN_02X20 +# +DEF CONN_02X20 P 0 1 Y N 1 F N +F0 "P" 0 1050 50 H V C CNN +F1 "CONN_02X20" 0 0 50 V V C CNN +F2 "" 0 -950 50 H V C CNN +F3 "" 0 -950 50 H V C CNN +$FPLIST + Pin_Header_Straight_2X20 + Pin_Header_Angled_2X20 + Socket_Strip_Straight_2X20 + Socket_Strip_Angled_2X20 +$ENDFPLIST +DRAW +S -100 -945 -50 -955 0 1 0 N +S -100 -845 -50 -855 0 1 0 N +S -100 -745 -50 -755 0 1 0 N +S -100 -645 -50 -655 0 1 0 N +S -100 -545 -50 -555 0 1 0 N +S -100 -445 -50 -455 0 1 0 N +S -100 -345 -50 -355 0 1 0 N +S -100 -245 -50 -255 0 1 0 N +S -100 -145 -50 -155 0 1 0 N +S -100 -45 -50 -55 0 1 0 N +S -100 55 -50 45 0 1 0 N +S -100 155 -50 145 0 1 0 N +S -100 255 -50 245 0 1 0 N +S -100 355 -50 345 0 1 0 N +S -100 455 -50 445 0 1 0 N +S -100 555 -50 545 0 1 0 N +S -100 655 -50 645 0 1 0 N +S -100 755 -50 745 0 1 0 N +S -100 855 -50 845 0 1 0 N +S -100 955 -50 945 0 1 0 N +S -100 1000 100 -1000 0 1 0 N +S 50 -945 100 -955 0 1 0 N +S 50 -845 100 -855 0 1 0 N +S 50 -745 100 -755 0 1 0 N +S 50 -645 100 -655 0 1 0 N +S 50 -545 100 -555 0 1 0 N +S 50 -445 100 -455 0 1 0 N +S 50 -345 100 -355 0 1 0 N +S 50 -245 100 -255 0 1 0 N +S 50 -145 100 -155 0 1 0 N +S 50 -45 100 -55 0 1 0 N +S 50 55 100 45 0 1 0 N +S 50 155 100 145 0 1 0 N +S 50 255 100 245 0 1 0 N +S 50 355 100 345 0 1 0 N +S 50 455 100 445 0 1 0 N +S 50 555 100 545 0 1 0 N +S 50 655 100 645 0 1 0 N +S 50 755 100 745 0 1 0 N +S 50 855 100 845 0 1 0 N +S 50 955 100 945 0 1 0 N +X P1 1 -250 950 150 R 50 50 1 1 P +X P2 2 250 950 150 L 50 50 1 1 P +X P3 3 -250 850 150 R 50 50 1 1 P +X P4 4 250 850 150 L 50 50 1 1 P +X P5 5 -250 750 150 R 50 50 1 1 P +X P6 6 250 750 150 L 50 50 1 1 P +X P7 7 -250 650 150 R 50 50 1 1 P +X P8 8 250 650 150 L 50 50 1 1 P +X P9 9 -250 550 150 R 50 50 1 1 P +X P10 10 250 550 150 L 50 50 1 1 P +X P20 20 250 50 150 L 50 50 1 1 P +X P30 30 250 -450 150 L 50 50 1 1 P +X P40 40 250 -950 150 L 50 50 1 1 P +X P11 11 -250 450 150 R 50 50 1 1 P +X P21 21 -250 -50 150 R 50 50 1 1 P +X P31 31 -250 -550 150 R 50 50 1 1 P +X P12 12 250 450 150 L 50 50 1 1 P +X P22 22 250 -50 150 L 50 50 1 1 P +X P32 32 250 -550 150 L 50 50 1 1 P +X P13 13 -250 350 150 R 50 50 1 1 P +X P23 23 -250 -150 150 R 50 50 1 1 P +X P33 33 -250 -650 150 R 50 50 1 1 P +X P14 14 250 350 150 L 50 50 1 1 P +X P24 24 250 -150 150 L 50 50 1 1 P +X P34 34 250 -650 150 L 50 50 1 1 P +X P15 15 -250 250 150 R 50 50 1 1 P +X P25 25 -250 -250 150 R 50 50 1 1 P +X P35 35 -250 -750 150 R 50 50 1 1 P +X P16 16 250 250 150 L 50 50 1 1 P +X P26 26 250 -250 150 L 50 50 1 1 P +X P36 36 250 -750 150 L 50 50 1 1 P +X P17 17 -250 150 150 R 50 50 1 1 P +X P27 27 -250 -350 150 R 50 50 1 1 P +X P37 37 -250 -850 150 R 50 50 1 1 P +X P18 18 250 150 150 L 50 50 1 1 P +X P28 28 250 -350 150 L 50 50 1 1 P +X P38 38 250 -850 150 L 50 50 1 1 P +X P19 19 -250 50 150 R 50 50 1 1 P +X P29 29 -250 -450 150 R 50 50 1 1 P +X P39 39 -250 -950 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# C_Small +# +DEF C_Small C 0 10 N N 1 F N +F0 "C" 10 70 50 H V L CNN +F1 "C_Small" 10 -80 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 13 -60 -20 60 -20 N +P 2 0 1 12 -60 20 60 20 N +X ~ 1 0 100 80 D 50 50 1 1 P +X ~ 2 0 -100 80 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Fan +# +DEF Fan M 0 0 Y Y 1 F N +F0 "M" 100 200 50 H V L CNN +F1 "Fan" 100 -100 50 H V L TNN +F2 "" 0 10 50 H I C CNN +F3 "" 0 10 50 H I C CNN +$FPLIST + Pin_Headers:Pin_Header_Straight_1x02 + Connect:bornier2 + TerminalBlock*2pol +$ENDFPLIST +DRAW +A -98 94 113 297 -910 0 1 0 N 0 150 -100 -20 +A 0 -70 112 1534 266 0 1 0 N -100 -20 100 -20 +A 103 95 115 -915 1519 0 1 0 N 100 -20 0 150 +C 0 40 128 0 1 10 N +P 2 0 1 0 0 -200 0 -180 N +P 2 0 1 0 0 -88 0 -104 N +P 2 0 1 0 0 168 0 182 N +P 2 0 1 0 0 180 0 200 N +X + 1 0 300 100 D 50 50 1 1 P +X - 2 0 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# R_Small +# +DEF R_Small R 0 10 N N 1 F N +F0 "R" 30 20 50 H V L CNN +F1 "R_Small" 30 -40 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -30 70 30 -70 0 1 8 N +X ~ 1 0 100 30 D 50 50 1 1 P +X ~ 2 0 -100 30 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# TC654/TC655 +# +DEF TC654/TC655 U 0 40 Y Y 1 F N +F0 "U" 300 600 60 H V C CNN +F1 "TC654/TC655" 0 0 60 H V C CNB +F2 "" -300 50 60 H I C CNN +F3 "" -300 50 60 H I C CNN +DRAW +S -800 1000 800 -1000 0 1 0 f +X Vin 1 -1000 800 200 R 50 50 1 1 I +X CF 2 -1000 400 200 R 50 50 1 1 O +X SCLK 3 -1000 -400 200 R 50 50 1 1 I +X SDA 4 -1000 -800 200 R 50 50 1 1 B +X GND 5 0 -1200 200 U 50 50 1 1 I +X /FAULT 6 1000 -800 200 L 50 50 1 1 O +X SENSE2 7 1000 -400 200 L 50 50 1 1 I +X SENSE1 8 1000 400 200 L 50 50 1 1 I +X Vout 9 1000 800 200 L 50 50 1 1 O +X Vdd 10 0 1200 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# Thermistor +# +DEF Thermistor TH 0 0 N Y 1 F N +F0 "TH" 100 50 50 V V C CNN +F1 "Thermistor" -100 0 50 V V C BNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* + SM0603 + SM0805 +$ENDFPLIST +DRAW +S -40 100 40 -100 0 1 8 N +P 5 0 1 10 -75 125 -75 75 75 -75 75 -125 75 -125 N +X ~ 1 0 200 100 D 50 50 1 1 P +X ~ 2 0 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/mezza.bak b/mezza.bak new file mode 100644 index 0000000..17fcfdb --- /dev/null +++ b/mezza.bak @@ -0,0 +1,969 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:96boards +LIBS:pmw-fan +LIBS:Motor +LIBS:mezza-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "96Boards Mezzanine Project Template" +Date "14 Aug 2015" +Rev "A" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text GLabel 3950 1500 0 60 Output ~ 0 +UART0_RTS +$Comp +L GND #PWR01 +U 1 1 55D481C7 +P 3950 950 +F 0 "#PWR01" H 3950 700 50 0001 C CNN +F 1 "GND" H 3950 800 50 0000 C CNN +F 2 "" H 3950 950 60 0000 C CNN +F 3 "" H 3950 950 60 0000 C CNN + 1 3950 950 + 1 0 0 -1 +$EndComp +Text GLabel 3950 1300 0 60 Output ~ 0 +UART0_TX +$Comp +L GND #PWR02 +U 1 1 55D481CF +P 4000 3000 +F 0 "#PWR02" H 4000 2750 50 0001 C CNN +F 1 "GND" H 4000 2850 50 0000 C CNN +F 2 "" H 4000 3000 60 0000 C CNN +F 3 "" H 4000 3000 60 0000 C CNN + 1 4000 3000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 55D481D5 +P 4700 3000 +F 0 "#PWR03" H 4700 2750 50 0001 C CNN +F 1 "GND" H 4700 2850 50 0000 C CNN +F 2 "" H 4700 3000 60 0000 C CNN +F 3 "" H 4700 3000 60 0000 C CNN + 1 4700 3000 + 1 0 0 -1 +$EndComp +Text GLabel 3950 1200 0 60 Input ~ 0 +UART0_CTS +Text GLabel 4700 2900 2 60 Input ~ 0 +SYS_DCIN +$Comp +L GND #PWR04 +U 1 1 55D48218 +P 4750 950 +F 0 "#PWR04" H 4750 700 50 0001 C CNN +F 1 "GND" H 4750 800 50 0000 C CNN +F 2 "" H 4750 950 60 0000 C CNN +F 3 "" H 4750 950 60 0000 C CNN + 1 4750 950 + 1 0 0 -1 +$EndComp +$Comp +L CONN_02X20 P2 +U 1 1 55D48226 +P 4350 2050 +F 0 "P2" H 4350 3100 50 0000 C CNN +F 1 "CONN_02X20" V 4350 2050 50 0000 C CNN +F 2 "96boards:Socket_Strip_SMD_2x20_Pitch2mm" H 4350 1100 60 0001 C CNN +F 3 "" H 4350 1100 60 0000 C CNN +F 4 "Yxcon" H 4350 2050 60 0001 C CNN "Mfr" +F 5 "F240-1220A0xMUx1" H 4350 2050 60 0001 C CNN "Mfr Part #" + 1 4350 2050 + 1 0 0 -1 +$EndComp +$Comp +L +1V8 #PWR05 +U 1 1 55D4822C +P 3450 2750 +F 0 "#PWR05" H 3450 2600 50 0001 C CNN +F 1 "+1V8" H 3450 2890 50 0000 C CNN +F 2 "" H 3450 2750 60 0000 C CNN +F 3 "" H 3450 2750 60 0000 C CNN + 1 3450 2750 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR06 +U 1 1 55D48233 +P 3250 2750 +F 0 "#PWR06" H 3250 2600 50 0001 C CNN +F 1 "+5V" H 3250 2890 50 0000 C CNN +F 2 "" H 3250 2750 60 0000 C CNN +F 3 "" H 3250 2750 60 0000 C CNN + 1 3250 2750 + 1 0 0 -1 +$EndComp +Text GLabel 4700 1300 2 60 Input ~ 0 +RST_BTN_N +Text GLabel 3950 2100 0 60 BiDi ~ 0 +I2C1_SDA +Text GLabel 3950 2000 0 60 BiDi ~ 0 +I2C1_SCL +Text GLabel 3950 1900 0 60 BiDi ~ 0 +I2C0_SDA +Text GLabel 3950 1800 0 60 BiDi ~ 0 +I2C0_SCL +Text GLabel 3950 2200 0 60 Input ~ 0 +GPIO_A +Text GLabel 3950 1400 0 60 Input ~ 0 +UART0_RX +Text Notes 875 5350 0 60 ~ 0 +96Boards Low-Speed Expansion Connectors\n\nBy default, this is set up for a stackable surface-mount\narrangement. Do the following to switch to a through-hole\nconnector:\n\nOption 1) For a surface-mount non-stackable connector\n- Delete P2\n\nOption 2) For a through-hole non-stackable pin header\n- Delete P2\n- Change P1 footprint to "Pin_Header_Straight_2x20_Pitch2mm"\n\nOption 3) For a through-hole stackable socket strip connector\n- Delete P1\n- Change P2 footprint to "Socket_Strip_Straight_2x20_Pitch2mm"\n\nOption 2 and 3 are electrically equivalent. They differ on which side\nof the board to place the silkscreen labels.\n\nDelete this note once you have chosen the connector style. +Text GLabel 4700 1200 2 60 Input ~ 0 +PWR_BTN_N +Text GLabel 3950 1600 0 60 Input ~ 0 +UART1_TX +Text GLabel 3950 2300 0 60 Input ~ 0 +GPIO_C +Text GLabel 3950 2400 0 60 Input ~ 0 +GPIO_E +Text GLabel 3950 2500 0 60 Input ~ 0 +GPIO_G +Text GLabel 3950 2600 0 60 Input ~ 0 +GPIO_I +Text GLabel 3950 2700 0 60 Input ~ 0 +GPIO_K +Text GLabel 3950 1700 0 60 Input ~ 0 +UART1_RX +Text GLabel 4700 2200 2 60 Input ~ 0 +GPIO_B +Text GLabel 4700 1400 2 60 Input ~ 0 +SPIO_SCL +Text GLabel 4700 1500 2 60 Input ~ 0 +SPIO_DIN +Text GLabel 4700 1600 2 60 Input ~ 0 +SPIO_CS +Text GLabel 4700 1700 2 60 Input ~ 0 +SPIO_DOUT +Text GLabel 4700 1800 2 60 Input ~ 0 +PCM_FS +Text GLabel 4700 1900 2 60 Input ~ 0 +PCM_CLK +Text GLabel 4700 2000 2 60 Input ~ 0 +PCM_DO +Text GLabel 4700 2100 2 60 Input ~ 0 +PCM_DI +Text GLabel 4700 2300 2 60 Input ~ 0 +GPIO_D +Text GLabel 4700 2400 2 60 Input ~ 0 +GPIO_F +Text GLabel 4700 2500 2 60 Input ~ 0 +GPIO_H +Text GLabel 4700 2600 2 60 Input ~ 0 +GPIO_J +Text GLabel 4700 2700 2 60 Input ~ 0 +GPIO_L +Wire Wire Line + 4600 1200 4700 1200 +Wire Wire Line + 4600 900 4750 900 +Wire Wire Line + 4750 900 4750 950 +Wire Wire Line + 3250 2750 3250 2900 +Wire Wire Line + 3450 2750 3450 2800 +Wire Wire Line + 3950 2400 4100 2400 +Wire Wire Line + 3950 2500 4100 2500 +Wire Wire Line + 3950 2600 4100 2600 +Wire Wire Line + 3950 2700 4100 2700 +Wire Wire Line + 3450 2800 4100 2800 +Wire Wire Line + 4100 900 4100 1100 +Wire Wire Line + 3950 900 4100 900 +Wire Wire Line + 4600 900 4600 1100 +Wire Wire Line + 4600 1300 4700 1300 +Wire Wire Line + 4600 1400 4700 1400 +Wire Wire Line + 4600 1500 4700 1500 +Wire Wire Line + 4600 1600 4700 1600 +Wire Wire Line + 4600 1700 4700 1700 +Wire Wire Line + 4600 1800 4700 1800 +Wire Wire Line + 4600 1900 4700 1900 +Wire Wire Line + 4600 2000 4700 2000 +Wire Wire Line + 4600 2100 4700 2100 +Wire Wire Line + 4600 2200 4700 2200 +Wire Wire Line + 4600 2300 4700 2300 +Wire Wire Line + 4600 2400 4700 2400 +Wire Wire Line + 4600 2500 4700 2500 +Wire Wire Line + 4600 2600 4700 2600 +Wire Wire Line + 4600 2700 4700 2700 +Connection ~ 4650 2900 +Wire Wire Line + 4650 2800 4650 2900 +Wire Wire Line + 4600 2800 4650 2800 +Wire Wire Line + 4600 2900 4700 2900 +Wire Wire Line + 3950 900 3950 950 +Wire Wire Line + 3950 1200 4100 1200 +Wire Wire Line + 3950 2300 4100 2300 +Wire Wire Line + 3950 2200 4100 2200 +Wire Wire Line + 4100 3000 4000 3000 +Wire Wire Line + 4600 3000 4700 3000 +Wire Wire Line + 3250 2900 4100 2900 +Wire Wire Line + 3950 1300 4100 1300 +Wire Wire Line + 3950 1400 4100 1400 +Wire Wire Line + 3950 1800 4100 1800 +Wire Wire Line + 3950 1900 4100 1900 +Wire Wire Line + 3950 2000 4100 2000 +Wire Wire Line + 3950 2100 4100 2100 +Wire Wire Line + 3950 1600 4100 1600 +Wire Wire Line + 3950 1700 4100 1700 +Wire Wire Line + 4100 1500 3950 1500 +$Comp +L GND #PWR07 +U 1 1 55BEAA68 +P 1500 950 +F 0 "#PWR07" H 1500 700 50 0001 C CNN +F 1 "GND" H 1500 800 50 0000 C CNN +F 2 "" H 1500 950 60 0000 C CNN +F 3 "" H 1500 950 60 0000 C CNN + 1 1500 950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR08 +U 1 1 55BEA10A +P 1550 3000 +F 0 "#PWR08" H 1550 2750 50 0001 C CNN +F 1 "GND" H 1550 2850 50 0000 C CNN +F 2 "" H 1550 3000 60 0000 C CNN +F 3 "" H 1550 3000 60 0000 C CNN + 1 1550 3000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR09 +U 1 1 55BEA0BC +P 2250 3000 +F 0 "#PWR09" H 2250 2750 50 0001 C CNN +F 1 "GND" H 2250 2850 50 0000 C CNN +F 2 "" H 2250 3000 60 0000 C CNN +F 3 "" H 2250 3000 60 0000 C CNN + 1 2250 3000 + 1 0 0 -1 +$EndComp +Text GLabel 2250 2900 2 60 Input ~ 0 +SYS_DCIN +$Comp +L GND #PWR010 +U 1 1 55D43BD4 +P 2300 950 +F 0 "#PWR010" H 2300 700 50 0001 C CNN +F 1 "GND" H 2300 800 50 0000 C CNN +F 2 "" H 2300 950 60 0000 C CNN +F 3 "" H 2300 950 60 0000 C CNN + 1 2300 950 + 1 0 0 -1 +$EndComp +$Comp +L CONN_02X20 P1 +U 1 1 55D44709 +P 1900 2050 +F 0 "P1" H 1900 3100 50 0000 C CNN +F 1 "CONN_02X20" V 1900 2050 50 0000 C CNN +F 2 "96boards:Pin_Header_SMD_2x20_Pitch2mm" H 1900 1100 60 0001 C CNN +F 3 "" H 1900 1100 60 0000 C CNN +F 4 "Yxcon" H 1900 2050 60 0001 C CNN "Mfr" +F 5 "P220-1220A0xMxxxx2" H 1900 2050 60 0001 C CNN "Mfr Part #" + 1 1900 2050 + 1 0 0 -1 +$EndComp +$Comp +L +1V8 #PWR011 +U 1 1 55D43CFB +P 1000 2750 +F 0 "#PWR011" H 1000 2600 50 0001 C CNN +F 1 "+1V8" H 1000 2890 50 0000 C CNN +F 2 "" H 1000 2750 60 0000 C CNN +F 3 "" H 1000 2750 60 0000 C CNN + 1 1000 2750 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR012 +U 1 1 55D440FD +P 800 2750 +F 0 "#PWR012" H 800 2600 50 0001 C CNN +F 1 "+5V" H 800 2890 50 0000 C CNN +F 2 "" H 800 2750 60 0000 C CNN +F 3 "" H 800 2750 60 0000 C CNN + 1 800 2750 + 1 0 0 -1 +$EndComp +Text GLabel 1500 2100 0 60 BiDi ~ 0 +I2C1_SDA +Text GLabel 1500 2000 0 60 BiDi ~ 0 +I2C1_SCL +Text GLabel 1500 1900 0 60 BiDi ~ 0 +I2C0_SDA +Text GLabel 1500 1800 0 60 BiDi ~ 0 +I2C0_SCL +Text GLabel 2250 1200 2 60 Input ~ 0 +PWR_BTN_N +Text GLabel 2250 1300 2 60 Input ~ 0 +RST_BTN_N +Text GLabel 1500 1500 0 60 Output ~ 0 +UART0_RTS +Text GLabel 1500 1400 0 60 Input ~ 0 +UART0_RX +Text GLabel 1500 1300 0 60 Output ~ 0 +UART0_TX +Text GLabel 1500 1200 0 60 Input ~ 0 +UART0_CTS +Text GLabel 1500 2200 0 60 Input ~ 0 +GPIO_A +Text GLabel 2250 2200 2 60 Input ~ 0 +GPIO_B +Text GLabel 1500 1600 0 60 Input ~ 0 +UART1_TX +Text GLabel 1500 1700 0 60 Input ~ 0 +UART1_RX +Text GLabel 1500 2300 0 60 Input ~ 0 +GPIO_C +Text GLabel 1500 2400 0 60 Input ~ 0 +GPIO_E +Text GLabel 1500 2500 0 60 Input ~ 0 +GPIO_G +Text GLabel 1500 2600 0 60 Input ~ 0 +GPIO_I +Text GLabel 1500 2700 0 60 Input ~ 0 +GPIO_K +Text GLabel 2250 1400 2 60 Input ~ 0 +SPIO_SCL +Text GLabel 2250 1500 2 60 Input ~ 0 +SPIO_DIN +Text GLabel 2250 1600 2 60 Input ~ 0 +SPIO_CS +Text GLabel 2250 1700 2 60 Input ~ 0 +SPIO_DOUT +Text GLabel 2250 1800 2 60 Input ~ 0 +PCM_FS +Text GLabel 2250 1900 2 60 Input ~ 0 +PCM_CLK +Text GLabel 2250 2000 2 60 Input ~ 0 +PCM_DO +Text GLabel 2250 2100 2 60 Input ~ 0 +PCM_DI +Text GLabel 2250 2300 2 60 Input ~ 0 +GPIO_D +Text GLabel 2250 2400 2 60 Input ~ 0 +GPIO_F +Text GLabel 2250 2500 2 60 Input ~ 0 +GPIO_H +Text GLabel 2250 2600 2 60 Input ~ 0 +GPIO_J +Text GLabel 2250 2700 2 60 Input ~ 0 +GPIO_L +Wire Wire Line + 2150 900 2300 900 +Wire Wire Line + 2300 900 2300 950 +Wire Wire Line + 800 2750 800 2900 +Wire Wire Line + 1000 2750 1000 2800 +Wire Wire Line + 1500 2400 1650 2400 +Wire Wire Line + 1500 2500 1650 2500 +Wire Wire Line + 1500 2600 1650 2600 +Wire Wire Line + 1500 2700 1650 2700 +Wire Wire Line + 1000 2800 1650 2800 +Wire Wire Line + 1650 900 1650 1100 +Wire Wire Line + 1500 900 1650 900 +Wire Wire Line + 2150 900 2150 1100 +Wire Wire Line + 2150 1200 2250 1200 +Wire Wire Line + 2150 1300 2250 1300 +Wire Wire Line + 2150 1400 2250 1400 +Wire Wire Line + 2150 1500 2250 1500 +Wire Wire Line + 2150 1600 2250 1600 +Wire Wire Line + 2150 1700 2250 1700 +Wire Wire Line + 2150 1800 2250 1800 +Wire Wire Line + 2150 1900 2250 1900 +Wire Wire Line + 2150 2000 2250 2000 +Wire Wire Line + 2150 2100 2250 2100 +Wire Wire Line + 2150 2200 2250 2200 +Wire Wire Line + 2150 2300 2250 2300 +Wire Wire Line + 2150 2400 2250 2400 +Wire Wire Line + 2150 2500 2250 2500 +Wire Wire Line + 2150 2600 2250 2600 +Wire Wire Line + 2150 2700 2250 2700 +Connection ~ 2200 2900 +Wire Wire Line + 2200 2800 2200 2900 +Wire Wire Line + 2150 2800 2200 2800 +Wire Wire Line + 2150 2900 2250 2900 +Wire Wire Line + 1500 900 1500 950 +Wire Wire Line + 1500 1200 1650 1200 +Wire Wire Line + 1500 2300 1650 2300 +Wire Wire Line + 1500 2200 1650 2200 +Wire Wire Line + 1650 3000 1550 3000 +Wire Wire Line + 2150 3000 2250 3000 +Wire Wire Line + 800 2900 1650 2900 +Wire Wire Line + 1500 1300 1650 1300 +Wire Wire Line + 1500 1400 1650 1400 +Wire Wire Line + 1500 1800 1650 1800 +Wire Wire Line + 1500 1900 1650 1900 +Wire Wire Line + 1500 2000 1650 2000 +Wire Wire Line + 1500 2100 1650 2100 +Wire Wire Line + 1500 1600 1650 1600 +Wire Wire Line + 1500 1700 1650 1700 +Wire Wire Line + 1650 1500 1500 1500 +Text Notes 1375 825 0 60 ~ 0 +Bottom-side Pin Header +Text Notes 3925 825 0 60 ~ 0 +Top Side Socket Strip +Wire Notes Line + 675 650 675 5475 +Wire Notes Line + 675 5475 5600 5475 +Wire Notes Line + 5600 5475 5600 650 +Wire Notes Line + 5600 650 675 650 +$Comp +L GND #PWR? +U 1 1 59F063D1 +P 8100 5800 +F 0 "#PWR?" H 8100 5550 50 0001 C CNN +F 1 "GND" H 8100 5650 50 0000 C CNN +F 2 "" H 8100 5800 50 0001 C CNN +F 3 "" H 8100 5800 50 0001 C CNN + 1 8100 5800 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F0648C +P 6100 2550 +F 0 "#PWR?" H 6100 2400 50 0001 C CNN +F 1 "+5V" H 6100 2690 50 0000 C CNN +F 2 "" H 6100 2550 50 0001 C CNN +F 3 "" H 6100 2550 50 0001 C CNN + 1 6100 2550 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F06CC6 +P 6950 5200 +F 0 "#PWR?" H 6950 5050 50 0001 C CNN +F 1 "+5V" H 6950 5340 50 0000 C CNN +F 2 "" H 6950 5200 50 0001 C CNN +F 3 "" H 6950 5200 50 0001 C CNN + 1 6950 5200 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F06CEC +P 6700 4800 +F 0 "#PWR?" H 6700 4650 50 0001 C CNN +F 1 "+5V" H 6700 4940 50 0000 C CNN +F 2 "" H 6700 4800 50 0001 C CNN +F 3 "" H 6700 4800 50 0001 C CNN + 1 6700 4800 + 1 0 0 -1 +$EndComp +$Comp +L BS170 Q1 +U 1 1 59F0844C +P 9750 3150 +F 0 "Q1" H 9950 3225 50 0000 L CNN +F 1 "BS170" H 9950 3150 50 0000 L CNN +F 2 "TO-92" H 9950 3075 50 0000 L CIN +F 3 "" H 9750 3150 50 0000 L CNN + 1 9750 3150 + 1 0 0 -1 +$EndComp +$Comp +L BS170 Q2 +U 1 1 59F084EB +P 10350 3750 +F 0 "Q2" H 10550 3825 50 0000 L CNN +F 1 "BS170" H 10550 3750 50 0000 L CNN +F 2 "TO-92" H 10550 3675 50 0000 L CIN +F 3 "" H 10350 3750 50 0000 L CNN + 1 10350 3750 + 1 0 0 -1 +$EndComp +$Comp +L C_Small Csense1 +U 1 1 59F092A0 +P 9450 4200 +F 0 "Csense1" V 9350 4050 50 0000 L CNN +F 1 "0.1uF" V 9550 4100 50 0000 L CNN +F 2 "" H 9450 4200 50 0001 C CNN +F 3 "" H 9450 4200 50 0001 C CNN + 1 9450 4200 + 0 1 1 0 +$EndComp +$Comp +L C_Small Csense2 +U 1 1 59F0939B +P 10000 5000 +F 0 "Csense2" V 9900 4850 50 0000 L CNN +F 1 "0.1uF" V 10100 4900 50 0000 L CNN +F 2 "" H 10000 5000 50 0001 C CNN +F 3 "" H 10000 5000 50 0001 C CNN + 1 10000 5000 + 0 1 1 0 +$EndComp +$Comp +L C_Small CF +U 1 1 59F096B8 +P 7100 4300 +F 0 "CF" H 7200 4250 50 0000 L CNN +F 1 "1.0uF" H 7200 4350 50 0000 L CNN +F 2 "" H 7100 4300 50 0001 C CNN +F 3 "" H 7100 4300 50 0001 C CNN + 1 7100 4300 + -1 0 0 1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F09910 +P 10450 2200 +F 0 "#PWR?" H 10450 2050 50 0001 C CNN +F 1 "+5V" H 10450 2340 50 0000 C CNN +F 2 "" H 10450 2200 50 0001 C CNN +F 3 "" H 10450 2200 50 0001 C CNN + 1 10450 2200 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F0995C +P 9850 2200 +F 0 "#PWR?" H 9850 2050 50 0001 C CNN +F 1 "+5V" H 9850 2340 50 0000 C CNN +F 2 "" H 9850 2200 50 0001 C CNN +F 3 "" H 9850 2200 50 0001 C CNN + 1 9850 2200 + 1 0 0 -1 +$EndComp +$Comp +L R_Small Riso1 +U 1 1 59F09C36 +P 9450 3200 +F 0 "Riso1" V 9350 3100 50 0000 L CNN +F 1 "715" V 9550 3150 50 0000 L CNN +F 2 "" H 9450 3200 50 0001 C CNN +F 3 "" H 9450 3200 50 0001 C CNN + 1 9450 3200 + 0 1 1 0 +$EndComp +$Comp +L R_Small Riso2 +U 1 1 59F09D0C +P 9450 3800 +F 0 "Riso2" V 9350 3750 50 0000 L CNN +F 1 "715" V 9550 3750 50 0000 L CNN +F 2 "" H 9450 3800 50 0001 C CNN +F 3 "" H 9450 3800 50 0001 C CNN + 1 9450 3800 + 0 1 1 0 +$EndComp +$Comp +L R_Small Rsclk +U 1 1 59F09DDE +P 6700 4900 +F 0 "Rsclk" H 6800 5000 50 0000 L CNN +F 1 "20k" H 6800 4900 50 0000 L CNN +F 2 "" H 6700 4900 50 0001 C CNN +F 3 "" H 6700 4900 50 0001 C CNN + 1 6700 4900 + 1 0 0 -1 +$EndComp +$Comp +L R_Small Rsda +U 1 1 59F09EBC +P 6950 5300 +F 0 "Rsda" H 6700 5400 50 0000 L CNN +F 1 "20k" H 6750 5300 50 0000 L CNN +F 2 "" H 6950 5300 50 0001 C CNN +F 3 "" H 6950 5300 50 0001 C CNN + 1 6950 5300 + 1 0 0 -1 +$EndComp +$Comp +L R_Small Rsense1 +U 1 1 59F09F0D +P 9850 4450 +F 0 "Rsense1" H 9880 4470 50 0000 L CNN +F 1 "?" H 9880 4410 50 0000 L CNN +F 2 "" H 9850 4450 50 0001 C CNN +F 3 "" H 9850 4450 50 0001 C CNN + 1 9850 4450 + 1 0 0 -1 +$EndComp +$Comp +L R_Small Rsense2 +U 1 1 59F09F95 +P 10450 5650 +F 0 "Rsense2" H 10480 5670 50 0000 L CNN +F 1 "?" H 10480 5610 50 0000 L CNN +F 2 "" H 10450 5650 50 0001 C CNN +F 3 "" H 10450 5650 50 0001 C CNN + 1 10450 5650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F0C157 +P 9850 4550 +F 0 "#PWR?" H 9850 4300 50 0001 C CNN +F 1 "GND" H 9850 4400 50 0000 C CNN +F 2 "" H 9850 4550 50 0001 C CNN +F 3 "" H 9850 4550 50 0001 C CNN + 1 9850 4550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F0C193 +P 10450 5750 +F 0 "#PWR?" H 10450 5500 50 0001 C CNN +F 1 "GND" H 10450 5600 50 0000 C CNN +F 2 "" H 10450 5750 50 0001 C CNN +F 3 "" H 10450 5750 50 0001 C CNN + 1 10450 5750 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F0C4D2 +P 9350 5200 +F 0 "#PWR?" H 9350 5050 50 0001 C CNN +F 1 "+5V" H 9350 5340 50 0000 C CNN +F 2 "" H 9350 5200 50 0001 C CNN +F 3 "" H 9350 5200 50 0001 C CNN + 1 9350 5200 + 1 0 0 -1 +$EndComp +$Comp +L R_Small R/fault +U 1 1 59F0C510 +P 9350 5300 +F 0 "R/fault" H 9000 5200 50 0000 L CNN +F 1 "20k" H 9150 5300 50 0000 L CNN +F 2 "" H 9350 5300 50 0001 C CNN +F 3 "" H 9350 5300 50 0001 C CNN + 1 9350 5300 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F0DFE1 +P 7100 4400 +F 0 "#PWR?" H 7100 4150 50 0001 C CNN +F 1 "GND" H 7100 4250 50 0000 C CNN +F 2 "" H 7100 4400 50 0001 C CNN +F 3 "" H 7100 4400 50 0001 C CNN + 1 7100 4400 + 1 0 0 -1 +$EndComp +$Comp +L TC654/TC655 U? +U 1 1 59F0E54F +P 8100 4600 +F 0 "U?" H 8400 5200 60 0000 C CNN +F 1 "TC654/TC655" H 8100 4600 60 0000 C CNB +F 2 "" H 7800 4650 60 0001 C CNN +F 3 "" H 7800 4650 60 0001 C CNN + 1 8100 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 5400 7100 5400 +Wire Wire Line + 6500 5000 7100 5000 +Connection ~ 6700 5000 +Connection ~ 6950 5400 +Wire Wire Line + 9100 5400 9800 5400 +Connection ~ 9350 5400 +Wire Wire Line + 9100 5000 9900 5000 +Wire Wire Line + 10450 3950 10450 5550 +Connection ~ 10450 5000 +Wire Wire Line + 10100 5000 10450 5000 +Wire Wire Line + 9850 3350 9850 4350 +Wire Wire Line + 9100 4200 9350 4200 +Connection ~ 9850 4200 +Wire Wire Line + 9550 4200 9850 4200 +Wire Wire Line + 9550 3800 10150 3800 +Wire Wire Line + 9100 3800 9350 3800 +Connection ~ 9200 3800 +Wire Wire Line + 9200 3800 9200 3200 +Wire Wire Line + 9200 3200 9350 3200 +Text GLabel 6500 5000 0 60 Input ~ 0 +I2C0_SCL +Text GLabel 6500 5400 0 60 BiDi ~ 0 +I2C0_SDA +$Comp +L Fan Fan1 +U 1 1 59F12BDE +P 9850 2500 +F 0 "Fan1" H 9950 2700 50 0000 L CNN +F 1 "Fan1" H 9950 2400 50 0000 L TNN +F 2 "" H 9850 2510 50 0001 C CNN +F 3 "" H 9850 2510 50 0001 C CNN + 1 9850 2500 + 1 0 0 -1 +$EndComp +$Comp +L Fan Fan2 +U 1 1 59F12CDB +P 10450 2500 +F 0 "Fan2" H 10550 2700 50 0000 L CNN +F 1 "Fan2" H 10550 2400 50 0000 L TNN +F 2 "" H 10450 2510 50 0001 C CNN +F 3 "" H 10450 2510 50 0001 C CNN + 1 10450 2500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9850 2700 9850 2950 +Wire Wire Line + 10450 2700 10450 3550 +$Comp +L R_Small R2 +U 1 1 59F134B8 +P 6100 4000 +F 0 "R2" H 6200 4050 50 0000 L CNN +F 1 "14.7K" H 6200 3950 50 0000 L CNN +F 2 "" H 6100 4000 50 0001 C CNN +F 3 "" H 6100 4000 50 0001 C CNN + 1 6100 4000 + 1 0 0 -1 +$EndComp +$Comp +L R_Small R1 +U 1 1 59F1355A +P 6100 3550 +F 0 "R1" H 6200 3600 50 0000 L CNN +F 1 "34.8K" H 6200 3500 50 0000 L CNN +F 2 "" H 6100 3550 50 0001 C CNN +F 3 "" H 6100 3550 50 0001 C CNN + 1 6100 3550 + 1 0 0 -1 +$EndComp +$Comp +L C_Small C2 +U 1 1 59F135D3 +P 8450 3050 +F 0 "C2" H 8250 3000 50 0000 L CNN +F 1 "1uF" H 8200 3100 50 0000 L CNN +F 2 "" H 8450 3050 50 0001 C CNN +F 3 "" H 8450 3050 50 0001 C CNN + 1 8450 3050 + -1 0 0 1 +$EndComp +$Comp +L C_Small C1 +U 1 1 59F13679 +P 6600 4000 +F 0 "C1" H 6400 3950 50 0000 L CNN +F 1 "0.01uF" H 6250 4050 50 0000 L CNN +F 2 "" H 6600 4000 50 0001 C CNN +F 3 "" H 6600 4000 50 0001 C CNN + 1 6600 4000 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F156D0 +P 6600 4100 +F 0 "#PWR?" H 6600 3850 50 0001 C CNN +F 1 "GND" H 6600 3950 50 0000 C CNN +F 2 "" H 6600 4100 50 0001 C CNN +F 3 "" H 6600 4100 50 0001 C CNN + 1 6600 4100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F15781 +P 6100 4100 +F 0 "#PWR?" H 6100 3850 50 0001 C CNN +F 1 "GND" H 6100 3950 50 0000 C CNN +F 2 "" H 6100 4100 50 0001 C CNN +F 3 "" H 6100 4100 50 0001 C CNN + 1 6100 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 3800 7100 3800 +Wire Wire Line + 6600 3300 6600 3900 +Connection ~ 6600 3800 +Wire Wire Line + 6100 3650 6100 3900 +Connection ~ 6100 3800 +Wire Wire Line + 6100 2550 6100 3450 +$Comp +L Thermistor NTC_Thermistor +U 1 1 59F16197 +P 6600 3100 +F 0 "NTC_Thermistor" H 6950 3150 50 0000 C CNN +F 1 "100k @ 25°C" H 7000 3000 50 0000 C BNN +F 2 "" H 6600 3100 50 0001 C CNN +F 3 "" H 6600 3100 50 0001 C CNN + 1 6600 3100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F16680 +P 8450 3150 +F 0 "#PWR?" H 8450 2900 50 0001 C CNN +F 1 "GND" H 8450 3000 50 0000 C CNN +F 2 "" H 8450 3150 50 0001 C CNN +F 3 "" H 8450 3150 50 0001 C CNN + 1 8450 3150 + 1 0 0 -1 +$EndComp +Connection ~ 6100 2650 +Wire Wire Line + 6100 2650 8450 2650 +Wire Wire Line + 8450 2650 8450 2950 +Connection ~ 6600 2650 +Wire Wire Line + 6600 2650 6600 2900 +Connection ~ 8100 2650 +Wire Wire Line + 8100 2650 8100 3400 +Text GLabel 9800 5400 2 60 Input ~ 0 +GPIO_L +$EndSCHEMATC diff --git a/mezza.kicad_pcb b/mezza.kicad_pcb new file mode 100644 index 0000000..ae10142 --- /dev/null +++ b/mezza.kicad_pcb @@ -0,0 +1,535 @@ +(kicad_pcb (version 4) (host pcbnew 4.0.1-3.201512221401+6198~38~ubuntu15.10.1-stable) + + (general + (links 44) + (no_connects 44) + (area 85.071429 87.15 185.633753 154.050001) + (thickness 1.6) + (drawings 11) + (tracks 0) + (zones 0) + (modules 6) + (nets 37) + ) + + (page A4) + (title_block + (title "96Boards Mezzanine Project Template") + (date 2015-08-08) + (rev A) + (company "Linaro Ltd") + ) + + (layers + (0 F.Cu signal) + (31 B.Cu signal hide) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user hide) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user hide) + (48 B.Fab user hide) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.254) + (user_trace_width 0.254) + (user_trace_width 0.381) + (user_trace_width 0.635) + (trace_clearance 0.1778) + (zone_clearance 0.508) + (zone_45_only yes) + (trace_min 0.1778) + (segment_width 0.2) + (edge_width 0.1) + (via_size 0.6) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 3 3) + (pad_drill 2.5) + (pad_to_mask_clearance 0) + (aux_axis_origin 100 100) + (grid_origin 100 100) + (visible_elements FFFFFF7B) + (pcbplotparams + (layerselection 0x010ef_80000001) + (usegerberextensions false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory gerbers/)) + ) + + (net 0 "") + (net 1 +1V8) + (net 2 GND) + (net 3 +5V) + (net 4 I2C0_SCL) + (net 5 I2C0_SDA) + (net 6 I2C1_SCL) + (net 7 I2C1_SDA) + (net 8 PWR_BTN_N) + (net 9 RST_BTN_N) + (net 10 SYS_DCIN) + (net 11 GPIO_B) + (net 12 GPIO_A) + (net 13 SPIO_SCL) + (net 14 SPIO_DIN) + (net 15 SPIO_CS) + (net 16 SPIO_DOUT) + (net 17 PCM_FS) + (net 18 PCM_CLK) + (net 19 PCM_DO) + (net 20 PCM_DI) + (net 21 GPIO_D) + (net 22 GPIO_F) + (net 23 GPIO_H) + (net 24 GPIO_J) + (net 25 GPIO_L) + (net 26 UART1_TX) + (net 27 UART1_RX) + (net 28 GPIO_C) + (net 29 GPIO_E) + (net 30 GPIO_G) + (net 31 GPIO_I) + (net 32 GPIO_K) + (net 33 UART0_CTS) + (net 34 UART0_TX) + (net 35 UART0_RX) + (net 36 UART0_RTS) + + (net_class Default "This is the default net class." + (clearance 0.1778) + (trace_width 0.254) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net GPIO_A) + (add_net GPIO_B) + (add_net GPIO_C) + (add_net GPIO_D) + (add_net GPIO_E) + (add_net GPIO_F) + (add_net GPIO_G) + (add_net GPIO_H) + (add_net GPIO_I) + (add_net GPIO_J) + (add_net GPIO_K) + (add_net GPIO_L) + (add_net I2C0_SCL) + (add_net I2C0_SDA) + (add_net I2C1_SCL) + (add_net I2C1_SDA) + (add_net PCM_CLK) + (add_net PCM_DI) + (add_net PCM_DO) + (add_net PCM_FS) + (add_net PWR_BTN_N) + (add_net RST_BTN_N) + (add_net SPIO_CS) + (add_net SPIO_DIN) + (add_net SPIO_DOUT) + (add_net SPIO_SCL) + (add_net SYS_DCIN) + (add_net UART0_CTS) + (add_net UART0_RTS) + (add_net UART0_RX) + (add_net UART0_TX) + (add_net UART1_RX) + (add_net UART1_TX) + ) + + (net_class Power "" + (clearance 0.1778) + (trace_width 0.381) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +1V8) + (add_net +5V) + (add_net GND) + ) + + (module Sensors:Hole_2.5MM locked (layer F.Cu) (tedit 55DECD77) (tstamp 55F48FD6) + (at 104 135.5) + (fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Hole_2.5MM (at 0 -0.5) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.5) (layers *.Cu *.Mask)) + ) + + (module Sensors:Hole_2.5MM locked (layer F.Cu) (tedit 55DECD77) (tstamp 55DED4DA) + (at 181 135.5) + (fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Hole_2.5MM (at 0 -0.5) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.5) (layers *.Cu *.Mask)) + ) + + (module Sensors:Hole_2.5MM locked (layer F.Cu) (tedit 55C6917D) (tstamp 55C69203) + (at 181 104) + (fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Hole_2.5MM (at 0 -0.5) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.5) (layers *.Cu *.Mask)) + ) + + (module Sensors:Hole_2.5MM locked (layer F.Cu) (tedit 55C743C8) (tstamp 55C691E1) + (at 104 104) + (fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Hole_2.5MM (at 0 -0.5) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.5) (layers *.Cu *.Mask)) + ) + + (module 96boards:Socket_Strip_SMD_2x20_Pitch2mm locked (layer F.Cu) (tedit 55F865FA) (tstamp 56AB82C3) + (at 110 105 90) + (descr "Double row SMD 2mm socket strip, 2x20 contacts") + (path /55D48226) + (attr smd) + (fp_text reference P2 (at 1 -2 90) (layer F.SilkS) + (effects (font (size 0.7 0.7) (thickness 0.15))) + ) + (fp_text value CONN_02X20 (at 1 -4 90) (layer F.Fab) + (effects (font (size 1.016 1.016) (thickness 0.2032))) + ) + (fp_line (start -3 -0.75) (end -3 38.75) (layer F.SilkS) (width 0.15)) + (fp_line (start 5 38.75) (end 5 -0.75) (layer F.SilkS) (width 0.15)) + (fp_line (start 5 -0.75) (end -3 -0.75) (layer F.SilkS) (width 0.15)) + (fp_line (start 5 38.75) (end -3 38.75) (layer F.SilkS) (width 0.15)) + (pad 5 smd rect (at -1.65 4) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 34 UART0_TX)) + (pad 3 smd rect (at -1.65 2) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 33 UART0_CTS)) + (pad 4 smd rect (at 3.65 2) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 8 PWR_BTN_N)) + (pad 2 smd rect (at 3.65 -0.01) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad 1 smd rect (at -1.65 -0.01) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad 7 smd rect (at -1.65 6) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 35 UART0_RX)) + (pad 9 smd rect (at -1.65 8) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 36 UART0_RTS)) + (pad 11 smd rect (at -1.65 10) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 26 UART1_TX)) + (pad 13 smd rect (at -1.65 12) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 27 UART1_RX)) + (pad 15 smd rect (at -1.65 14) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 4 I2C0_SCL)) + (pad 17 smd rect (at -1.65 16) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 5 I2C0_SDA)) + (pad 19 smd rect (at -1.65 18) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 6 I2C1_SCL)) + (pad 21 smd rect (at -1.65 20) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 7 I2C1_SDA)) + (pad 23 smd rect (at -1.65 22) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 12 GPIO_A)) + (pad 25 smd rect (at -1.65 24) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 28 GPIO_C)) + (pad 27 smd rect (at -1.65 26) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 29 GPIO_E)) + (pad 29 smd rect (at -1.65 28) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 30 GPIO_G)) + (pad 31 smd rect (at -1.65 30) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 31 GPIO_I)) + (pad 33 smd rect (at -1.65 32) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 32 GPIO_K)) + (pad 35 smd rect (at -1.65 34) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 1 +1V8)) + (pad 37 smd rect (at -1.65 36) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 3 +5V)) + (pad 39 smd rect (at -1.65 38) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad 6 smd rect (at 3.65 4) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 9 RST_BTN_N)) + (pad 8 smd rect (at 3.65 6) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 13 SPIO_SCL)) + (pad 10 smd rect (at 3.65 8) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 14 SPIO_DIN)) + (pad 12 smd rect (at 3.65 10) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 15 SPIO_CS)) + (pad 14 smd rect (at 3.65 12) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 16 SPIO_DOUT)) + (pad 16 smd rect (at 3.65 14) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 17 PCM_FS)) + (pad 18 smd rect (at 3.65 16) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 18 PCM_CLK)) + (pad 20 smd rect (at 3.65 18) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 19 PCM_DO)) + (pad 22 smd rect (at 3.65 20) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 20 PCM_DI)) + (pad 24 smd rect (at 3.65 22) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 11 GPIO_B)) + (pad 26 smd rect (at 3.65 24) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 21 GPIO_D)) + (pad 28 smd rect (at 3.65 26) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 22 GPIO_F)) + (pad 30 smd rect (at 3.65 28) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 23 GPIO_H)) + (pad 32 smd rect (at 3.65 30) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 24 GPIO_J)) + (pad 34 smd rect (at 3.65 32) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 25 GPIO_L)) + (pad 36 smd rect (at 3.65 34) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 10 SYS_DCIN)) + (pad 38 smd rect (at 3.65 36) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 10 SYS_DCIN)) + (pad 40 smd rect (at 3.65 38) (size 0.89 2.1) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (model Socket_Strips.3dshapes/Socket_Strip_Straight_2x20.wrl + (at (xyz 0.0394 -0.749 0.01576)) + (scale (xyz 0.787 0.787 0.5)) + (rotate (xyz 0 0 90)) + ) + ) + + (module 96boards:Pin_Header_SMD_2x20_Pitch2mm locked (layer B.Cu) (tedit 55F9A19C) (tstamp 56AB8296) + (at 110 105 270) + (descr "Double row SMD 2mm pin header, 2x20 contacts") + (path /55D44709) + (attr smd) + (fp_text reference P1 (at -1 2 270) (layer B.SilkS) + (effects (font (size 0.7 0.7) (thickness 0.15)) (justify mirror)) + ) + (fp_text value CONN_02X20 (at -1 4 270) (layer B.Fab) + (effects (font (size 1.016 1.016) (thickness 0.2032)) (justify mirror)) + ) + (fp_line (start -4.95 0.6) (end -4.95 -38.7) (layer B.SilkS) (width 0.15)) + (fp_line (start -4.95 -38.7) (end 2.95 -38.7) (layer B.SilkS) (width 0.15)) + (fp_line (start -4.95 0.6) (end 2.95 0.6) (layer B.SilkS) (width 0.15)) + (fp_line (start 2.95 0.6) (end 2.95 -38.7) (layer B.SilkS) (width 0.15)) + (pad "" np_thru_hole circle (at -1 -37) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask B.SilkS)) + (pad 1 smd rect (at 1.25 0) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 2 GND)) + (pad 2 smd rect (at -3.25 0.01) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 2 GND)) + (pad "" np_thru_hole circle (at -1 -1) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask B.SilkS)) + (pad 4 smd rect (at -3.25 -2) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 8 PWR_BTN_N)) + (pad 6 smd rect (at -3.25 -4) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 9 RST_BTN_N)) + (pad 8 smd rect (at -3.25 -6) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 13 SPIO_SCL)) + (pad 10 smd rect (at -3.25 -8) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 14 SPIO_DIN)) + (pad 12 smd rect (at -3.25 -10) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 15 SPIO_CS)) + (pad 14 smd rect (at -3.25 -12) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 16 SPIO_DOUT)) + (pad 16 smd rect (at -3.25 -14) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 17 PCM_FS)) + (pad 18 smd rect (at -3.25 -16) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 18 PCM_CLK)) + (pad 20 smd rect (at -3.25 -18) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 19 PCM_DO)) + (pad 22 smd rect (at -3.25 -20) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 20 PCM_DI)) + (pad 24 smd rect (at -3.25 -22) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 11 GPIO_B)) + (pad 26 smd rect (at -3.25 -24) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 21 GPIO_D)) + (pad 28 smd rect (at -3.25 -26) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 22 GPIO_F)) + (pad 30 smd rect (at -3.25 -28) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 23 GPIO_H)) + (pad 32 smd rect (at -3.25 -30) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 24 GPIO_J)) + (pad 34 smd rect (at -3.25 -32) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 25 GPIO_L)) + (pad 36 smd rect (at -3.25 -34) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 10 SYS_DCIN)) + (pad 38 smd rect (at -3.25 -36) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 10 SYS_DCIN)) + (pad 40 smd rect (at -3.25 -38) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 2 GND)) + (pad 3 smd rect (at 1.25 -2) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 33 UART0_CTS)) + (pad 5 smd rect (at 1.25 -4) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 34 UART0_TX)) + (pad 7 smd rect (at 1.25 -6) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 35 UART0_RX)) + (pad 9 smd rect (at 1.25 -8) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 36 UART0_RTS)) + (pad 11 smd rect (at 1.25 -10) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 26 UART1_TX)) + (pad 13 smd rect (at 1.25 -12) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 27 UART1_RX)) + (pad 15 smd rect (at 1.25 -14) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 4 I2C0_SCL)) + (pad 17 smd rect (at 1.25 -16) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 5 I2C0_SDA)) + (pad 19 smd rect (at 1.25 -18) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 6 I2C1_SCL)) + (pad 21 smd rect (at 1.25 -20) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 7 I2C1_SDA)) + (pad 23 smd rect (at 1.25 -22) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 12 GPIO_A)) + (pad 25 smd rect (at 1.25 -24) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 28 GPIO_C)) + (pad 27 smd rect (at 1.25 -26) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 29 GPIO_E)) + (pad 29 smd rect (at 1.25 -28) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 30 GPIO_G)) + (pad 31 smd rect (at 1.25 -30) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 31 GPIO_I)) + (pad 33 smd rect (at 1.25 -32) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 32 GPIO_K)) + (pad 35 smd rect (at 1.25 -34) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 1 +1V8)) + (pad 37 smd rect (at 1.25 -36) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 3 +5V)) + (pad 39 smd rect (at 1.25 -38) (size 0.89 3) (layers B.Cu B.Paste B.Mask) + (net 2 GND)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_2x20.wrl + (at (xyz -0.0394 -0.749 0.01576)) + (scale (xyz 0.787 0.787 0.5)) + (rotate (xyz 0 0 90)) + ) + ) + + (dimension 18.5 (width 0.3) (layer F.Fab) + (gr_text 18.5mm (at 93.65 144.75 90) (layer F.Fab) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (feature1 (pts (xy 104 135.5) (xy 92.3 135.5))) + (feature2 (pts (xy 104 154) (xy 92.3 154))) + (crossbar (pts (xy 95 154) (xy 95 135.5))) + (arrow1a (pts (xy 95 135.5) (xy 95.586421 136.626504))) + (arrow1b (pts (xy 95 135.5) (xy 94.413579 136.626504))) + (arrow2a (pts (xy 95 154) (xy 95.586421 152.873496))) + (arrow2b (pts (xy 95 154) (xy 94.413579 152.873496))) + ) + (dimension 4 (width 0.3) (layer F.Fab) + (gr_text 4mm (at 95 107 90) (layer F.Fab) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (feature1 (pts (xy 104 100) (xy 92.3 100))) + (feature2 (pts (xy 104 104) (xy 92.3 104))) + (crossbar (pts (xy 95 104) (xy 95 100))) + (arrow1a (pts (xy 95 100) (xy 95.586421 101.126504))) + (arrow1b (pts (xy 95 100) (xy 94.413579 101.126504))) + (arrow2a (pts (xy 95 104) (xy 95.586421 102.873496))) + (arrow2b (pts (xy 95 104) (xy 94.413579 102.873496))) + ) + (dimension 4 (width 0.3) (layer F.Fab) + (gr_text 4mm (at 178 95) (layer F.Fab) (tstamp 56AB8CC9) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (feature1 (pts (xy 185 104) (xy 185 92.3))) + (feature2 (pts (xy 181 104) (xy 181 92.3))) + (crossbar (pts (xy 181 95) (xy 185 95))) + (arrow1a (pts (xy 185 95) (xy 183.873496 95.586421))) + (arrow1b (pts (xy 185 95) (xy 183.873496 94.413579))) + (arrow2a (pts (xy 181 95) (xy 182.126504 95.586421))) + (arrow2b (pts (xy 181 95) (xy 182.126504 94.413579))) + ) + (dimension 6 (width 0.3) (layer F.Fab) + (gr_text 6mm (at 113 95) (layer F.Fab) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (feature1 (pts (xy 110 104) (xy 110 92.3))) + (feature2 (pts (xy 104 104) (xy 104 92.3))) + (crossbar (pts (xy 104 95) (xy 110 95))) + (arrow1a (pts (xy 110 95) (xy 108.873496 95.586421))) + (arrow1b (pts (xy 110 95) (xy 108.873496 94.413579))) + (arrow2a (pts (xy 104 95) (xy 105.126504 95.586421))) + (arrow2b (pts (xy 104 95) (xy 105.126504 94.413579))) + ) + (dimension 4 (width 0.3) (layer F.Fab) + (gr_text 4mm (at 97 95) (layer F.Fab) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (feature1 (pts (xy 104 104) (xy 104 92.3))) + (feature2 (pts (xy 100 104) (xy 100 92.3))) + (crossbar (pts (xy 100 95) (xy 104 95))) + (arrow1a (pts (xy 104 95) (xy 102.873496 95.586421))) + (arrow1b (pts (xy 104 95) (xy 102.873496 94.413579))) + (arrow2a (pts (xy 100 95) (xy 101.126504 95.586421))) + (arrow2b (pts (xy 100 95) (xy 101.126504 94.413579))) + ) + (dimension 85 (width 0.3) (layer F.Fab) + (gr_text 85mm (at 142.5 88.65) (layer F.Fab) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (feature1 (pts (xy 185 100) (xy 185 87.3))) + (feature2 (pts (xy 100 100) (xy 100 87.3))) + (crossbar (pts (xy 100 90) (xy 185 90))) + (arrow1a (pts (xy 185 90) (xy 183.873496 90.586421))) + (arrow1b (pts (xy 185 90) (xy 183.873496 89.413579))) + (arrow2a (pts (xy 100 90) (xy 101.126504 90.586421))) + (arrow2b (pts (xy 100 90) (xy 101.126504 89.413579))) + ) + (dimension 54 (width 0.3) (layer F.Fab) + (gr_text 54mm (at 88.65 127 90) (layer F.Fab) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (feature1 (pts (xy 100 100) (xy 87.3 100))) + (feature2 (pts (xy 100 154) (xy 87.3 154))) + (crossbar (pts (xy 90 154) (xy 90 100))) + (arrow1a (pts (xy 90 100) (xy 90.586421 101.126504))) + (arrow1b (pts (xy 90 100) (xy 89.413579 101.126504))) + (arrow2a (pts (xy 90 154) (xy 90.586421 152.873496))) + (arrow2b (pts (xy 90 154) (xy 89.413579 152.873496))) + ) + (gr_line (start 100 154) (end 184.999492 154) (angle 90) (layer Edge.Cuts) (width 0.1) (tstamp 55F1F924)) + (gr_line (start 184.999492 100) (end 184.999492 154) (angle 90) (layer Edge.Cuts) (width 0.1)) + (gr_line (start 100 154) (end 100 100) (angle 90) (layer Edge.Cuts) (width 0.1)) + (gr_line (start 100 100) (end 184.999492 100) (angle 90) (layer Edge.Cuts) (width 0.1)) + +) diff --git a/mezza.pro b/mezza.pro new file mode 100644 index 0000000..f01e76a --- /dev/null +++ b/mezza.pro @@ -0,0 +1,73 @@ +update=mer. 25 oct. 2017 15:37:23 CEST +version=1 +last_client=kicad +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[general] +version=1 +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=96boards +LibName31=pmw-fan +LibName32=Motor diff --git a/mezza.sch b/mezza.sch new file mode 100644 index 0000000..17fcfdb --- /dev/null +++ b/mezza.sch @@ -0,0 +1,969 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:96boards +LIBS:pmw-fan +LIBS:Motor +LIBS:mezza-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "96Boards Mezzanine Project Template" +Date "14 Aug 2015" +Rev "A" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text GLabel 3950 1500 0 60 Output ~ 0 +UART0_RTS +$Comp +L GND #PWR01 +U 1 1 55D481C7 +P 3950 950 +F 0 "#PWR01" H 3950 700 50 0001 C CNN +F 1 "GND" H 3950 800 50 0000 C CNN +F 2 "" H 3950 950 60 0000 C CNN +F 3 "" H 3950 950 60 0000 C CNN + 1 3950 950 + 1 0 0 -1 +$EndComp +Text GLabel 3950 1300 0 60 Output ~ 0 +UART0_TX +$Comp +L GND #PWR02 +U 1 1 55D481CF +P 4000 3000 +F 0 "#PWR02" H 4000 2750 50 0001 C CNN +F 1 "GND" H 4000 2850 50 0000 C CNN +F 2 "" H 4000 3000 60 0000 C CNN +F 3 "" H 4000 3000 60 0000 C CNN + 1 4000 3000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 55D481D5 +P 4700 3000 +F 0 "#PWR03" H 4700 2750 50 0001 C CNN +F 1 "GND" H 4700 2850 50 0000 C CNN +F 2 "" H 4700 3000 60 0000 C CNN +F 3 "" H 4700 3000 60 0000 C CNN + 1 4700 3000 + 1 0 0 -1 +$EndComp +Text GLabel 3950 1200 0 60 Input ~ 0 +UART0_CTS +Text GLabel 4700 2900 2 60 Input ~ 0 +SYS_DCIN +$Comp +L GND #PWR04 +U 1 1 55D48218 +P 4750 950 +F 0 "#PWR04" H 4750 700 50 0001 C CNN +F 1 "GND" H 4750 800 50 0000 C CNN +F 2 "" H 4750 950 60 0000 C CNN +F 3 "" H 4750 950 60 0000 C CNN + 1 4750 950 + 1 0 0 -1 +$EndComp +$Comp +L CONN_02X20 P2 +U 1 1 55D48226 +P 4350 2050 +F 0 "P2" H 4350 3100 50 0000 C CNN +F 1 "CONN_02X20" V 4350 2050 50 0000 C CNN +F 2 "96boards:Socket_Strip_SMD_2x20_Pitch2mm" H 4350 1100 60 0001 C CNN +F 3 "" H 4350 1100 60 0000 C CNN +F 4 "Yxcon" H 4350 2050 60 0001 C CNN "Mfr" +F 5 "F240-1220A0xMUx1" H 4350 2050 60 0001 C CNN "Mfr Part #" + 1 4350 2050 + 1 0 0 -1 +$EndComp +$Comp +L +1V8 #PWR05 +U 1 1 55D4822C +P 3450 2750 +F 0 "#PWR05" H 3450 2600 50 0001 C CNN +F 1 "+1V8" H 3450 2890 50 0000 C CNN +F 2 "" H 3450 2750 60 0000 C CNN +F 3 "" H 3450 2750 60 0000 C CNN + 1 3450 2750 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR06 +U 1 1 55D48233 +P 3250 2750 +F 0 "#PWR06" H 3250 2600 50 0001 C CNN +F 1 "+5V" H 3250 2890 50 0000 C CNN +F 2 "" H 3250 2750 60 0000 C CNN +F 3 "" H 3250 2750 60 0000 C CNN + 1 3250 2750 + 1 0 0 -1 +$EndComp +Text GLabel 4700 1300 2 60 Input ~ 0 +RST_BTN_N +Text GLabel 3950 2100 0 60 BiDi ~ 0 +I2C1_SDA +Text GLabel 3950 2000 0 60 BiDi ~ 0 +I2C1_SCL +Text GLabel 3950 1900 0 60 BiDi ~ 0 +I2C0_SDA +Text GLabel 3950 1800 0 60 BiDi ~ 0 +I2C0_SCL +Text GLabel 3950 2200 0 60 Input ~ 0 +GPIO_A +Text GLabel 3950 1400 0 60 Input ~ 0 +UART0_RX +Text Notes 875 5350 0 60 ~ 0 +96Boards Low-Speed Expansion Connectors\n\nBy default, this is set up for a stackable surface-mount\narrangement. Do the following to switch to a through-hole\nconnector:\n\nOption 1) For a surface-mount non-stackable connector\n- Delete P2\n\nOption 2) For a through-hole non-stackable pin header\n- Delete P2\n- Change P1 footprint to "Pin_Header_Straight_2x20_Pitch2mm"\n\nOption 3) For a through-hole stackable socket strip connector\n- Delete P1\n- Change P2 footprint to "Socket_Strip_Straight_2x20_Pitch2mm"\n\nOption 2 and 3 are electrically equivalent. They differ on which side\nof the board to place the silkscreen labels.\n\nDelete this note once you have chosen the connector style. +Text GLabel 4700 1200 2 60 Input ~ 0 +PWR_BTN_N +Text GLabel 3950 1600 0 60 Input ~ 0 +UART1_TX +Text GLabel 3950 2300 0 60 Input ~ 0 +GPIO_C +Text GLabel 3950 2400 0 60 Input ~ 0 +GPIO_E +Text GLabel 3950 2500 0 60 Input ~ 0 +GPIO_G +Text GLabel 3950 2600 0 60 Input ~ 0 +GPIO_I +Text GLabel 3950 2700 0 60 Input ~ 0 +GPIO_K +Text GLabel 3950 1700 0 60 Input ~ 0 +UART1_RX +Text GLabel 4700 2200 2 60 Input ~ 0 +GPIO_B +Text GLabel 4700 1400 2 60 Input ~ 0 +SPIO_SCL +Text GLabel 4700 1500 2 60 Input ~ 0 +SPIO_DIN +Text GLabel 4700 1600 2 60 Input ~ 0 +SPIO_CS +Text GLabel 4700 1700 2 60 Input ~ 0 +SPIO_DOUT +Text GLabel 4700 1800 2 60 Input ~ 0 +PCM_FS +Text GLabel 4700 1900 2 60 Input ~ 0 +PCM_CLK +Text GLabel 4700 2000 2 60 Input ~ 0 +PCM_DO +Text GLabel 4700 2100 2 60 Input ~ 0 +PCM_DI +Text GLabel 4700 2300 2 60 Input ~ 0 +GPIO_D +Text GLabel 4700 2400 2 60 Input ~ 0 +GPIO_F +Text GLabel 4700 2500 2 60 Input ~ 0 +GPIO_H +Text GLabel 4700 2600 2 60 Input ~ 0 +GPIO_J +Text GLabel 4700 2700 2 60 Input ~ 0 +GPIO_L +Wire Wire Line + 4600 1200 4700 1200 +Wire Wire Line + 4600 900 4750 900 +Wire Wire Line + 4750 900 4750 950 +Wire Wire Line + 3250 2750 3250 2900 +Wire Wire Line + 3450 2750 3450 2800 +Wire Wire Line + 3950 2400 4100 2400 +Wire Wire Line + 3950 2500 4100 2500 +Wire Wire Line + 3950 2600 4100 2600 +Wire Wire Line + 3950 2700 4100 2700 +Wire Wire Line + 3450 2800 4100 2800 +Wire Wire Line + 4100 900 4100 1100 +Wire Wire Line + 3950 900 4100 900 +Wire Wire Line + 4600 900 4600 1100 +Wire Wire Line + 4600 1300 4700 1300 +Wire Wire Line + 4600 1400 4700 1400 +Wire Wire Line + 4600 1500 4700 1500 +Wire Wire Line + 4600 1600 4700 1600 +Wire Wire Line + 4600 1700 4700 1700 +Wire Wire Line + 4600 1800 4700 1800 +Wire Wire Line + 4600 1900 4700 1900 +Wire Wire Line + 4600 2000 4700 2000 +Wire Wire Line + 4600 2100 4700 2100 +Wire Wire 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1500 950 +F 0 "#PWR07" H 1500 700 50 0001 C CNN +F 1 "GND" H 1500 800 50 0000 C CNN +F 2 "" H 1500 950 60 0000 C CNN +F 3 "" H 1500 950 60 0000 C CNN + 1 1500 950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR08 +U 1 1 55BEA10A +P 1550 3000 +F 0 "#PWR08" H 1550 2750 50 0001 C CNN +F 1 "GND" H 1550 2850 50 0000 C CNN +F 2 "" H 1550 3000 60 0000 C CNN +F 3 "" H 1550 3000 60 0000 C CNN + 1 1550 3000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR09 +U 1 1 55BEA0BC +P 2250 3000 +F 0 "#PWR09" H 2250 2750 50 0001 C CNN +F 1 "GND" H 2250 2850 50 0000 C CNN +F 2 "" H 2250 3000 60 0000 C CNN +F 3 "" H 2250 3000 60 0000 C CNN + 1 2250 3000 + 1 0 0 -1 +$EndComp +Text GLabel 2250 2900 2 60 Input ~ 0 +SYS_DCIN +$Comp +L GND #PWR010 +U 1 1 55D43BD4 +P 2300 950 +F 0 "#PWR010" H 2300 700 50 0001 C CNN +F 1 "GND" H 2300 800 50 0000 C CNN +F 2 "" H 2300 950 60 0000 C CNN +F 3 "" H 2300 950 60 0000 C CNN + 1 2300 950 + 1 0 0 -1 +$EndComp +$Comp +L CONN_02X20 P1 +U 1 1 55D44709 +P 1900 2050 +F 0 "P1" H 1900 3100 50 0000 C CNN +F 1 "CONN_02X20" V 1900 2050 50 0000 C CNN +F 2 "96boards:Pin_Header_SMD_2x20_Pitch2mm" H 1900 1100 60 0001 C CNN +F 3 "" H 1900 1100 60 0000 C CNN +F 4 "Yxcon" H 1900 2050 60 0001 C CNN "Mfr" +F 5 "P220-1220A0xMxxxx2" H 1900 2050 60 0001 C CNN "Mfr Part #" + 1 1900 2050 + 1 0 0 -1 +$EndComp +$Comp +L +1V8 #PWR011 +U 1 1 55D43CFB +P 1000 2750 +F 0 "#PWR011" H 1000 2600 50 0001 C CNN +F 1 "+1V8" H 1000 2890 50 0000 C CNN +F 2 "" H 1000 2750 60 0000 C CNN +F 3 "" H 1000 2750 60 0000 C CNN + 1 1000 2750 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR012 +U 1 1 55D440FD +P 800 2750 +F 0 "#PWR012" H 800 2600 50 0001 C CNN +F 1 "+5V" H 800 2890 50 0000 C CNN +F 2 "" H 800 2750 60 0000 C CNN +F 3 "" H 800 2750 60 0000 C CNN + 1 800 2750 + 1 0 0 -1 +$EndComp +Text GLabel 1500 2100 0 60 BiDi ~ 0 +I2C1_SDA +Text GLabel 1500 2000 0 60 BiDi ~ 0 +I2C1_SCL +Text GLabel 1500 1900 0 60 BiDi ~ 0 +I2C0_SDA +Text GLabel 1500 1800 0 60 BiDi ~ 0 +I2C0_SCL +Text GLabel 2250 1200 2 60 Input ~ 0 +PWR_BTN_N +Text GLabel 2250 1300 2 60 Input ~ 0 +RST_BTN_N +Text GLabel 1500 1500 0 60 Output ~ 0 +UART0_RTS +Text GLabel 1500 1400 0 60 Input ~ 0 +UART0_RX +Text GLabel 1500 1300 0 60 Output ~ 0 +UART0_TX +Text GLabel 1500 1200 0 60 Input ~ 0 +UART0_CTS +Text GLabel 1500 2200 0 60 Input ~ 0 +GPIO_A +Text GLabel 2250 2200 2 60 Input ~ 0 +GPIO_B +Text GLabel 1500 1600 0 60 Input ~ 0 +UART1_TX +Text GLabel 1500 1700 0 60 Input ~ 0 +UART1_RX +Text GLabel 1500 2300 0 60 Input ~ 0 +GPIO_C +Text GLabel 1500 2400 0 60 Input ~ 0 +GPIO_E +Text GLabel 1500 2500 0 60 Input ~ 0 +GPIO_G +Text GLabel 1500 2600 0 60 Input ~ 0 +GPIO_I +Text GLabel 1500 2700 0 60 Input ~ 0 +GPIO_K +Text GLabel 2250 1400 2 60 Input ~ 0 +SPIO_SCL +Text GLabel 2250 1500 2 60 Input ~ 0 +SPIO_DIN +Text GLabel 2250 1600 2 60 Input ~ 0 +SPIO_CS +Text GLabel 2250 1700 2 60 Input ~ 0 +SPIO_DOUT +Text GLabel 2250 1800 2 60 Input ~ 0 +PCM_FS +Text GLabel 2250 1900 2 60 Input ~ 0 +PCM_CLK +Text GLabel 2250 2000 2 60 Input ~ 0 +PCM_DO +Text GLabel 2250 2100 2 60 Input ~ 0 +PCM_DI +Text GLabel 2250 2300 2 60 Input ~ 0 +GPIO_D +Text GLabel 2250 2400 2 60 Input ~ 0 +GPIO_F +Text GLabel 2250 2500 2 60 Input ~ 0 +GPIO_H +Text GLabel 2250 2600 2 60 Input ~ 0 +GPIO_J +Text GLabel 2250 2700 2 60 Input ~ 0 +GPIO_L +Wire Wire Line + 2150 900 2300 900 +Wire Wire Line + 2300 900 2300 950 +Wire Wire Line + 800 2750 800 2900 +Wire Wire Line + 1000 2750 1000 2800 +Wire Wire Line + 1500 2400 1650 2400 +Wire Wire Line + 1500 2500 1650 2500 +Wire Wire Line + 1500 2600 1650 2600 +Wire Wire Line + 1500 2700 1650 2700 +Wire Wire Line + 1000 2800 1650 2800 +Wire Wire Line + 1650 900 1650 1100 +Wire Wire Line + 1500 900 1650 900 +Wire Wire Line + 2150 900 2150 1100 +Wire Wire Line + 2150 1200 2250 1200 +Wire Wire Line + 2150 1300 2250 1300 +Wire Wire Line + 2150 1400 2250 1400 +Wire Wire Line + 2150 1500 2250 1500 +Wire Wire Line + 2150 1600 2250 1600 +Wire Wire Line + 2150 1700 2250 1700 +Wire Wire Line + 2150 1800 2250 1800 +Wire Wire Line + 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Wire Line + 1500 1700 1650 1700 +Wire Wire Line + 1650 1500 1500 1500 +Text Notes 1375 825 0 60 ~ 0 +Bottom-side Pin Header +Text Notes 3925 825 0 60 ~ 0 +Top Side Socket Strip +Wire Notes Line + 675 650 675 5475 +Wire Notes Line + 675 5475 5600 5475 +Wire Notes Line + 5600 5475 5600 650 +Wire Notes Line + 5600 650 675 650 +$Comp +L GND #PWR? +U 1 1 59F063D1 +P 8100 5800 +F 0 "#PWR?" H 8100 5550 50 0001 C CNN +F 1 "GND" H 8100 5650 50 0000 C CNN +F 2 "" H 8100 5800 50 0001 C CNN +F 3 "" H 8100 5800 50 0001 C CNN + 1 8100 5800 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F0648C +P 6100 2550 +F 0 "#PWR?" H 6100 2400 50 0001 C CNN +F 1 "+5V" H 6100 2690 50 0000 C CNN +F 2 "" H 6100 2550 50 0001 C CNN +F 3 "" H 6100 2550 50 0001 C CNN + 1 6100 2550 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F06CC6 +P 6950 5200 +F 0 "#PWR?" H 6950 5050 50 0001 C CNN +F 1 "+5V" H 6950 5340 50 0000 C CNN +F 2 "" H 6950 5200 50 0001 C CNN +F 3 "" H 6950 5200 50 0001 C CNN + 1 6950 5200 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F06CEC +P 6700 4800 +F 0 "#PWR?" H 6700 4650 50 0001 C CNN +F 1 "+5V" H 6700 4940 50 0000 C CNN +F 2 "" H 6700 4800 50 0001 C CNN +F 3 "" H 6700 4800 50 0001 C CNN + 1 6700 4800 + 1 0 0 -1 +$EndComp +$Comp +L BS170 Q1 +U 1 1 59F0844C +P 9750 3150 +F 0 "Q1" H 9950 3225 50 0000 L CNN +F 1 "BS170" H 9950 3150 50 0000 L CNN +F 2 "TO-92" H 9950 3075 50 0000 L CIN +F 3 "" H 9750 3150 50 0000 L CNN + 1 9750 3150 + 1 0 0 -1 +$EndComp +$Comp +L BS170 Q2 +U 1 1 59F084EB +P 10350 3750 +F 0 "Q2" H 10550 3825 50 0000 L CNN +F 1 "BS170" H 10550 3750 50 0000 L CNN +F 2 "TO-92" H 10550 3675 50 0000 L CIN +F 3 "" H 10350 3750 50 0000 L CNN + 1 10350 3750 + 1 0 0 -1 +$EndComp +$Comp +L C_Small Csense1 +U 1 1 59F092A0 +P 9450 4200 +F 0 "Csense1" V 9350 4050 50 0000 L CNN +F 1 "0.1uF" V 9550 4100 50 0000 L CNN +F 2 "" H 9450 4200 50 0001 C CNN +F 3 "" H 9450 4200 50 0001 C CNN + 1 9450 4200 + 0 1 1 0 +$EndComp +$Comp +L C_Small Csense2 +U 1 1 59F0939B +P 10000 5000 +F 0 "Csense2" V 9900 4850 50 0000 L CNN +F 1 "0.1uF" V 10100 4900 50 0000 L CNN +F 2 "" H 10000 5000 50 0001 C CNN +F 3 "" H 10000 5000 50 0001 C CNN + 1 10000 5000 + 0 1 1 0 +$EndComp +$Comp +L C_Small CF +U 1 1 59F096B8 +P 7100 4300 +F 0 "CF" H 7200 4250 50 0000 L CNN +F 1 "1.0uF" H 7200 4350 50 0000 L CNN +F 2 "" H 7100 4300 50 0001 C CNN +F 3 "" H 7100 4300 50 0001 C CNN + 1 7100 4300 + -1 0 0 1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F09910 +P 10450 2200 +F 0 "#PWR?" H 10450 2050 50 0001 C CNN +F 1 "+5V" H 10450 2340 50 0000 C CNN +F 2 "" H 10450 2200 50 0001 C CNN +F 3 "" H 10450 2200 50 0001 C CNN + 1 10450 2200 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F0995C +P 9850 2200 +F 0 "#PWR?" H 9850 2050 50 0001 C CNN +F 1 "+5V" H 9850 2340 50 0000 C CNN +F 2 "" H 9850 2200 50 0001 C CNN +F 3 "" H 9850 2200 50 0001 C CNN + 1 9850 2200 + 1 0 0 -1 +$EndComp +$Comp +L R_Small Riso1 +U 1 1 59F09C36 +P 9450 3200 +F 0 "Riso1" V 9350 3100 50 0000 L CNN +F 1 "715" V 9550 3150 50 0000 L CNN +F 2 "" H 9450 3200 50 0001 C CNN +F 3 "" H 9450 3200 50 0001 C CNN + 1 9450 3200 + 0 1 1 0 +$EndComp +$Comp +L R_Small Riso2 +U 1 1 59F09D0C +P 9450 3800 +F 0 "Riso2" V 9350 3750 50 0000 L CNN +F 1 "715" V 9550 3750 50 0000 L CNN +F 2 "" H 9450 3800 50 0001 C CNN +F 3 "" H 9450 3800 50 0001 C CNN + 1 9450 3800 + 0 1 1 0 +$EndComp +$Comp +L R_Small Rsclk +U 1 1 59F09DDE +P 6700 4900 +F 0 "Rsclk" H 6800 5000 50 0000 L CNN +F 1 "20k" H 6800 4900 50 0000 L CNN +F 2 "" H 6700 4900 50 0001 C CNN +F 3 "" H 6700 4900 50 0001 C CNN + 1 6700 4900 + 1 0 0 -1 +$EndComp +$Comp +L R_Small Rsda +U 1 1 59F09EBC +P 6950 5300 +F 0 "Rsda" H 6700 5400 50 0000 L CNN +F 1 "20k" H 6750 5300 50 0000 L CNN +F 2 "" H 6950 5300 50 0001 C CNN +F 3 "" H 6950 5300 50 0001 C CNN + 1 6950 5300 + 1 0 0 -1 +$EndComp +$Comp +L R_Small Rsense1 +U 1 1 59F09F0D +P 9850 4450 +F 0 "Rsense1" H 9880 4470 50 0000 L CNN +F 1 "?" H 9880 4410 50 0000 L CNN +F 2 "" H 9850 4450 50 0001 C CNN +F 3 "" H 9850 4450 50 0001 C CNN + 1 9850 4450 + 1 0 0 -1 +$EndComp +$Comp +L R_Small Rsense2 +U 1 1 59F09F95 +P 10450 5650 +F 0 "Rsense2" H 10480 5670 50 0000 L CNN +F 1 "?" H 10480 5610 50 0000 L CNN +F 2 "" H 10450 5650 50 0001 C CNN +F 3 "" H 10450 5650 50 0001 C CNN + 1 10450 5650 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F0C157 +P 9850 4550 +F 0 "#PWR?" H 9850 4300 50 0001 C CNN +F 1 "GND" H 9850 4400 50 0000 C CNN +F 2 "" H 9850 4550 50 0001 C CNN +F 3 "" H 9850 4550 50 0001 C CNN + 1 9850 4550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F0C193 +P 10450 5750 +F 0 "#PWR?" H 10450 5500 50 0001 C CNN +F 1 "GND" H 10450 5600 50 0000 C CNN +F 2 "" H 10450 5750 50 0001 C CNN +F 3 "" H 10450 5750 50 0001 C CNN + 1 10450 5750 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR? +U 1 1 59F0C4D2 +P 9350 5200 +F 0 "#PWR?" H 9350 5050 50 0001 C CNN +F 1 "+5V" H 9350 5340 50 0000 C CNN +F 2 "" H 9350 5200 50 0001 C CNN +F 3 "" H 9350 5200 50 0001 C CNN + 1 9350 5200 + 1 0 0 -1 +$EndComp +$Comp +L R_Small R/fault +U 1 1 59F0C510 +P 9350 5300 +F 0 "R/fault" H 9000 5200 50 0000 L CNN +F 1 "20k" H 9150 5300 50 0000 L CNN +F 2 "" H 9350 5300 50 0001 C CNN +F 3 "" H 9350 5300 50 0001 C CNN + 1 9350 5300 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F0DFE1 +P 7100 4400 +F 0 "#PWR?" H 7100 4150 50 0001 C CNN +F 1 "GND" H 7100 4250 50 0000 C CNN +F 2 "" H 7100 4400 50 0001 C CNN +F 3 "" H 7100 4400 50 0001 C CNN + 1 7100 4400 + 1 0 0 -1 +$EndComp +$Comp +L TC654/TC655 U? +U 1 1 59F0E54F +P 8100 4600 +F 0 "U?" H 8400 5200 60 0000 C CNN +F 1 "TC654/TC655" H 8100 4600 60 0000 C CNB +F 2 "" H 7800 4650 60 0001 C CNN +F 3 "" H 7800 4650 60 0001 C CNN + 1 8100 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 5400 7100 5400 +Wire Wire Line + 6500 5000 7100 5000 +Connection ~ 6700 5000 +Connection ~ 6950 5400 +Wire Wire Line + 9100 5400 9800 5400 +Connection ~ 9350 5400 +Wire Wire Line + 9100 5000 9900 5000 +Wire Wire Line + 10450 3950 10450 5550 +Connection ~ 10450 5000 +Wire Wire Line + 10100 5000 10450 5000 +Wire Wire Line + 9850 3350 9850 4350 +Wire Wire Line + 9100 4200 9350 4200 +Connection ~ 9850 4200 +Wire Wire Line + 9550 4200 9850 4200 +Wire Wire Line + 9550 3800 10150 3800 +Wire Wire Line + 9100 3800 9350 3800 +Connection ~ 9200 3800 +Wire Wire Line + 9200 3800 9200 3200 +Wire Wire Line + 9200 3200 9350 3200 +Text GLabel 6500 5000 0 60 Input ~ 0 +I2C0_SCL +Text GLabel 6500 5400 0 60 BiDi ~ 0 +I2C0_SDA +$Comp +L Fan Fan1 +U 1 1 59F12BDE +P 9850 2500 +F 0 "Fan1" H 9950 2700 50 0000 L CNN +F 1 "Fan1" H 9950 2400 50 0000 L TNN +F 2 "" H 9850 2510 50 0001 C CNN +F 3 "" H 9850 2510 50 0001 C CNN + 1 9850 2500 + 1 0 0 -1 +$EndComp +$Comp +L Fan Fan2 +U 1 1 59F12CDB +P 10450 2500 +F 0 "Fan2" H 10550 2700 50 0000 L CNN +F 1 "Fan2" H 10550 2400 50 0000 L TNN +F 2 "" H 10450 2510 50 0001 C CNN +F 3 "" H 10450 2510 50 0001 C CNN + 1 10450 2500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9850 2700 9850 2950 +Wire Wire Line + 10450 2700 10450 3550 +$Comp +L R_Small R2 +U 1 1 59F134B8 +P 6100 4000 +F 0 "R2" H 6200 4050 50 0000 L CNN +F 1 "14.7K" H 6200 3950 50 0000 L CNN +F 2 "" H 6100 4000 50 0001 C CNN +F 3 "" H 6100 4000 50 0001 C CNN + 1 6100 4000 + 1 0 0 -1 +$EndComp +$Comp +L R_Small R1 +U 1 1 59F1355A +P 6100 3550 +F 0 "R1" H 6200 3600 50 0000 L CNN +F 1 "34.8K" H 6200 3500 50 0000 L CNN +F 2 "" H 6100 3550 50 0001 C CNN +F 3 "" H 6100 3550 50 0001 C CNN + 1 6100 3550 + 1 0 0 -1 +$EndComp +$Comp +L C_Small C2 +U 1 1 59F135D3 +P 8450 3050 +F 0 "C2" H 8250 3000 50 0000 L CNN +F 1 "1uF" H 8200 3100 50 0000 L CNN +F 2 "" H 8450 3050 50 0001 C CNN +F 3 "" H 8450 3050 50 0001 C CNN + 1 8450 3050 + -1 0 0 1 +$EndComp +$Comp +L C_Small C1 +U 1 1 59F13679 +P 6600 4000 +F 0 "C1" H 6400 3950 50 0000 L CNN +F 1 "0.01uF" H 6250 4050 50 0000 L CNN +F 2 "" H 6600 4000 50 0001 C CNN +F 3 "" H 6600 4000 50 0001 C CNN + 1 6600 4000 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F156D0 +P 6600 4100 +F 0 "#PWR?" H 6600 3850 50 0001 C CNN +F 1 "GND" H 6600 3950 50 0000 C CNN +F 2 "" H 6600 4100 50 0001 C CNN +F 3 "" H 6600 4100 50 0001 C CNN + 1 6600 4100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F15781 +P 6100 4100 +F 0 "#PWR?" H 6100 3850 50 0001 C CNN +F 1 "GND" H 6100 3950 50 0000 C CNN +F 2 "" H 6100 4100 50 0001 C CNN +F 3 "" H 6100 4100 50 0001 C CNN + 1 6100 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 3800 7100 3800 +Wire Wire Line + 6600 3300 6600 3900 +Connection ~ 6600 3800 +Wire Wire Line + 6100 3650 6100 3900 +Connection ~ 6100 3800 +Wire Wire Line + 6100 2550 6100 3450 +$Comp +L Thermistor NTC_Thermistor +U 1 1 59F16197 +P 6600 3100 +F 0 "NTC_Thermistor" H 6950 3150 50 0000 C CNN +F 1 "100k @ 25°C" H 7000 3000 50 0000 C BNN +F 2 "" H 6600 3100 50 0001 C CNN +F 3 "" H 6600 3100 50 0001 C CNN + 1 6600 3100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR? +U 1 1 59F16680 +P 8450 3150 +F 0 "#PWR?" H 8450 2900 50 0001 C CNN +F 1 "GND" H 8450 3000 50 0000 C CNN +F 2 "" H 8450 3150 50 0001 C CNN +F 3 "" H 8450 3150 50 0001 C CNN + 1 8450 3150 + 1 0 0 -1 +$EndComp +Connection ~ 6100 2650 +Wire Wire Line + 6100 2650 8450 2650 +Wire Wire Line + 8450 2650 8450 2950 +Connection ~ 6600 2650 +Wire Wire Line + 6600 2650 6600 2900 +Connection ~ 8100 2650 +Wire Wire Line + 8100 2650 8100 3400 +Text GLabel 9800 5400 2 60 Input ~ 0 +GPIO_L +$EndSCHEMATC diff --git a/pmw-fan.bak b/pmw-fan.bak new file mode 100644 index 0000000..236d199 --- /dev/null +++ b/pmw-fan.bak @@ -0,0 +1,48 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# TC654 +# +DEF TC654 U 0 40 Y Y 1 F N +F0 "U" 300 600 60 H V C CNN +F1 "TC654" 250 -450 60 H V C CNN +F2 "" -300 50 60 H I C CNN +F3 "" -300 50 60 H I C CNN +DRAW +S -400 550 400 -500 0 1 0 f +X Vin 1 -600 0 200 R 50 50 1 1 I +X CF 2 600 200 200 L 50 50 1 1 I +X SCLK 3 -600 300 200 R 50 50 1 1 I +X SDA 4 -600 200 200 R 50 50 1 1 I +X GND 5 -100 750 200 D 50 50 1 1 I +X /FAULT 6 -600 -300 200 R 50 50 1 1 I +X SENSE2 7 -600 -200 200 R 50 50 1 1 I +X SENSE1 8 -600 -100 200 R 50 50 1 1 I +X Vout 9 600 300 200 L 50 50 1 1 I +X Vdd 10 0 750 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# TC654/TC655 +# +DEF TC654/TC655 U 0 40 Y Y 1 F N +F0 "U" 300 600 60 H V C CNN +F1 "TC654/TC655" 0 0 60 H V C CNB +F2 "" -300 50 60 H I C CNN +F3 "" -300 50 60 H I C CNN +DRAW +S -800 1000 800 -1000 0 1 0 f +X Vin 1 -1000 800 200 R 50 50 1 1 I +X CF 2 -1000 400 200 R 50 50 1 1 O +X SCLK 3 -1000 -400 200 R 50 50 1 1 I +X SDA 4 -1000 -800 200 R 50 50 1 1 B +X GND 5 0 -1250 200 U 50 50 1 1 I +X /FAULT 6 1000 -800 200 L 50 50 1 1 O +X SENSE2 7 1000 -400 200 L 50 50 1 1 I +X SENSE1 8 1000 400 200 L 50 50 1 1 I +X Vout 9 1000 800 200 L 50 50 1 1 O +X Vdd 10 0 1200 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/pmw-fan.bck b/pmw-fan.bck new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/pmw-fan.bck @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/pmw-fan.dcm b/pmw-fan.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/pmw-fan.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/pmw-fan.lib b/pmw-fan.lib new file mode 100644 index 0000000..fb54dce --- /dev/null +++ b/pmw-fan.lib @@ -0,0 +1,48 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# TC654 +# +DEF TC654 U 0 40 Y Y 1 F N +F0 "U" 300 600 60 H V C CNN +F1 "TC654" 250 -450 60 H V C CNN +F2 "" -300 50 60 H I C CNN +F3 "" -300 50 60 H I C CNN +DRAW +S -400 550 400 -500 0 1 0 f +X Vin 1 -600 0 200 R 50 50 1 1 I +X CF 2 600 200 200 L 50 50 1 1 I +X SCLK 3 -600 300 200 R 50 50 1 1 I +X SDA 4 -600 200 200 R 50 50 1 1 I +X GND 5 -100 750 200 D 50 50 1 1 I +X /FAULT 6 -600 -300 200 R 50 50 1 1 I +X SENSE2 7 -600 -200 200 R 50 50 1 1 I +X SENSE1 8 -600 -100 200 R 50 50 1 1 I +X Vout 9 600 300 200 L 50 50 1 1 I +X Vdd 10 0 750 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# TC654/TC655 +# +DEF TC654/TC655 U 0 40 Y Y 1 F N +F0 "U" 300 600 60 H V C CNN +F1 "TC654/TC655" 0 0 60 H V C CNB +F2 "" -300 50 60 H I C CNN +F3 "" -300 50 60 H I C CNN +DRAW +S -800 1000 800 -1000 0 1 0 f +X Vin 1 -1000 800 200 R 50 50 1 1 I +X CF 2 -1000 400 200 R 50 50 1 1 O +X SCLK 3 -1000 -400 200 R 50 50 1 1 I +X SDA 4 -1000 -800 200 R 50 50 1 1 B +X GND 5 0 -1200 200 U 50 50 1 1 I +X /FAULT 6 1000 -800 200 L 50 50 1 1 O +X SENSE2 7 1000 -400 200 L 50 50 1 1 I +X SENSE1 8 1000 400 200 L 50 50 1 1 I +X Vout 9 1000 800 200 L 50 50 1 1 O +X Vdd 10 0 1200 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/pmw-fan.pretty/TC654.kicad_mod b/pmw-fan.pretty/TC654.kicad_mod new file mode 100644 index 0000000..44363c2 --- /dev/null +++ b/pmw-fan.pretty/TC654.kicad_mod @@ -0,0 +1,18 @@ +(module TC654 (layer F.Cu) (tedit 59EFD32E) + (fp_text reference REF** (at -6.5 2.5) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value TC654 (at -6.5 1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 10 smd rect (at -1 -4.4) (size 0.3 1.4) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd rect (at -0.5 -4.4) (size 0.3 1.4) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd rect (at 0 -4.4) (size 0.3 1.4) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd rect (at 0.5 -4.4) (size 0.3 1.4) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd rect (at 1 -4.4) (size 0.3 1.4) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd rect (at -1 4.4) (size 0.3 1.4) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd rect (at -0.5 4.4) (size 0.3 1.4) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd rect (at 0 4.4) (size 0.3 1.4) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd rect (at 0.5 4.4) (size 0.3 1.4) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at 1 4.4) (size 0.3 1.4) (layers F.Cu F.Paste F.Mask)) +) diff --git a/readme.md b/readme.md new file mode 100644 index 0000000..9959632 --- /dev/null +++ b/readme.md @@ -0,0 +1,69 @@ +96boards Mezzanine Project Template + +MEZZANINE PROJECT TEMPLATE +=============================================== + +This project provides you with all the base files required for +a mezzanine pcb project. + +In this project, you will find the following: +- COPYING (license) +- meta +- 96boards.pretty (folder containing footprints) ° +- mezza-cache.lib ° (system file, ignore) +- mezza.pro ° +- mezza.sch ° +- mezza.kicad_pcb ° +- fp-lib-table ° + +*Files marked with ° are the KiCad project files* + +####What is this project for? + +This is a project template for anyone who wants to develop a 96Boards +Mezzanine board <a +href="https://www.96boards.org/products/ce/">(compatible with these +boards)</a>. + +This project's schematic only contains the necessary connectors needed +for a mezzanine board. By default it is set up for SMD connectors, but +can easily be changed to through-hole. + +The <em>PCB</em> includes the connectors and mounting holes. The holes +and connectors have been positioned so that the boards are aligned when +mounted. The <em>edge cuts</em> also aligns with the base board. All the +mezzanine board low-speed expansion connector <em>IO</em> is connected +to the header pins. High-speed expansion IO has not yet been added. + +####How to use this project + +This project has been formatted to work with KiCad's "New Project from +Template" tool. You should clone this project into your KiCad templates +directory. For example, on OSX the system template directory is +<em>/Library/Application Support/kicad/template/</em>. A Linux user's +template directory is <em>$HOME/kicad/template/</em> + +Once cloned, you can use the new template by navigating to +File > New Project > New Project From Template. After selecting your +save location, click on <em>System Templates</em> or <em>User +Templates</em> (depending on which file path you previously selected to +clone the project to). Upon validation of the file path, the 96Boards +mezzanine template should appear under the 96Boards logo. Select the +template and you'll be good to go. + +#####Changing to Through Hole Connector +By default, this project loads with the connectors set up as SMD. If you +would prefer to use a through hole instead, follow the instructions on +the schematic to delete a connector and change the footprint on the +other. To change the footprint, right click and select <em>Edit +Component</em>. In the dialog box, click on the footprint section, then +on the right there should now be a button called <em>Assign +Footprint</em>. Click the button, and choose the different footprint +file. Create a new netlist file, open up the PCB editor, and <em>Load +Netlist</em>, ensuring that <em>Exchange Footprint</em> is set to +CHANGE, and <em>Extra Footprints</em> is set to DELETE. Click <em>Read +Current Netlist</em> to load the new connector. Now you should have only +one connector on the board, and when you view in 3D view, there will be +a through hole connector. + +Copyright (c) 2016, Linaro, Inc. |
