diff options
| author | Aaron Li <aaron.li@intel.com> | 2020-09-22 10:28:53 +0800 |
|---|---|---|
| committer | Liming Gao <gaoliming@byosoft.com.cn> | 2020-09-23 09:18:36 +0800 |
| commit | 4efd9ab2cfabdcbd6ca410f870bc889e76f18d85 (patch) | |
| tree | 30be899781d6c90338a1cc0bc6752d7ca6be6fc4 /Silicon | |
| parent | 80ae2271fd9ad1c3b656f4c3e1fbbcbd4e035b7e (diff) | |
Tools/FitGen: Fix microcode alignment support
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2971
This patch is to fix a issue that "-A" option would only support
2^n Byte alignment of microcode.
Signed-off-by: Aaron Li <aaron.li@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Diffstat (limited to 'Silicon')
| -rw-r--r-- | Silicon/Intel/Tools/FitGen/FitGen.c | 8 | ||||
| -rw-r--r-- | Silicon/Intel/Tools/FitGen/FitGen.h | 4 |
2 files changed, 9 insertions, 3 deletions
diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c b/Silicon/Intel/Tools/FitGen/FitGen.c index c4006e69..851d42cb 100644 --- a/Silicon/Intel/Tools/FitGen/FitGen.c +++ b/Silicon/Intel/Tools/FitGen/FitGen.c @@ -363,7 +363,7 @@ Returns: printf ("\tMicrocodeSlotSize - Occupied region size of each Microcode binary.\n");
printf ("\tMicrocodeFfsGuid - Guid of FFS which is used to save Microcode binary");
printf ("\t-NA - No 0x800 aligned Microcode requirement. No -NA means Microcode is aligned with option MicrocodeAlignment value.\n");
- printf ("\tMicrocodeAlignment - HEX value of Microcode alignment. Ignored if \"-NA\" is specified. Default value is 0x800.\n");
+ printf ("\tMicrocodeAlignment - HEX value of Microcode alignment. Ignored if \"-NA\" is specified. Default value is 0x800. The Microcode update data must start at a 16-byte aligned linear address.\n");
printf ("\tRecordType - FIT entry record type. User should ensure it is ordered.\n");
printf ("\tRecordDataAddress - FIT entry record data address.\n");
printf ("\tRecordDataSize - FIT entry record data size.\n");
@@ -1176,7 +1176,11 @@ Returns: // MCU might be put at 2KB alignment, if so, we need to adjust the size as 2KB alignment.
//
if (gFitTableContext.MicrocodeIsAligned) {
- MicrocodeSize = (*(UINT32 *)(MicrocodeBuffer + 32) + (gFitTableContext.MicrocodeAlignValue - 1)) & ~(gFitTableContext.MicrocodeAlignValue - 1);
+ if (gFitTableContext.MicrocodeAlignValue & 0xF) {
+ printf ("-A Parameter incorrect, Microcode data must start at a 16-byte aligned linear address!\n");
+ return 0;
+ }
+ MicrocodeSize = ROUNDUP (*(UINT32 *)(MicrocodeBuffer + 32), gFitTableContext.MicrocodeAlignValue);
} else {
MicrocodeSize = (*(UINT32 *)(MicrocodeBuffer + 32));
}
diff --git a/Silicon/Intel/Tools/FitGen/FitGen.h b/Silicon/Intel/Tools/FitGen/FitGen.h index abad2d87..435fc262 100644 --- a/Silicon/Intel/Tools/FitGen/FitGen.h +++ b/Silicon/Intel/Tools/FitGen/FitGen.h @@ -31,7 +31,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // Utility version information
//
#define UTILITY_MAJOR_VERSION 0
-#define UTILITY_MINOR_VERSION 62
+#define UTILITY_MINOR_VERSION 63
#define UTILITY_DATE __DATE__
//
@@ -45,4 +45,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent (ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1))
;
+#define ROUNDUP(Size, Alignment) (((Size) + (Alignment) - 1) / (Alignment) * (Alignment))
+
#endif
|