diff options
| -rw-r--r--[-rwxr-xr-x] | arch/arm/dts/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/dts/imx8qxp-rom5620-a1-u-boot.dtsi | 249 | ||||
| -rw-r--r-- | arch/arm/dts/imx8qxp-rom5620-a1.dts | 459 | ||||
| -rwxr-xr-x[-rw-r--r--] | board/freescale/imx8qxp_rom5620a1/imx8qxp_rom5620a1.c | 43 | ||||
| -rw-r--r-- | configs/imx8qxp_rom5620a1_2G_defconfig | 14 | ||||
| -rw-r--r-- | configs/imx8qxp_rom5620a1_2G_fspi_defconfig | 14 | ||||
| -rw-r--r-- | include/configs/imx8qxp_rom5620.h | 14 |
7 files changed, 779 insertions, 15 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 60108e30db..8e5806b7d2 100755..100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -777,6 +777,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qxp-17x17-val.dtb \ fsl-imx8dx-17x17-val.dtb \ fsl-imx8qxp-mek-auto.dtb \ + imx8qxp-rom5620-a1.dtb \ fsl-imx8dx-mek.dtb \ fsl-imx8dxl-phantom-mek.dtb \ fsl-imx8dxl-evk.dtb \ diff --git a/arch/arm/dts/imx8qxp-rom5620-a1-u-boot.dtsi b/arch/arm/dts/imx8qxp-rom5620-a1-u-boot.dtsi new file mode 100644 index 0000000000..2cea96ec28 --- /dev/null +++ b/arch/arm/dts/imx8qxp-rom5620-a1-u-boot.dtsi @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/ { + + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; + +}; + +&{/imx8qx-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qxp-mek} { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio6 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio7 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&pd_conn_usb2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2_phy { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-spl; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + mmc-hs400-1_8v; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&i2c1 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx-virt-i2c"; +}; + +&{/i2c@5a810000/i2cswitch@71} { + compatible = "nxp,pca9646", "fsl,imx-virt-i2c-mux"; + virtual-bus-seq = <12>; +}; + +&wu { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8qxp-rom5620-a1.dts b/arch/arm/dts/imx8qxp-rom5620-a1.dts new file mode 100644 index 0000000000..11209506ea --- /dev/null +++ b/arch/arm/dts/imx8qxp-rom5620-a1.dts @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP ROM-5620 A1"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + + aliases { + i2c4 = &bb_i2c1; + i2c5 = &mfi_i2c1; + i2c6 = &i2cexp1_i2c1; + i2c7 = &i2cexp2_i2c1; + gpio8 = &pca9557_a; + gpio9 = &pca9557_b; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3480>; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qxp-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + }; +}; + +&A35_0 { + u-boot,dm-pre-reloc; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + i2cswitch@71 { + compatible = "nxp,pca9646"; + reg = <0x71>; + u-boot,i2c-offset-len = <0>; + #address-cells = <1>; + #size-cells = <0>; + + bb_i2c1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + mfi_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2cexp1_i2c1: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2cexp2_i2c1: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + pca9557_a: gpio@1a { + compatible = "nxp,pca9557"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + }; + pca9557_b: gpio@1d { + compatible = "nxp,pca9557"; + reg = <0x1d>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + + port { + it6263_0_in: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + power-on-gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on = <&epdev_on>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <720>; + hfront-porch = <220>; + hback-porch = <110>; + hsync-len = <40>; + vback-porch = <5>; + vfront-porch = <20>; + vsync-len = <5>; + }; + }; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; diff --git a/board/freescale/imx8qxp_rom5620a1/imx8qxp_rom5620a1.c b/board/freescale/imx8qxp_rom5620a1/imx8qxp_rom5620a1.c index d9c0359731..5b4e56f208 100644..100755 --- a/board/freescale/imx8qxp_rom5620a1/imx8qxp_rom5620a1.c +++ b/board/freescale/imx8qxp_rom5620a1/imx8qxp_rom5620a1.c @@ -331,6 +331,22 @@ int board_usb_cleanup(int index, enum usb_init_type init) } #endif +#define WDOG_TRIG IMX_GPIO_NR(1, 14) + +static iomux_cfg_t wdt_trig[] = { + SC_P_ADC_IN4 | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void setup_iomux_wdt(void) +{ + int value = -1; + + imx8_iomux_setup_multiple_pads(wdt_trig, ARRAY_SIZE(wdt_trig)); + gpio_request(WDOG_TRIG, "wdt_trig"); + gpio_direction_output(WDOG_TRIG, 1); + value = gpio_get_value(WDOG_TRIG); +} + int board_init(void) { board_gpio_init(); @@ -348,6 +364,7 @@ int board_init(void) } #endif + setup_iomux_wdt(); return 0; } @@ -381,6 +398,30 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif +#define DEBUG_UART_SEL IMX_GPIO_NR(0, 27) + +static iomux_cfg_t debug_uart_sel_gpio[] = { + SC_P_SAI0_RXD | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void debug_uart_sel(void) +{ + int value = -1; + + imx8_iomux_setup_multiple_pads(debug_uart_sel_gpio, ARRAY_SIZE(debug_uart_sel_gpio)); + gpio_request(DEBUG_UART_SEL, "debug_uart_sel"); + gpio_direction_input(DEBUG_UART_SEL); + + value = gpio_get_value(DEBUG_UART_SEL); + + /* High: enable debug log. Low: disable debug log. */ + if(value == 0) + { + env_set("console", "disabled"); + env_set("earlycon", "disabled"); + } +} + int board_late_init(void) { char *fdt_file; @@ -425,6 +466,8 @@ int board_late_init(void) board_late_mmc_env_init(); #endif + debug_uart_sel(); + return 0; } diff --git a/configs/imx8qxp_rom5620a1_2G_defconfig b/configs/imx8qxp_rom5620a1_2G_defconfig index d722005448..7ddf37b0b9 100644 --- a/configs/imx8qxp_rom5620a1_2G_defconfig +++ b/configs/imx8qxp_rom5620a1_2G_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x400000 CONFIG_DM_GPIO=y CONFIG_SPL_LOAD_IMX_CONTAINER=y -CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_rom5620a1/uboot-container.cfg" CONFIG_TARGET_IMX8QXP_ROM5620A1_2G=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_EFI_PARTITION=n @@ -25,7 +25,7 @@ CONFIG_SPL=y CONFIG_PANIC_HANG=y CONFIG_SPL_TEXT_BASE=0x100000 CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_rom5620a1/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y CONFIG_SPL_BOARD_INIT=y @@ -52,7 +52,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_DEFAULT_DEVICE_TREE="imx8qxp-rom5620-a1" CONFIG_DEFAULT_FDT_FILE="imx8qxp-rom5620-a1.dtb" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -114,6 +114,8 @@ CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_BAR=y CONFIG_CMD_SF=y CONFIG_SF_DEFAULT_BUS=0 CONFIG_SF_DEFAULT_CS=0 @@ -126,15 +128,15 @@ CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB=y -CONFIG_USB_TCPC=y +# CONFIG_USB_TCPC is not set CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_USB_CDNS3=y -CONFIG_USB_CDNS3_GADGET=y +# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS3_GADGET is not set CONFIG_USB_GADGET_DUALSPEED=y CONFIG_CDNS3_USB_PHY=y CONFIG_PHY=y diff --git a/configs/imx8qxp_rom5620a1_2G_fspi_defconfig b/configs/imx8qxp_rom5620a1_2G_fspi_defconfig index b6b0175d00..a20b57b13d 100644 --- a/configs/imx8qxp_rom5620a1_2G_fspi_defconfig +++ b/configs/imx8qxp_rom5620a1_2G_fspi_defconfig @@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x400000 CONFIG_DM_GPIO=y CONFIG_SPL_LOAD_IMX_CONTAINER=y -CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_rom5620a1/uboot-container.cfg" CONFIG_TARGET_IMX8QXP_ROM5620A1_2G=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y @@ -29,7 +29,7 @@ CONFIG_SPL=y CONFIG_PANIC_HANG=y CONFIG_SPL_TEXT_BASE=0x100000 CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_rom5620a1/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y CONFIG_SPL_BOARD_INIT=y @@ -56,7 +56,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_DEFAULT_DEVICE_TREE="imx8qxp-rom5620-a1" CONFIG_DEFAULT_FDT_FILE="imx8qxp-rom5620-a1.dtb" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -116,6 +116,8 @@ CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_BAR=y CONFIG_CMD_SF=y CONFIG_SF_DEFAULT_BUS=0 CONFIG_SF_DEFAULT_CS=0 @@ -128,15 +130,15 @@ CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB=y -CONFIG_USB_TCPC=y +# CONFIG_USB_TCPC is not set CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_USB_CDNS3=y -CONFIG_USB_CDNS3_GADGET=y +# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS3_GADGET is not set CONFIG_USB_GADGET_DUALSPEED=y CONFIG_CDNS3_USB_PHY=y CONFIG_PHY=y diff --git a/include/configs/imx8qxp_rom5620.h b/include/configs/imx8qxp_rom5620.h index ee8d68b175..40e172664a 100644 --- a/include/configs/imx8qxp_rom5620.h +++ b/include/configs/imx8qxp_rom5620.h @@ -11,6 +11,9 @@ #include "imx_env.h" +#define CONFIG_ADVANTECH_MX8 +#define CONFIG_HAS_ETH1 + #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_MAX_SIZE (192 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) @@ -153,6 +156,11 @@ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "lvds_single0=setenv fdt_file imx8qxp-rom5620-a1-lvds0-auo.dtb; boot\0" \ + "lvds_single1=setenv fdt_file imx8qxp-rom5620-a1-lvds1-auo.dtb; boot\0" \ + "lvds_chimei=setenv fdt_file imx8qxp-rom5620-a1-lvds-chimei.dtb; boot\0" \ + "lvds_dual=setenv fdt_file imx8qxp-rom5620-a1-lvds-dual.dtb; boot\0" \ + "hdmi_bridge=setenv fdt_file imx8qxp-rom5620-a1-hdmi-bridge.dtb; boot\0" \ "auth_os=auth_cntr ${cntr_addr}\0" \ "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ "mmcboot=echo Booting from mmc ...; " \ @@ -288,7 +296,7 @@ /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ #ifdef CONFIG_FSL_FSPI -#define FSL_FSPI_FLASH_SIZE SZ_64M +#define FSL_FSPI_FLASH_SIZE SZ_8M #define FSL_FSPI_FLASH_NUM 1 #define FSPI0_BASE_ADDR 0x5d120000 #define FSPI0_AMBA_BASE 0 @@ -323,11 +331,11 @@ #if (CONFIG_FEC_ENET_DEV == 0) #define IMX_FEC_BASE 0x5B040000 -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_FEC_MXC_PHYADDR 0x4 #define CONFIG_ETHPRIME "eth0" #elif (CONFIG_FEC_ENET_DEV == 1) #define IMX_FEC_BASE 0x5B050000 -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_MXC_PHYADDR 0x6 #define CONFIG_ETHPRIME "eth1" #endif |