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authorAlistair Delva <adelva@google.com>2022-09-26 11:39:09 -0700
committerAlistair Delva <adelva@google.com>2022-09-26 11:55:22 -0700
commit066925bdea42277bc303867dbf7b7f38161dec2a (patch)
treef9dce036525e49bd1eb7de21c149f74992726b47
parent50d8bba1441958300c843b098e0991739cec3c9a (diff)
ANDROID: Re-enable check_member
This workaround is no longer required in newer U-Boot/Clang combinations. Drop it. Signed-off-by: Alistair Delva <adelva@google.com> Change-Id: I618f15b6f50f174d5cc0b1bcd240f55dcbd5ad9f
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_rk3328.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_rk3399.h4
-rw-r--r--arch/arm/include/asm/arch-rockchip/edp_rk3288.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/gpio.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/grf_rk3399.h6
-rw-r--r--arch/arm/include/asm/arch-rockchip/pmu_rk3399.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/vop_rk3288.h2
-rw-r--r--arch/x86/include/asm/fast_spi.h2
8 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
index 8143ae2c683..226744d67d9 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
@@ -41,7 +41,7 @@ struct rk3328_cru {
u32 emmc_con[2];
u32 sdmmc_ext_con[2];
};
-//check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
+check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24 * MHz)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
index 467c502dfd0..d941a129f3e 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -29,7 +29,7 @@ struct rk3399_pmucru {
u32 reserved5[2];
u32 pmucru_gatedis_con[2];
};
-//check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
+check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
struct rockchip_cru {
u32 apll_l_con[6];
@@ -63,7 +63,7 @@ struct rockchip_cru {
u32 sdio0_con[2];
u32 sdio1_con[2];
};
-//check_member(rockchip_cru, sdio1_con[1], 0x594);
+check_member(rockchip_cru, sdio1_con[1], 0x594);
#define KHz 1000
#define OSC_HZ (24*MHz)
#define LPLL_HZ (600*MHz)
diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
index 5aa8b0a3a23..9559813e520 100644
--- a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
@@ -153,7 +153,7 @@ struct rk3288_edp {
u8 res30[0x10];
u32 pll_reg_5;
};
-//check_member(rk3288_edp, pll_reg_5, 0xa00);
+check_member(rk3288_edp, pll_reg_5, 0xa00);
/* func_en_1 */
#define VID_CAP_FUNC_EN_N (0x1 << 6)
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
index 6329b0323db..1aaec5faecc 100644
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -22,7 +22,7 @@ struct rockchip_gpio_regs {
u32 reserved1[(0x60 - 0x54) / 4];
u32 ls_sync;
};
-//check_member(rockchip_gpio_regs, ls_sync, 0x60);
+check_member(rockchip_gpio_regs, ls_sync, 0x60);
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index 892bd94fbd8..dd89cd20505 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -190,7 +190,7 @@ struct rk3399_grf_regs {
u32 reserved34;
u32 emmcphy_status;
};
-//check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
+check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
struct rk3399_pmugrf_regs {
union {
@@ -267,7 +267,7 @@ struct rk3399_pmugrf_regs {
u32 os_reg2;
u32 os_reg3;
};
-//check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
+check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
struct rk3399_pmusgrf_regs {
u32 ddr_rgn_con[35];
@@ -320,7 +320,7 @@ struct rk3399_pmusgrf_regs {
u32 slv_secure_con3;
u32 slv_secure_con4;
};
-//check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
+check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
enum {
/* GRF_GPIO2A_IOMUX */
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
index b7a0f92cfd3..f1096dccced 100644
--- a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
@@ -67,6 +67,6 @@ struct rk3399_pmu_regs {
u32 pmu_sys_reg_reg3;
};
-//check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc);
+check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc);
#endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
index 8b122876ef6..49a71414379 100644
--- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -68,7 +68,7 @@ struct rk3288_vop {
u32 dsp_vs_st_end_f1;
u32 dsp_vact_st_end_f1;
};
-//check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c);
+check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c);
enum rockchip_fb_data_format_t {
ARGB8888 = 0,
diff --git a/arch/x86/include/asm/fast_spi.h b/arch/x86/include/asm/fast_spi.h
index fd7f6d57b08..998847b82c6 100644
--- a/arch/x86/include/asm/fast_spi.h
+++ b/arch/x86/include/asm/fast_spi.h
@@ -37,7 +37,7 @@ struct fast_spi_regs {
u32 ptinx;
u32 ptdata;
};
-// check_member(fast_spi_regs, ptdata, 0xd0);
+check_member(fast_spi_regs, ptdata, 0xd0);
/* Bit definitions for BFPREG (0x00) register */
#define SPIBAR_BFPREG_PRB_MASK 0x7fff