add register state tests

4 files changed, 285 insertions, 0 deletions

diff --git a/Makefile b/Makefile
index 0d32bd1..2741488 100644
--- a/Makefile
+++ b/Makefile
@@ -20,6 +20,8 @@ all: test5-kern.bin
 all: test6-kern.bin
 all: test7-kern.bin
 all: test8-kern.bin
+all: test9-kern.bin
+all: test10-kern.bin
 
 test1-kern.elf: cortexm.ld common.ld setup.o init-m.o test1.o
 test2-kern.elf: cortexm.ld common.ld setup.o init-m.o test2.o
@@ -29,6 +31,8 @@ test5-kern.elf: cortexm.ld common.ld setup.o init-m.o test5.o
 test6-kern.elf: cortexm.ld common.ld setup.o init-m.o test6.o
 test7-kern.elf: cortexm.ld common.ld setup.o init-m.o test7.o
 test8-kern.elf: cortexm.ld common.ld setup.o init-m.o test8.o inst_skip.o
+test9-kern.elf: cortexm.ld common.ld setup.o init-m-test9.o test9.o
+test10-kern.elf:cortexm.ld common.ld setup.o init-m.o test10.o
 
 clean:
 	rm -f *.o *.elf *.map *.bin *.img
diff --git a/init-m-test9.S b/init-m-test9.S
new file mode 100644
index 0000000..049464b
--- /dev/null
+++ b/init-m-test9.S
@@ -0,0 +1,131 @@
+.thumb
+.syntax unified
+
+.section .text.start
+.global _boot_reset
+.align 7
+_boot_reset:
+.word _main_stack_top
+.word _start /* reset */
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+.word _vec_stuck
+
+.section .text
+
+.global _start
+.thumb_func
+_start:
+  ldr r3, =early_state
+
+  mov r0, lr
+  str r0, [r3], #4
+
+  mrs r0, XPSR
+  str r0, [r3], #4
+
+  mrs r0, PRIMASK
+  str r0, [r3], #4
+
+  mrs r0, FAULTMASK
+  str r0, [r3], #4
+
+  mrs r0, BASEPRI
+  str r0, [r3], #4
+
+  mrs r0, CONTROL
+  str r0, [r3], #4
+
+  ldr r2, =0xe000e000
+
+  ldr r0, [r2, #0xd00] /* CPUID */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0xd04] /* ICSR */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0xd04] /* VTOR */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0xd0c] /* AIRCR */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0xd10] /* SCR */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0xd14] /* CCR */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0xd18] /* SHPR1 */
+  str r0, [r3], #4
+  ldr r0, [r2, #0xd1c] /* SHPR2 */
+  str r0, [r3], #4
+  ldr r0, [r2, #0xd20] /* SHPR3 */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0xd24] /* SHCSR */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0x10] /* SYST_CSR */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0x4] /* ICTR */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0xd90] /* MPU_TYPE */
+  str r0, [r3], #4
+
+  ldr r0, [r2, #0xd94] /* MPU_CTRL */
+  str r0, [r3], #4
+
+  ldr r0, =0xdeadbeaf
+  str r0, [r3], #4
+
+  blx board_setup
+  blx main
+  /* fall through to abort() */
+
+.global abort
+.thumb_func
+abort:
+  ldr sp, =_main_stack_top
+
+  ldr r0, =0x05fa0004 /* reset request */
+  ldr r1, =0xe000ed0c /* AIRCR */
+  str r0, [r1]
+  dsb
+
+_stuck:
+  b _stuck
+
+.thumb_func
+_vec_stuck:
+  mov r0, #'S'
+  ldr r1, =0x4000c000
+  str r0, [r1]
+  bl abort
+
+.section .rodata
+.global hexchars
+hexchars:
+.string "0123456789abcdef"
+
+.section .bss
+.align 4
+
+.global _main_stack_bot
+_main_stack_bot:
+.skip 0x400
+.global _main_stack_top
+_main_stack_top:
diff --git a/test10.c b/test10.c
new file mode 100644
index 0000000..9f585c1
--- /dev/null
+++ b/test10.c
@@ -0,0 +1,80 @@
+/* Test exception handling registers
+ */
+#include "armv7m.h"
+
+static
+void test_equal(const char *msg, uint32_t lhs, uint32_t rhs)
+{
+    puts(lhs==rhs ? "ok - " : "fail - ");
+    puthex(lhs);
+    puts(" == ");
+    puthex(rhs);
+    puts(" # ");
+    puts(msg);
+    putc('\n');
+}
+
+static
+volatile unsigned test;
+
+static
+void pendsv(void)
+{
+    switch(test) {
+    case 2:
+        puts("3. In PendSV\n");
+        /* RETTOBASE not set */
+        test_equal("ICSR ", 0x0000000e, in32(SCB(0xd04)));
+        test_equal("SHCSR", 0x00000480, in32(SCB(0xd24)));
+        test = 3;
+        break;
+    default:
+        puts("Unexpected PendSV\n");
+        abort();
+    }
+}
+
+static
+void svc(void)
+{
+    switch(test) {
+    case 1:
+        puts("2. In SVC\n");
+        test = 2;
+        /* RETTOBASE set */
+        test_equal("ICSR ", 0x0000080b, in32(SCB(0xd04)));
+        test_equal("SHCSR", 0x00000080, in32(SCB(0xd24)));
+        rmw(32, SCB(0xd04), 1<<28, 1<<28); /* Pend PendSV */
+        puts("4. Back in SVC\n");
+        test_equal("test ", 3, test);
+        test = 4;
+        break;
+    default:
+        puts("Unexpected SVC\n");
+        abort();
+    }
+}
+
+void main(void)
+{
+    run_table.svc = &svc;
+    run_table.pendsv = &pendsv;
+
+    rmw(32,SCB(0xd0c),0x700, PRIGROUP<<8);
+    out32(SCB(0xd1c), PRIO(2,0)<<24); /* SVC prio 2 */
+    out32(SCB(0xd20), PRIO(1,0)<<16); /* PendSV prio 1 */
+
+    test = 1;
+    /* RETTOBASE not set */
+    test_equal("ICSR ", 0x00000000, in32(SCB(0xd04)));
+    test_equal("SHCSR", 0x00000000, in32(SCB(0xd24)));
+    puts("1. Call SVC\n");
+    SVC(42);
+    puts("5. Back in main\n");
+    test_equal("test ", 4, test);
+    test = 5;
+    test_equal("ICSR ", 0x00000000, in32(SCB(0xd04)));
+    test_equal("SHCSR", 0x00000000, in32(SCB(0xd24)));
+
+    puts("Done\n");
+}
diff --git a/test9.c b/test9.c
new file mode 100644
index 0000000..3b03d60
--- /dev/null
+++ b/test9.c
@@ -0,0 +1,70 @@
+/* Capture initial register states
+ */
+#include "armv7m.h"
+
+static
+void test_equal(const char *msg, uint32_t lhs, uint32_t rhs)
+{
+    puts(lhs==rhs ? "ok - " : "fail - ");
+    puthex(lhs);
+    puts(" == ");
+    puthex(rhs);
+    puts(" # ");
+    puts(msg);
+    putc('\n');
+}
+
+struct early_state_t {
+    uint32_t LR;
+    uint32_t XPSR;
+    uint32_t PRIMASK;
+    uint32_t FAULTMASK;
+    uint32_t BASEPRI;
+    uint32_t CONTROL;
+    uint32_t cpuid;
+    uint32_t icsr;
+    uint32_t vtor;
+    uint32_t aircr;
+    uint32_t scr;
+    uint32_t ccr;
+    uint32_t shpr[3];
+    uint32_t shcsr;
+    uint32_t syst_csr;
+    uint32_t ictr;
+    uint32_t mpu_type;
+    uint32_t mpu_ctrl;
+    uint32_t marker;
+} early_state;
+
+void main(void)
+{
+#define TEST(FLD, VAL) test_equal(#FLD, early_state.FLD, VAL)
+    TEST(marker, 0xdeadbeaf); /* check consistency w/ init-m-test9.S */
+    TEST(LR, 0xffffffff);
+    TEST(XPSR, 0);
+    TEST(PRIMASK, 0);
+    TEST(FAULTMASK, 0);
+    TEST(BASEPRI, 0);
+    TEST(CONTROL, 0);
+    puts("# cpuid ");
+    puthex(early_state.cpuid);
+    putc('\n');
+    TEST(icsr, 0);
+    TEST(vtor, 0);
+    TEST(aircr, 0xfa050000);
+    TEST(scr, 0);
+    TEST(ccr, 1<<9); /* STKALIGN */
+    TEST(shpr[0], 0);
+    TEST(shpr[1], 0);
+    TEST(shpr[2], 0);
+    TEST(shcsr, 0);
+    TEST(syst_csr, 0);
+    puts("# ictr ");
+    puthex(early_state.ictr);
+    putc('\n');
+    puts("# mpu_type ");
+    puthex(early_state.mpu_type);
+    putc('\n');
+    TEST(mpu_ctrl, 0);
+    puts("Done\n");
+}