test9: Correct expected SYST_CSR value

In QEMU commit a40e10f1dc3e0fedd we fixed a bug in our systick timer
implementation where we always implemented a 1MHz reference clock,
whether the board had a reference clock or not. For the Stellaris
board which we run these test cases on, there is no reference clock;
the reset value of SYST_CSR has therefore changed to its correct
value of 4 (with the CLKSOURCE bit set to indicate that the systick
clock is running on the CPU clock).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/test9.c b/test9.c
index d3d8b09..4796de0 100644
--- a/test9.c
+++ b/test9.c
@@ -59,7 +59,7 @@ void main(void)
     TEST(shpr[1], 0);
     TEST(shpr[2], 0);
     TEST(shcsr, 0);
-    TEST(syst_csr, 0);
+    TEST(syst_csr, 4);
     puts("# ictr ");
     puthex(early_state.ictr);
     putc('\n');