diff options
| author | Thomas Huth <thuth@redhat.com> | 2023-09-14 13:33:07 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-09-18 13:24:07 +0100 |
| commit | 372a5db529d2188ee0691c7be6fc65ff11bc3657 (patch) | |
| tree | 21b22fa022e29578e91f2977f93423731d0f3a0d | |
| parent | f4d6a335b092afd61c4f04caf22e4e730b6edeb3 (diff) | |
s390x: Add simple s390x.risu file
This only adds a limited set of s390x instructions for initial testing.
More instructions will be added later.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230914113311.379537-4-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | s390x.risu | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/s390x.risu b/s390x.risu new file mode 100644 index 0000000..1661be6 --- /dev/null +++ b/s390x.risu @@ -0,0 +1,81 @@ +############################################################################### +# Copyright 2023 Red Hat Inc. +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Thomas Huth - initial implementation +############################################################################### + +.mode s390x + +# format:RR Add (register + register, 32 bit) +AR Z 00011010 r1:4 r2:4 + +# format:RRE Add (register + register, 64 bit) +AGR Z 10111001 00001000 00000000 r1:4 r2:4 + +# format:RRE Add (register + register, 32 bit to 64 bit) +AGFR Z 10111001 00011000 00000000 r1:4 r2:4 + +# format:RRF-a Add (three registers, 32 bit) +ARK STFLE45 10111001 11111000 r3:4 0000 r1:4 r2:4 + +# format:RRF-a Add (three registers, 64 bit) +AGRK STFLE45 10111001 11101000 r3:4 0000 r1:4 r2:4 + + +# format:RRE Add Halfword Immediate (32 bit) +AHI Z 10100111 r1:4 1010 i2:16 + +# format:RI Add Halfword Immediate (64 bit) +AGHI Z 10100111 r1:4 1011 i2:16 + + +# format:RR Add Logical (32 bit) +ALR Z 00011110 r1:4 r2:4 + +# format:RRE Add Logical (64 bit) +ALGR Z 10111001 00001010 00000000 r1:4 r2:4 + +# format:RRE Add Logical (32 bit to 64 bit) +ALGFR Z 10111001 00011010 00000000 r1:4 r2:4 + + +# format:RRF-c Population Count +POPCNT STFLE45 10111001 11100001 m3:4 0000 r1:4 r2:4 + + +###### Binary floating point instructions ###### + +# format:RRE ADD (short BFP) +AEBR BFP 10110011 00001010 00000000 r1:4 r2:4 + +# format:RRE ADD (long BFP) +ADBR BFP 10110011 00011010 00000000 r1:4 r2:4 + +# format:RRE ADD (extended BFP) +AXBR BFP 10110011 01001010 00000000 r1:4 r2:4 + + +# format:RRE COMPARE (short BFP) +CEBR BFP 10110011 00001001 00000000 r1:4 r2:4 + +# format:RRE COMPARE (long BFP) +CDBR BFP 10110011 00011001 00000000 r1:4 r2:4 + +# format:RRE COMPARE (extended BFP) +CXBR BFP 10110011 01001001 00000000 r1:4 r2:4 + + +# format:RRF-e LOAD FP INTEGER (short BFP) +FIEBRA BFP 10110011 01010111 m3:4 m4:4 r1:4 r2:4 + +# format:RRF-e LOAD FP INTEGER (long BFP) +FIDBRA BFP 10110011 01011111 m3:4 m4:4 r1:4 r2:4 + +# format:RRF-e LOAD FP INTEGER (extended BFP) +FIXBRA BFP 10110011 01000111 m3:4 m4:4 r1:4 r2:4 + |