arm.risu: add patterns for Neon "2 register misc" forms

1 files changed, 39 insertions, 54 deletions

diff --git a/arm.risu b/arm.risu
index 498a2e4..8d659e2 100644
--- a/arm.risu
+++ b/arm.risu
@@ -25,9 +25,9 @@ VMUL A2 cond:4 11100 d 10 vn:4 vd:4 101 sz n 0 m 0 vm:4
 VDIV A1 cond:4 11101 d 00 vn:4 vd:4 101 sz n 0 m 0 vm:4
 
 ########### VCVT #########################################
-# These patterns should cover all the VCVT* instructions
-# in their ARM encodings. NB that the patterns for half
-# precision conversions are commented out and untested.
+# These patterns should cover all the non-Neon VCVT*
+# instructions in their ARM encodings. Neon VCVT* are
+# in the Neon data processing insns sections later.
 ##########################################################
 
 # VCVT between fp and int: split in two because opc2 must be 000 or 10x (A8.6.295)
@@ -45,23 +45,9 @@ VCVT_d A1 cond:4 11101 d 111 op 1 u vd:4 101 sf 0 1 i 0 0 imm:3
 # sx==0, bit 3 == 1, bits 2..0 and 5 0
 VCVT_e A1 cond:4 11101 d 111 op 1 u vd:4 101 sf 0 1 0 0 1000
 
-# VCVT fp to integer, neon (A8.6.294)
-# Split to not generate the Q=1 Vd<0> or Vm<0>=1 cases
-# (they UNDEF but qemu gets this wrong for just about all neon)
-VCVT_neon_q0 A1 1111 0011 1 d 11 10 11 vd:4 0 11 op:2 0 m 0 vm:4
-VCVT_neon_q1 A1 1111 0011 1 d 11 10 11 vd:3 0 0 11 op:2 1 m 0 vm:3 0
-
 # VCVT between double and single (A8.6.298)
 VCVT_298 A1 cond:4 1110 1 d 11 0111 vd:4 101 sz 1 1 m 0 vm:4
 
-# These three patterns deal with conversions to and from
-# half-precision (16 bit) floats. A8 doesn't have these; you'll
-# need an A9 as the master to use these.
-
-# we don't generate the sz!=01 UNDEF cases
-# two patterns to avoid the op==1 Vd<0>==1 and op==0 Vm<0>==1 UNDEF cases
-VCVT_299_a A1 1111 0011 1 d 11 01 10 vd:4 011 0 0 0 m 0 vm:3 0
-VCVT_299_b A1 1111 0011 1 d 11 01 10 vd:3 0 011 1 0 0 m 0 vm:4
 # VCVTB, VCVTT (A8.6.300)
 VCTV_B_TT A1 cond:4 1110 1 d 11 001 op vd:4 101 0 t 1 m 0 vm:4
 
@@ -126,32 +112,6 @@ PLDW_reg A1 1111 0111 u 001 rn:4 1111 imm:5 type:2 0 rm:4
 # no overlap with PLD_imm because rn can't be 15
 PLD_lit A1 1111 0101 u 101 1111 1111 imm:12
 
-
-# VQMOVN, VQMOVUN
-# includes VMOVN when op=00
-VQMOVN A1 1111 0011 1 d 11 sz:2 10 vd:4 0010 op:2 m 0 vm:3 0 { ($sz != 3); }
-
-# VUZP : Q=0 case (sz 11 or 10 undefs; d == m is UNKNOWN results)
-VUZP_a A1 1111 0011 1 d 11 0 sz 10 vd:4 0001 0 0 m 0 vm:4 { ($d != $m) || ($vd != $vm); }
-# Q=1 case (sz 11, vd<0> or vm<0> 1 undefs; d == m is UNKNOWN results)
-VUZP_b A1 1111 0011 1 d 11 sz:2 10 vd:3 0 0001 0 1 m 0 vm:3 0 { ($sz != 3) && (($d != $m) || ($vd != $vm)); }
-
-# VZIP : Q=0 case (sz 11 or 10 undefs; d == m is UNKNOWN results)
-VZIP_a A1 1111 0011 1 d 11 0 sz 10 vd:4 0001 1 0 m 0 vm:4 { ($d != $m) || ($vd != $vm); }
-# Q=1 case (sz 11, vd<0> or vm<0> 1 undefs; d == m is UNKNOWN results)
-VZIP_b A1 1111 0011 1 d 11 sz:2 10 vd:3 0 0001 1 1 m 0 vm:3 0 { ($sz != 3) && (($d != $m) || ($vd != $vm)); }
-
-# Q=0
-VRECPE_a A1 1111 0011 1 d 11 10 11 vd:4 010 f 0 0 m 0 vm:4
-# Q=1
-VRECPE_b A1 1111 0011 1 d 11 10 11 vd:3 0 010 f 0 1 m 0 vm:3 0
-
-# Q=0
-VRSQRTE_a A1 1111 0011 1 d 11 10 11 vd:4 010 f 1 0 m 0 vm:4
-# Q=1
-VRSQRTE_b A1 1111 0011 1 d 11 10 11 vd:3 0 010 f 1 1 m 0 vm:3 0
-
-
 # Unsigned saturating add/subtract
 # UQADD16, UQSUB16, UQADD8, UQSUB8
 UQADD16 A1 cond:4 01100110 rn:4 rd:4 1111 0001 rm:4
@@ -226,17 +186,6 @@ VCGE A2a 1111 0011 0 d 0 0 vn:4 vd:4 1110 n 0 m 0 vm:4
 VCGE A2b 1111 0011 0 d 0 0 vn:3 0 vd:3 0 1110 n 1 m 0 vm:3 0
 VCGT A2a 1111 0011 0 d 1 0 vn:4 vd:4 1110 n 0 m 0 vm:4
 VCGT A2b 1111 0011 0 d 1 0 vn:3 0 vd:3 0 1110 n 1 m 0 vm:3 0
-# VCEQ, VCGE, VCGT, VCLT, VCLE with imm 0 -- F=1 forms only!
-VCEQ0 A1a 1111 0011 1 d 11 10 0 1 vd:4 0 1 010 0 m 0 vm:4
-VCEQ0 A1b 1111 0011 1 d 11 10 0 1 vd:3 0 0 1 010 1 m 0 vm:3 0
-VCGE0 A1a 1111 0011 1 d 11 10 0 1 vd:4 0 1 001 0 m 0 vm:4
-VCGE0 A1b 1111 0011 1 d 11 10 0 1 vd:3 0 0 1 001 1 m 0 vm:3 0
-VCGT0 A1a 1111 0011 1 d 11 10 0 1 vd:4 0 1 000 0 m 0 vm:4
-VCGT0 A1b 1111 0011 1 d 11 10 0 1 vd:3 0 0 1 000 1 m 0 vm:3 0
-VCLE0 A1a 1111 0011 1 d 11 10 0 1 vd:4 0 1 011 0 m 0 vm:4
-VCLE0 A1b 1111 0011 1 d 11 10 0 1 vd:3 0 0 1 011 1 m 0 vm:3 0
-VCLT0 A1a 1111 0011 1 d 11 10 0 1 vd:4 0 1 100 0 m 0 vm:4
-VCLT0 A1b 1111 0011 1 d 11 10 0 1 vd:3 0 0 1 100 1 m 0 vm:3 0
 
 # VACGE, VACGT
 VACG A1a 1111 0011 0 d op 0 vn:4 vd:4 1110 n 0 m 1 vm:4
@@ -725,3 +674,39 @@ VQDMULL_scalar A2 1111 0010 1 d sz:2 vn:4 vd:4 1011 n 1 m 0 vm:4 { $sz != 3; }
 VQDMULH_scalar A2 1111 001 q 1 d sz:2 vn:4 vd:4 1100 n 1 m 0 vm:4 { $sz != 3; }
 VQRDMULH_scalar A2 1111 001 q 1 d sz:2 vn:4 vd:4 1101 n 1 m 0 vm:4 { $sz != 3; }
 
+########### Neon 2 regs miscellaneous #####################
+# Instructions from the Neon "2 regs miscellaneous" space
+# (table A7-13 in DDI0406B)
+# UNDEF cases included.
+###########################################################
+VREV A1 1111 0011 1 d 11 sz:2 00 vd:4 000 op:2 q m 0 vm:4
+VPADDL A1 1111 0011 1 d 11 sz:2 00 vd:4 0010 op q m 0 vm:4
+VCLS A1 1111 0011 1 d 11 sz:2 00 vd:4 0 1000 q m 0 vm:4
+VCLZ A1 1111 0011 1 d 11 sz:2 00 vd:4 0 1001 q m 0 vm:4
+VCNT A1 1111 0011 1 d 11 sz:2 00 vd:4 0 1010 q m 0 vm:4
+VMVN A1 1111 0011 1 d 11 sz:2 00 vd:4 0 1011 q m 0 vm:4
+VPADAL A1 1111 0011 1 d 11 sz:2 00 vd:4 0110 op q m 0 vm:4
+VQABS A1 1111 0011 1 d 11 sz:2 00 vd:4 0111 0 q m 0 vm:4
+VQNEG A1 1111 0011 1 d 11 sz:2 00 vd:4 0111 1 q m 0 vm:4
+VCGT0 A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 000 q m 0 vm:4
+VCGE0 A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 001 q m 0 vm:4
+VCEQ0 A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 010 q m 0 vm:4
+VCLE0 A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 011 q m 0 vm:4
+VCLT0 A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 100 q m 0 vm:4
+VABS A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 110 q m 0 vm:4
+VNEG A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 111 q m 0 vm:4
+VSWP A1 1111 0011 1 d 11 sz:2 10 vd:4 00000 q m 0 vm:4
+VTRN A1 1111 0011 1 d 11 sz:2 10 vd:4 00001 q m 0 vm:4
+# d == m gives UNKNOWN results, so avoid it
+VUZP A1 1111 0011 1 d 11 sz:2 10 vd:4 00010 q m 0 vm:4 { ($d != $m) || ($vd != $vm); }
+VZIP A1 1111 0011 1 d 11 sz:2 10 vd:4 00011 q m 0 vm:4 { ($d != $m) || ($vd != $vm); }
+# includes VMOVN, VQMOVUN
+VQMOVN A1 1111 0011 1 d 11 sz:2 10 vd:4 0010 op:2 m 0 vm:4
+VSHLL A2 1111 0011 1 d 11 sz:2 10 vd:4 0011 0 0 m 0 vm:4
+# float-halfprec (A8.6.299)
+# NB that half-precision needs at least an A9; A8 doesn't have it
+VCVT_half A1 1111 0011 1 d 11 sz:2 10 vd:4 011 op 0 0 m 0 vm:4
+VRECPE A1 1111 0011 1 d 11 sz:2 11 vd:4 010 f 0 q m 0 vm:4
+VRSQRTE A1 1111 0011 1 d 11 sz:2 11 vd:4 010 f 1 q m 0 vm:4
+# float to int, neon versions (A8.6.294)
+VCVT_neon A1 1111 0011 1 d 11 sz:2 11 vd:4 0 11 op:2 q m 0 vm:4