Add patterns for VST* multiple structures.

Add patterns for VST* multiple structures. This completes the
coverage of the neon element load/store space.

1 files changed, 71 insertions, 2 deletions

diff --git a/arm.risu b/arm.risu
index 5ab1caf..8df60a6 100644
--- a/arm.risu
+++ b/arm.risu
@@ -378,8 +378,11 @@ VRECPS A1a 1111 0010 0 d 0 0 vn:4 vd:4 1111 n 0 m 1 vm:4
 VRECPS A1b 1111 0010 0 d 0 0 vn:3 0 vd:3 0 1111 n 1 m 1 vm:3 0
 
 ########### Neon loads and stores #########################
-# This set of patterns isn't complete yet...
-##########################################################
+# These patterns cover all the Neon element/structure
+# load store insns, ie the whole of the space in section
+# A7.7 of the ARM ARM DDI0406B, including the UNDEF space.
+# This is all of VLD1,VLD2,VLD3,VLD4,VST1,VST2,VST3,VST4.
+###########################################################
 
 # VLD*, single element to all lanes
 
@@ -631,6 +634,72 @@ VLDn_m A1b 1111 0100 0 d 10 rn:4 vd:4 10 type:2 sz:2 11 xm:4
 VLDn_m A1c 1111 0100 0 d 10 rn:4 vd:4 type:2 0 type0 11 align:2 xm:4
 VLDn_m A1d 1111 0100 0 d 10 rn:4 vd:4 0011 11 align:2 xm:4
 
+# VST*, multiple elements
+
+# We separate these out by 'type' field
+# type 0111: VST1 regs=1
+VST1_m A1a 1111 0100 0 d 00 rn:4 vd:4 0111 sz:2 0 align xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 1) <= 32); } \
+   !memory { align(8); reg($rn); }
+# type 1010: VST1 regs=2
+VST1_m A1b 1111 0100 0 d 00 rn:4 vd:4 1010 sz:2 align:2 xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 2) <= 32) && ($align != 3); } \
+   !memory { align(16); reg($rn); }
+# type 0110: VST1 regs=3
+VST1_m A1c 1111 0100 0 d 00 rn:4 vd:4 0110 sz:2 0 align xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 3) <= 32); } \
+   !memory { align(8); reg($rn); }
+# type 0010: VST1 regs=4
+VST1_m A1d 1111 0100 0 d 00 rn:4 vd:4 0010 sz:2 align:2 xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 4) <= 32); } \
+   !memory { align(32); reg($rn); }
+
+# type 1000: VST2 regs=1 inc=1
+VST2_m A1a 1111 0100 0 d 00 rn:4 vd:4 1000 sz:2 align:2 xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 1 + 1) <= 32) && ($align != 3) && ($sz != 3); } \
+   !memory { align(16); reg($rn); }
+# type 1001: VST2 regs=1 inc=2
+VST2_m A1b 1111 0100 0 d 00 rn:4 vd:4 1001 sz:2 align:2 xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 2 + 1) <= 32) && ($align != 3) && ($sz != 3); } \
+   !memory { align(16); reg($rn); }
+# type 0011: VST2 regs=2 inc=2
+VST2_m A1c 1111 0100 0 d 00 rn:4 vd:4 0011 sz:2 align:2 xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 2 + 2) <= 32) && ($sz != 3); } \
+   !memory { align(32); reg($rn); }
+
+# type 0100: VST3 inc=1
+VST3_m A1a 1111 0100 0 d 00 rn:4 vd:4 0100 sz:2 0 align xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 2) <= 31) && ($sz != 3); } \
+   !memory { align(8); reg($rn); }
+# type 0101: VST3 inc=2
+VST3_m A1b 1111 0100 0 d 00 rn:4 vd:4 0101 sz:2 0 align xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 4) <= 31) && ($sz != 3); } \
+   !memory { align(8); reg($rn); }
+
+# type 0000: VST4 inc=1
+VST4_m A1a 1111 0100 0 d 00 rn:4 vd:4 0000 sz:2 align:2 xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 3) <= 31) && ($sz != 3); } \
+   !memory { align(32); reg($rn); }
+# type 0001: VST4 inc=2
+VST4_m A1b 1111 0100 0 d 00 rn:4 vd:4 0000 sz:2 align:2 xm:4 \
+   !constraints { ($rn != $xm) && (((($d << 4)|$vd) + 6) <= 31) && ($sz != 3); } \
+   !memory { align(32); reg($rn); }
+
+# UNDEF cases for all VST*_m:
+
+# These are the patterns for VST*_m UNDEFs on align bits being wrong
+# Conveniently the conditions for all the VST* line up with the top
+# bits of the type field.
+# type = 01xx align = 1x
+VSTn_m A1a 1111 0100 0 d 10 rn:4 vd:4 01 type:2 sz:2 1 align xm:4
+# type = 10xx align = 11
+VSTn_m A1b 1111 0100 0 d 10 rn:4 vd:4 10 type:2 sz:2 11 xm:4
+
+# VST2/3/4 UNDEF on SZ=1; slightly tedious to pick these out
+# but they are type = xx0x or type = 0011
+VSTn_m A1c 1111 0100 0 d 10 rn:4 vd:4 type:2 0 type0 11 align:2 xm:4
+VSTn_m A1d 1111 0100 0 d 10 rn:4 vd:4 0011 11 align:2 xm:4
+
 # Unused spaces in the load/store instruction encoding space
 # (everything else is some sort of VLDn/VSTn)
 # A = 0 cases: