arm.risu: add patterns covering VFP data processing space

1 files changed, 55 insertions, 37 deletions

diff --git a/arm.risu b/arm.risu
index ee1d3ad..f5fb57c 100644
--- a/arm.risu
+++ b/arm.risu
@@ -14,43 +14,6 @@
 # Some random patterns
 #ADD A1 cond:4 0000 100 s rn:4 rd:4 imm:5 type:2 0 rm:4
 #RBIT A1 cond:4 0110 1111 1111 rd:4 1111 0011 rm:4
-#VADD A2 cond:4 11100 d 11 vn:4 vd:4 101 sz n 0 m 0 vm:4
-
-# Some patterns for testing basic VFP arithmetic, not
-# because we expect these to be wrong but so we can check
-# that they work when we fiddle with the FPSCR.
-VADD A2 cond:4 11100 d 11 vn:4 vd:4 101 sz n 0 m 0 vm:4
-VSUB A2 cond:4 11100 d 11 vn:4 vd:4 101 sz n 1 m 0 vm:4
-VMUL A2 cond:4 11100 d 10 vn:4 vd:4 101 sz n 0 m 0 vm:4
-VDIV A1 cond:4 11101 d 00 vn:4 vd:4 101 sz n 0 m 0 vm:4
-
-########### VCVT #########################################
-# These patterns should cover all the non-Neon VCVT*
-# instructions in their ARM encodings. Neon VCVT* are
-# in the Neon data processing insns sections later.
-##########################################################
-
-# VCVT between fp and int: split in two because opc2 must be 000 or 10x (A8.6.295)
-VCVT_a A1 cond:4 11101 d 111 000 vd:4 101 sz op 1 m 0 vm:4
-VCVT_b A1 cond:4 11101 d 111 10 x vd:4 101 sz op 1 m 0 vm:4
-
-# VCVT between fp and fixed point (A.8.6.297)
-# Ugh. UNPREDICTABLE unless the 32 bit int formed by imm4:i is at least
-# 16 (if sx is 0) or 32 (if sx is 1). That is, if sx==0 then either
-# bit 3 must be 0 or bits 2..0 and 5 must be 0.
-# sx==1 case first:
-VCVT_c A1 cond:4 11101 d 111 op 1 u vd:4 101 sf 1 1 i 0 imm:4
-# sx==0, bit 3 == 0
-VCVT_d A1 cond:4 11101 d 111 op 1 u vd:4 101 sf 0 1 i 0 0 imm:3
-# sx==0, bit 3 == 1, bits 2..0 and 5 0
-VCVT_e A1 cond:4 11101 d 111 op 1 u vd:4 101 sf 0 1 0 0 1000
-
-# VCVT between double and single (A8.6.298)
-VCVT_298 A1 cond:4 1110 1 d 11 0111 vd:4 101 sz 1 1 m 0 vm:4
-
-# VCVTB, VCVTT (A8.6.300)
-VCTV_B_TT A1 cond:4 1110 1 d 11 001 op vd:4 101 0 t 1 m 0 vm:4
-
 
 # various 32x32->64 multiplies
 # we omit the v5-and-below constraint that rn must not be rdhi or rdlo
@@ -665,3 +628,58 @@ VDUP_scalar A1 1111 0011 1 d 11 imm:4 vd:4 11000 q m 0 vm:4
 ###########################################################
 # End of Neon Data Processing instruction patterns.
 ###########################################################
+
+########### VFP Data Processing ###########################
+# The following sets of patterns cover the whole of the
+# "VFP data-processing instructions" space
+# as described in DDI0406B table A7-16 and the subtables
+# it refers to.
+###########################################################
+
+# VMLA, VMLS
+VMLA A2 cond:4 11100 d 00 vn:4 vd:4 101 sz n op m 0 vm:4
+# VNMLA, VNMLS
+VNMLA A1 cond:4 11100 d 01 vn:4 vd:4 101 sz n op m 0 vm:4
+VNMUL A2 cond:4 11100 d 10 vn:4 vd:4 101 sz n 1 m 0 vm:4
+VMUL A2 cond:4 11100 d 10 vn:4 vd:4 101 sz n 0 m 0 vm:4
+VADD A2 cond:4 11100 d 11 vn:4 vd:4 101 sz n 0 m 0 vm:4
+VSUB A2 cond:4 11100 d 11 vn:4 vd:4 101 sz n 1 m 0 vm:4
+VDIV A1 cond:4 11101 d 00 vn:4 vd:4 101 sz n 0 m 0 vm:4
+
+# Other VFP data processing instructions (opc1 1x11)
+# We don't check that SBO/SBZ bits here UNDEF if wrong.
+VMOV_imm A2 cond:4 11101 d 11 immh:4 vd:4 101 sz 0000 imml:4
+VMOV A2 cond:4 11101 d 11 0000 vd:4 101 sz 0 1 m 0 vm:4
+VABS A2 cond:4 11101 d 11 0000 vd:4 101 sz 1 1 m 0 vm:4
+VNEG A2 cond:4 11101 d 11 0001 vd:4 101 sz 0 1 m 0 vm:4
+VSQRT A1 cond:4 11101 d 11 0001 vd:4 101 sz 1 1 m 0 vm:4
+# VCVTB, VCVTT (A8.6.300) [requires half-precision extension]
+VCTV_B_TT A1 cond:4 1110 1 d 11 001 op vd:4 101 0 t 1 m 0 vm:4
+VCMP A1 cond:4 11101 d 11 0100 vd:4 101 sz e 1 m 0 vm:4
+VCMP A2 cond:4 11101 d 11 0101 vd:4 101 sz e 1 0 0 0000
+
+# VCVT between double and single (A8.6.298)
+VCVT_298 A1 cond:4 1110 1 d 11 0111 vd:4 101 sz 1 1 m 0 vm:4
+# VCVT between fp and int: split in two because opc2 must be 000 or 10x (A8.6.295)
+VCVT_a A1 cond:4 11101 d 111 000 vd:4 101 sz op 1 m 0 vm:4
+VCVT_b A1 cond:4 11101 d 111 10 x vd:4 101 sz op 1 m 0 vm:4
+
+# VCVT between fp and fixed point (A.8.6.297)
+# Ugh. UNPREDICTABLE unless the 32 bit int formed by imm4:i is at least
+# 16 (if sx is 0) or 32 (if sx is 1). That is, if sx==0 then either
+# bit 3 must be 0 or bits 2..0 and 5 must be 0.
+# sx==1 case first:
+VCVT_c A1 cond:4 11101 d 111 op 1 u vd:4 101 sf 1 1 i 0 imm:4
+# sx==0, bit 3 == 0
+VCVT_d A1 cond:4 11101 d 111 op 1 u vd:4 101 sf 0 1 i 0 0 imm:3
+# sx==0, bit 3 == 1, bits 2..0 and 5 0
+VCVT_e A1 cond:4 11101 d 111 op 1 u vd:4 101 sf 0 1 0 0 1000
+
+# UNDEF patterns in VFP data processing space (not currently checked):
+# opc1 1x00 opc3 x1
+# opc1 1x01
+# opc1 1x10
+# opc1 1x11 opc2 0110 opc3 x1
+# opc1 1x11 opc2 0111 opc3 01
+# opc1 1x11 opc2 1001 opc3 x1
+