aarch64.risu: add support for pre/post idx unscaled ldr/str

addressing using pre-index / post-index and normal unscaled offset
only differ in encoding by a two bit-field.
Also there is no pre-index / post-index version of prefetch mem.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/risugen b/risugen
index a303f39..83dd5ec 100755
--- a/risugen
+++ b/risugen
@@ -635,6 +635,10 @@ sub reg_plus_imm($$@)
 {
     # Handle reg + immediate addressing mode
     my ($base, $imm, @trashed) = @_;
+    if ($imm == 0) {
+        return reg($base, @trashed);
+    }
+
     write_get_offset();
     # Now r0 is the address we want to do the access to,
     # so set the basereg by doing the inverse of the