risugen: allow shift by 4 in reg_plus_reg_shifted

aarch64 SIMD/fp instruction variants require addressing
in the form register plus register shifted by 4, to align
128bit data.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

1 files changed, 3 insertions, 1 deletions

diff --git a/risugen b/risugen
index b1232c3..5dd02c4 100755
--- a/risugen
+++ b/risugen
@@ -713,7 +713,9 @@ sub reg_plus_reg_shifted($$$@)
 {
     # handle reg + reg LSL imm addressing mode
     my ($base, $idx, $shift, @trashed) = @_;
-    die "reg_plus_reg_shifted: bad shift size\n" if ($shift < 0 || $shift > 3);
+    if ($shift < 0 || $shift > 4 || (!$is_aarch64 && $shift == 4)) {
+        die "reg_plus_reg_shifted: bad shift size\n";
+    }
     my $savedidx = 0;
     if ($idx == 0) {
         # save the index into some other register for the