blob: c33b86f1a6ed92829c28f34d391b7a5b62a1f488 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
|
/******************************************************************************
* Copyright (c) 2013 Linaro Limited
* All rights reserved. This program and the accompanying materials
* are made available under the terms of the Eclipse Public License v1.0
* which accompanies this distribution, and is available at
* http://www.eclipse.org/legal/epl-v10.html
*
* Contributors:
* Claudio Fontana (Linaro) - initial implementation
* based on Peter Maydell's risu_arm.c
*****************************************************************************/
#ifndef RISU_REGINFO_AARCH64_H
#define RISU_REGINFO_AARCH64_H
#include <signal.h> /* for SVE_MAGIC */
struct simd_reginfo {
__uint128_t vregs[32];
char end[0];
};
#ifdef SVE_MAGIC
struct sve_reginfo {
/* SVE */
uint16_t vl; /* current VL */
__uint128_t zregs[SVE_NUM_ZREGS][SVE_VQ_MAX];
uint16_t pregs[SVE_NUM_PREGS][SVE_VQ_MAX];
uint16_t ffr[SVE_VQ_MAX];
char end[0];
};
#endif
/* The kernel headers set this based on future arch extensions.
The current arch maximum is 16. Save space below. */
#undef SVE_VQ_MAX
#define SVE_VQ_MAX 16
struct reginfo {
uint64_t fault_address;
uint64_t regs[31];
uint64_t sp;
uint64_t pc;
uint32_t flags;
uint32_t faulting_insn;
/* FP/SIMD */
uint32_t fpsr;
uint32_t fpcr;
union {
struct simd_reginfo simd;
#ifdef SVE_MAGIC
struct sve_reginfo sve;
#endif
};
};
#endif /* RISU_REGINFO_AARCH64_H */
|
