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authorGrant Likely <grant.likely@linaro.org>2015-02-21 22:35:21 +0000
committerGrant Likely <grant.likely@linaro.org>2015-02-21 22:35:38 +0000
commitce5ad797b089c918f276f4b8625fbe584b77a196 (patch)
tree36c42dfd1789cf00065d98b159440c17a9d70158
Initial Commit
Diffstat
-rw-r--r--96boards-uart-cache.lib173
-rw-r--r--96boards-uart.cmp59
-rw-r--r--96boards-uart.dsn229
-rw-r--r--96boards-uart.kicad_pcb587
-rw-r--r--96boards-uart.lst24
-rw-r--r--96boards-uart.mod381
-rw-r--r--96boards-uart.net145
-rw-r--r--96boards-uart.pro88
-rw-r--r--96boards-uart.sch317
-rw-r--r--mosfet.dcm9
-rw-r--r--mosfet.lib73
-rw-r--r--notes8
12 files changed, 2093 insertions, 0 deletions
diff --git a/96boards-uart-cache.lib b/96boards-uart-cache.lib
new file mode 100644
index 0000000..53331d6
--- /dev/null
+++ b/96boards-uart-cache.lib
@@ -0,0 +1,173 @@
+EESchema-LIBRARY Version 2.3 Date: Sat 21 Feb 2015 18:25:41 GMT
+#encoding utf-8
+#
+# +1.8V
+#
+DEF +1.8V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 140 20 H I C CNN
+F1 "+1.8V" 0 110 30 H V C CNN
+F2 "~" 0 0 60 H V C CNN
+F3 "~" 0 0 60 H V C CNN
+ALIAS 1V8
+DRAW
+P 3 0 0 0 0 0 0 40 0 40 N
+X +1.8V 1 0 0 0 U 20 20 0 0 W N
+C 0 60 20 0 1 0 N
+ENDDRAW
+ENDDEF
+#
+# CONN_20X2
+#
+DEF CONN_20X2 P 0 10 Y N 1 F N
+F0 "P" 0 1050 60 H V C CNN
+F1 "CONN_20X2" 0 0 50 V V C CNN
+F2 "~" 0 0 60 H V C CNN
+F3 "~" 0 0 60 H V C CNN
+DRAW
+S -100 1000 100 -1000 0 1 0 N
+X P1 1 -400 950 300 R 60 30 1 1 P I
+X P2 2 400 950 300 L 60 30 1 1 P I
+X P3 3 -400 850 300 R 60 30 1 1 P I
+X P4 4 400 850 300 L 60 30 1 1 P I
+X P5 5 -400 750 300 R 60 30 1 1 P I
+X P6 6 400 750 300 L 60 30 1 1 P I
+X P7 7 -400 650 300 R 60 30 1 1 P I
+X P8 8 400 650 300 L 60 30 1 1 P I
+X P9 9 -400 550 300 R 60 30 1 1 P I
+X P10 10 400 550 300 L 60 30 1 1 P I
+X P20 20 400 50 300 L 60 30 1 1 P I
+X P30 30 400 -450 300 L 60 30 1 1 P I
+X P40 40 400 -950 300 L 60 30 1 1 P I
+X P11 11 -400 450 300 R 60 30 1 1 P I
+X P21 21 -400 -50 300 R 60 30 1 1 P I
+X P31 31 -400 -550 300 R 60 30 1 1 P I
+X P12 12 400 450 300 L 60 30 1 1 P I
+X P22 22 400 -50 300 L 60 30 1 1 P I
+X P32 32 400 -550 300 L 60 30 1 1 P I
+X P13 13 -400 350 300 R 60 30 1 1 P I
+X P23 23 -400 -150 300 R 60 30 1 1 P I
+X P33 33 -400 -650 300 R 60 30 1 1 P I
+X P14 14 400 350 300 L 60 30 1 1 P I
+X P24 24 400 -150 300 L 60 30 1 1 P I
+X P34 34 400 -650 300 L 60 30 1 1 P I
+X P15 15 -400 250 300 R 60 30 1 1 P I
+X ~ 25 -400 -250 300 R 60 30 1 1 P I
+X P35 35 -400 -750 300 R 60 30 1 1 P I
+X P16 16 400 250 300 L 60 30 1 1 P I
+X P26 26 400 -250 300 L 60 30 1 1 P I
+X P36 36 400 -750 300 L 60 30 1 1 P I
+X P17 17 -400 150 300 R 60 30 1 1 P I
+X P27 27 -400 -350 300 R 60 30 1 1 P I
+X P37 37 -400 -850 300 R 60 30 1 1 P I
+X P18 18 400 150 300 L 60 30 1 1 P I
+X P28 28 400 -350 300 L 60 30 1 1 P I
+X P38 38 400 -850 300 L 60 30 1 1 P I
+X P19 19 -400 50 300 R 60 30 1 1 P I
+X P29 29 -400 -450 300 R 60 30 1 1 P I
+X P39 39 -400 -950 300 R 60 30 1 1 P I
+ENDDRAW
+ENDDEF
+#
+# CONN_6
+#
+DEF CONN_6 P 0 30 Y N 1 F N
+F0 "P" -50 0 60 V V C CNN
+F1 "CONN_6" 50 0 60 V V C CNN
+F2 "~" 0 0 60 H V C CNN
+F3 "~" 0 0 60 H V C CNN
+DRAW
+S -100 300 100 -300 0 1 0 N
+X 1 1 -350 250 250 R 60 60 1 1 P I
+X 2 2 -350 150 250 R 60 60 1 1 P I
+X 3 3 -350 50 250 R 60 60 1 1 P I
+X 4 4 -350 -50 250 R 60 60 1 1 P I
+X 5 5 -350 -150 250 R 60 60 1 1 P I
+X 6 6 -350 -250 250 R 60 60 1 1 P I
+ENDDRAW
+ENDDEF
+#
+# DMN601DMK
+#
+DEF DMN601DMK Q 0 0 Y Y 2 F N
+F0 "Q" 0 -149 40 H V R CNN
+F1 "DMN601DMK" 0 150 40 H V R CNN
+F2 "SOT-26" -130 102 29 H V C CNN
+F3 "~" 0 0 60 H V C CNN
+$FPLIST
+ SOT-26*
+$ENDFPLIST
+DRAW
+C 50 0 111 0 1 10 N
+C 100 -50 5 0 1 0 N
+C 100 50 5 0 1 0 N
+P 2 0 1 20 25 -40 25 -65 N
+P 2 0 1 20 25 15 25 -15 N
+P 2 0 1 20 25 65 25 40 N
+P 2 0 1 0 120 15 115 10 N
+P 2 0 1 0 120 15 140 15 N
+P 2 0 1 0 140 15 145 20 N
+P 3 0 1 10 0 60 0 -60 0 -60 N
+P 4 0 1 0 30 -50 100 -50 100 -100 100 -100 N
+P 4 0 1 0 30 50 100 50 100 100 100 100 N
+P 4 0 1 0 100 50 130 50 130 -50 100 -50 N
+P 4 0 1 0 130 15 120 -10 140 -10 130 15 F
+P 5 0 1 0 30 0 50 0 100 0 100 -50 100 -50 N
+P 6 0 1 0 35 0 75 15 75 -15 35 0 40 0 40 0 F
+X S 1 100 -200 100 U 40 40 1 1 P
+X G 2 -200 -50 200 R 40 40 1 1 P
+X D 6 100 200 100 D 40 40 1 1 P
+X D 3 100 200 100 D 40 40 2 1 P
+X S 4 100 -200 100 U 40 40 2 1 P
+X G 5 -200 -50 200 R 40 40 2 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+F2 "~" 0 0 60 H V C CNN
+F3 "~" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 40 V V C CNN
+F1 "R" 7 1 40 V V C CNN
+F2 "~" -70 0 30 V V C CNN
+F3 "~" 0 0 30 H V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VCC
+#
+DEF VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 100 30 H I C CNN
+F1 "VCC" 0 100 30 H V C CNN
+F2 "~" 0 0 60 H V C CNN
+F3 "~" 0 0 60 H V C CNN
+DRAW
+X VCC 1 0 0 0 U 20 20 0 0 W N
+C 0 50 20 0 1 0 N
+P 3 0 1 0 0 0 0 30 0 30 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/96boards-uart.cmp b/96boards-uart.cmp
new file mode 100644
index 0000000..1fb27bc
--- /dev/null
+++ b/96boards-uart.cmp
@@ -0,0 +1,59 @@
+Cmp-Mod V01 Created by CvPcb (22-Jun-2014 BZR 4027)-stable date = Fri 20 Feb 2015 22:33:44 PST
+
+BeginCmp
+TimeStamp = /54E6538C;
+Reference = P1;
+ValeurCmp = CONN_20X2;
+IdModule = PIN_ARRAY_2MM_20X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /54E6539B;
+Reference = P2;
+ValeurCmp = CONN_6;
+IdModule = SIL-6;
+EndCmp
+
+BeginCmp
+TimeStamp = /54E653AA;
+Reference = P3;
+ValeurCmp = CONN_8;
+IdModule = SIL2MM-8;
+EndCmp
+
+BeginCmp
+TimeStamp = /54E7E6E1;
+Reference = Q1;
+ValeurCmp = DMN601DMK;
+IdModule = SOT23_6;
+EndCmp
+
+BeginCmp
+TimeStamp = /54E7D31F;
+Reference = R1;
+ValeurCmp = R;
+IdModule = SM0402_r;
+EndCmp
+
+BeginCmp
+TimeStamp = /54E7D852;
+Reference = R2;
+ValeurCmp = R;
+IdModule = SM0402_r;
+EndCmp
+
+BeginCmp
+TimeStamp = /54E7D3D1;
+Reference = R3;
+ValeurCmp = R;
+IdModule = SM0402_r;
+EndCmp
+
+BeginCmp
+TimeStamp = /54E7D85A;
+Reference = R4;
+ValeurCmp = R;
+IdModule = SM0402_r;
+EndCmp
+
+EndListe
diff --git a/96boards-uart.dsn b/96boards-uart.dsn
new file mode 100644
index 0000000..2c42676
--- /dev/null
+++ b/96boards-uart.dsn
@@ -0,0 +1,229 @@
+(pcb "/home/grant/hacking/hardware/96boards uart/96boards-uart.dsn"
+ (parser
+ (string_quote ")
+ (space_in_quoted_tokens on)
+ (host_cad "KiCad's Pcbnew")
+ (host_version "(22-Jun-2014 BZR 4027)-stable")
+ )
+ (resolution um 10)
+ (unit um)
+ (structure
+ (layer F.Cu
+ (type signal)
+ (property
+ (index 0)
+ )
+ )
+ (layer B.Cu
+ (type signal)
+ (property
+ (index 1)
+ )
+ )
+ (boundary
+ (path pcb 0 90000 -108000 90000 -122000 140000 -122000 140000 -108000
+ 90000 -108000)
+ )
+ (via "Via[0-1]_889:635_um" "Via[0-1]_889:0_um")
+ (rule
+ (width 254)
+ (clearance 254.1)
+ (clearance 254.1 (type default_smd))
+ (clearance 63.5 (type smd_smd))
+ )
+ )
+ (placement
+ (component SOT23_6
+ (place Q1 118500 -117500 front 0 (PN DMN601DMK))
+ )
+ (component SM0402_r
+ (place R1 115500 -119000 front 0 (PN R))
+ (place R3 115500 -116000 back 180 (PN R))
+ (place R2 121500 -116000 front 180 (PN R))
+ (place R4 121500 -119000 front 180 (PN R))
+ )
+ (component "SIL-6"
+ (place P2 106000 -119000 front 0 (PN CONN_6))
+ )
+ (component PIN_ARRAY_2MM_20X2
+ (place P1 119000 -112000 front 0 (PN CONN_20X2))
+ )
+ (component "SIL2MM-8"
+ (place P3 131000 -119000 front 0 (PN CONN_8))
+ )
+ )
+ (library
+ (image SOT23_6
+ (outline (path signal 127 -508 -762 -1270 -254))
+ (outline (path signal 127 1270 -762 -1333.5 -762))
+ (outline (path signal 127 -1333.5 -762 -1333.5 762))
+ (outline (path signal 127 -1333.5 762 1270 762))
+ (outline (path signal 127 1270 762 1270 -762))
+ (pin Rect[T]Pad_701.04x1000.76_um 6 -952.5 1270)
+ (pin Rect[T]Pad_701.04x1000.76_um 5 0 1270)
+ (pin Rect[T]Pad_701.04x1000.76_um 4 952.5 1270)
+ (pin Rect[T]Pad_701.04x1000.76_um 3 952.5 -1270)
+ (pin Rect[T]Pad_701.04x1000.76_um 2 0 -1270)
+ (pin Rect[T]Pad_701.04x1000.76_um 1 -952.5 -1270)
+ )
+ (image SM0402_r
+ (outline (path signal 71.12 -254 381 -762 381))
+ (outline (path signal 71.12 -762 381 -762 -381))
+ (outline (path signal 71.12 -762 -381 -254 -381))
+ (outline (path signal 71.12 254 381 762 381))
+ (outline (path signal 71.12 762 381 762 -381))
+ (outline (path signal 71.12 762 -381 254 -381))
+ (pin Rect[T]Pad_398.78x599.44_um 1 -449.58 0)
+ (pin Rect[T]Pad_398.78x599.44_um 2 449.58 0)
+ )
+ (image "SIL-6"
+ (outline (path signal 304.8 -7620 -1270 -7620 1270))
+ (outline (path signal 304.8 -7620 1270 7620 1270))
+ (outline (path signal 304.8 7620 1270 7620 -1270))
+ (outline (path signal 304.8 7620 -1270 -7620 -1270))
+ (outline (path signal 304.8 -5080 -1270 -5080 1270))
+ (pin Rect[A]Pad_1397x1397_um 1 -6350 0)
+ (pin Round[A]Pad_1397_um 2 -3810 0)
+ (pin Round[A]Pad_1397_um 3 -1270 0)
+ (pin Round[A]Pad_1397_um 4 1270 0)
+ (pin Round[A]Pad_1397_um 5 3810 0)
+ (pin Round[A]Pad_1397_um 6 6350 0)
+ )
+ (image PIN_ARRAY_2MM_20X2
+ (outline (path signal 304.8 20540 -2540 -20540 -2540))
+ (outline (path signal 304.8 20540 2540 -20540 2540))
+ (outline (path signal 304.8 20540 2540 20540 -2540))
+ (outline (path signal 304.8 -20540 2540 -20540 -2540))
+ (pin Rect[A]Pad_1200x1200_um 1 -19000 -1000)
+ (pin Round[A]Pad_1200_um 2 -19000 1000)
+ (pin Round[A]Pad_1200_um 11 -9000 -1000)
+ (pin Round[A]Pad_1200_um 4 -17000 1000)
+ (pin Round[A]Pad_1200_um 13 -7000 -1000)
+ (pin Round[A]Pad_1200_um 6 -15000 1000)
+ (pin Round[A]Pad_1200_um 15 -5000 -1000)
+ (pin Round[A]Pad_1200_um 8 -13000 1000)
+ (pin Round[A]Pad_1200_um 17 -3000 -1000)
+ (pin Round[A]Pad_1200_um 10 -11000 1000)
+ (pin Round[A]Pad_1200_um 19 -1000 -1000)
+ (pin Round[A]Pad_1200_um 12 -9000 1000)
+ (pin Round[A]Pad_1200_um 21 1000 -1000)
+ (pin Round[A]Pad_1200_um 14 -7000 1000)
+ (pin Round[A]Pad_1200_um 23 3000 -1000)
+ (pin Round[A]Pad_1200_um 16 -5000 1000)
+ (pin Round[A]Pad_1200_um 25 5000 -1000)
+ (pin Round[A]Pad_1200_um 18 -3000 1000)
+ (pin Round[A]Pad_1200_um 27 7000 -1000)
+ (pin Round[A]Pad_1200_um 20 -1000 1000)
+ (pin Round[A]Pad_1200_um 29 9000 -1000)
+ (pin Round[A]Pad_1200_um 22 1000 1000)
+ (pin Round[A]Pad_1200_um 31 11000 -1000)
+ (pin Round[A]Pad_1200_um 24 3000 1000)
+ (pin Round[A]Pad_1200_um 26 5000 1000)
+ (pin Round[A]Pad_1200_um 33 13000 -1000)
+ (pin Round[A]Pad_1200_um 28 7000 1000)
+ (pin Round[A]Pad_1200_um 32 11000 1000)
+ (pin Round[A]Pad_1200_um 34 13000 1000)
+ (pin Round[A]Pad_1200_um 36 15000 1000)
+ (pin Round[A]Pad_1200_um 38 17000 1000)
+ (pin Round[A]Pad_1200_um 35 15000 -1000)
+ (pin Round[A]Pad_1200_um 37 17000 -1000)
+ (pin Round[A]Pad_1200_um 3 -17000 -1000)
+ (pin Round[A]Pad_1200_um 5 -15000 -1000)
+ (pin Round[A]Pad_1200_um 7 -13000 -1000)
+ (pin Round[A]Pad_1200_um 9 -11000 -1000)
+ (pin Round[A]Pad_1200_um 39 19000 -1000)
+ (pin Round[A]Pad_1200_um 40 19000 1000)
+ (pin Round[A]Pad_1200_um 30 9000 1000)
+ )
+ (image "SIL2MM-8"
+ (outline (path signal 304.8 -8000 1000 8000 1000))
+ (outline (path signal 304.8 8000 1000 8000 -1000))
+ (outline (path signal 304.8 8000 -1000 -8000 -1000))
+ (outline (path signal 304.8 -8000 -1000 -8000 1000))
+ (outline (path signal 304.8 -6000 -1000 -6000 1000))
+ (pin Rect[A]Pad_1200x1200_um 1 -7000 0)
+ (pin Round[A]Pad_1200_um 2 -5000 0)
+ (pin Round[A]Pad_1200_um 3 -3000 0)
+ (pin Round[A]Pad_1200_um 4 -1000 0)
+ (pin Round[A]Pad_1200_um 5 1000 0)
+ (pin Round[A]Pad_1200_um 6 3000 0)
+ (pin Round[A]Pad_1200_um 7 5000 0)
+ (pin Round[A]Pad_1200_um 8 7000 0)
+ )
+ (padstack Round[A]Pad_1200_um
+ (shape (circle F.Cu 1200))
+ (shape (circle B.Cu 1200))
+ (attach off)
+ )
+ (padstack Round[A]Pad_1397_um
+ (shape (circle F.Cu 1397))
+ (shape (circle B.Cu 1397))
+ (attach off)
+ )
+ (padstack Rect[T]Pad_398.78x599.44_um
+ (shape (rect F.Cu -199.39 -299.72 199.39 299.72))
+ (attach off)
+ )
+ (padstack Rect[T]Pad_701.04x1000.76_um
+ (shape (rect F.Cu -350.52 -500.38 350.52 500.38))
+ (attach off)
+ )
+ (padstack Rect[A]Pad_1200x1200_um
+ (shape (rect F.Cu -600 -600 600 600))
+ (shape (rect B.Cu -600 -600 600 600))
+ (attach off)
+ )
+ (padstack Rect[A]Pad_1397x1397_um
+ (shape (rect F.Cu -698.5 -698.5 698.5 698.5))
+ (shape (rect B.Cu -698.5 -698.5 698.5 698.5))
+ (attach off)
+ )
+ (padstack "Via[0-1]_889:635_um"
+ (shape (circle F.Cu 889))
+ (shape (circle B.Cu 889))
+ (attach off)
+ )
+ (padstack "Via[0-1]_889:0_um"
+ (shape (circle F.Cu 889))
+ (shape (circle B.Cu 889))
+ (attach off)
+ )
+ )
+ (network
+ (net +1.8V
+ (pins Q1-5 Q1-2 R1-1 R2-1 P1-35)
+ )
+ (net /UART0_RXD
+ (pins Q1-4 R2-2 P1-7)
+ )
+ (net /UART0_TXD
+ (pins Q1-1 R1-2 P1-5)
+ )
+ (net GND
+ (pins P2-1 P1-1 P1-2 P3-8)
+ )
+ (net "N-000003"
+ (pins Q1-6 R3-2 P2-5 P3-4)
+ )
+ (net "N-000005"
+ (pins Q1-3 R4-2 P2-4 P3-5)
+ )
+ (net VCC
+ (pins R3-1 R4-1 P2-3 P3-6)
+ )
+ (class kicad_default "" +1.8V /UART0_RXD /UART0_TXD GND "N-000003" "N-000005"
+ VCC
+ (circuit
+ (use_via Via[0-1]_889:635_um)
+ )
+ (rule
+ (width 254)
+ (clearance 254.1)
+ )
+ )
+ )
+ (wiring
+ (wire (path B.Cu 254 100000 -113000 100000 -118650 99650 -119000)(net GND)(type protect))
+ (wire (path B.Cu 254 100000 -111000 100000 -113000)(net GND)(type protect))
+ )
+)
diff --git a/96boards-uart.kicad_pcb b/96boards-uart.kicad_pcb
new file mode 100644
index 0000000..dda4973
--- /dev/null
+++ b/96boards-uart.kicad_pcb
@@ -0,0 +1,587 @@
+(kicad_pcb (version 3) (host pcbnew "(22-Jun-2014 BZR 4027)-stable")
+
+ (general
+ (links 16)
+ (no_connects 0)
+ (area 96.949999 107.29084 141.050001 122.050001)
+ (thickness 1.6)
+ (drawings 20)
+ (tracks 64)
+ (zones 0)
+ (modules 7)
+ (nets 8)
+ )
+
+ (page A3)
+ (layers
+ (15 F.Cu signal)
+ (0 B.Cu signal)
+ (16 B.Adhes user)
+ (17 F.Adhes user)
+ (18 B.Paste user)
+ (19 F.Paste user)
+ (20 B.SilkS user)
+ (21 F.SilkS user)
+ (22 B.Mask user)
+ (23 F.Mask user)
+ (24 Dwgs.User user)
+ (25 Cmts.User user)
+ (26 Eco1.User user)
+ (27 Eco2.User user)
+ (28 Edge.Cuts user)
+ )
+
+ (setup
+ (last_trace_width 0.254)
+ (trace_clearance 0.254)
+ (zone_clearance 0.508)
+ (zone_45_only no)
+ (trace_min 0.254)
+ (segment_width 0.2)
+ (edge_width 0.1)
+ (via_size 0.889)
+ (via_drill 0.635)
+ (via_min_size 0.889)
+ (via_min_drill 0.508)
+ (uvia_size 0.508)
+ (uvia_drill 0.127)
+ (uvias_allowed no)
+ (uvia_min_size 0.508)
+ (uvia_min_drill 0.127)
+ (pcb_text_width 0.3)
+ (pcb_text_size 1.5 1.5)
+ (mod_edge_width 0.15)
+ (mod_text_size 1 1)
+ (mod_text_width 0.15)
+ (pad_size 1.2 1.2)
+ (pad_drill 0.8)
+ (pad_to_mask_clearance 0)
+ (aux_axis_origin 0 0)
+ (visible_elements FFFFFFEF)
+ (pcbplotparams
+ (layerselection 3178497)
+ (usegerberextensions true)
+ (excludeedgelayer true)
+ (linewidth 0.150000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15)
+ (hpglpenoverlay 2)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotothertext true)
+ (plotinvisibletext false)
+ (padsonsilk false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 0)
+ (scaleselection 1)
+ (outputdirectory ""))
+ )
+
+ (net 0 "")
+ (net 1 +1.8V)
+ (net 2 /UART0_RXD_HV)
+ (net 3 /UART0_RXD_LV)
+ (net 4 /UART0_TXD_HV)
+ (net 5 /UART0_TXD_LV)
+ (net 6 GND)
+ (net 7 VCC)
+
+ (net_class Default "This is the default net class."
+ (clearance 0.254)
+ (trace_width 0.254)
+ (via_dia 0.889)
+ (via_drill 0.635)
+ (uvia_dia 0.508)
+ (uvia_drill 0.127)
+ (add_net "")
+ (add_net +1.8V)
+ (add_net /UART0_RXD_HV)
+ (add_net /UART0_RXD_LV)
+ (add_net /UART0_TXD_HV)
+ (add_net /UART0_TXD_LV)
+ (add_net GND)
+ (add_net VCC)
+ )
+
+ (module SOT23_6 (layer F.Cu) (tedit 54E7F294) (tstamp 54E7F206)
+ (at 118.5 117.5)
+ (path /54E7E6E1)
+ (fp_text reference Q1 (at 1.99898 0 90) (layer F.SilkS)
+ (effects (font (size 0.762 0.762) (thickness 0.0762)))
+ )
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+ (rotate (xyz 0 0 0))
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+ (at (xyz 0 0 0))
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+ (rotate (xyz 0 0 0))
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+ )
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+ (module SM0402_r (layer F.Cu) (tedit 54E81964) (tstamp 54E7F21E)
+ (at 115.5 116)
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+ (at (xyz 0 0 0))
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+ (rotate (xyz 0 0 0))
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+
+ (module SM0402_r (layer F.Cu) (tedit 54E8A4DC) (tstamp 54E7F22A)
+ (at 121.5 116 180)
+ (path /54E7D852)
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+ (rotate (xyz 0 0 0))
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+ (module SM0402_r (layer F.Cu) (tedit 54E8A538) (tstamp 54E7F236)
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+
+ (module SIL-6 (layer F.Cu) (tedit 200000) (tstamp 54E7F28D)
+ (at 106 120)
+ (descr "Connecteur 6 pins")
+ (tags "CONN DEV")
+ (path /54E6539B)
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+ (pad 6 thru_hole circle (at 6.35 0) (size 1.397 1.397) (drill 0.8128)
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+ (tags CONN)
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+ (segment (start 119 117.5) (end 118.5 117) (width 0.254) (layer F.Cu) (net 1) (tstamp 54E8A76B))
+ (segment (start 121 117.5) (end 119 117.5) (width 0.254) (layer F.Cu) (net 1) (tstamp 54E8A768))
+ (segment (start 121.94958 116.55042) (end 121 117.5) (width 0.254) (layer F.Cu) (net 1) (tstamp 54E8A763))
+ (segment (start 107.27 120) (end 107.27 116.23) (width 0.254) (layer B.Cu) (net 2))
+ (segment (start 117.5475 115.0475) (end 117.5475 116.23) (width 0.254) (layer F.Cu) (net 2) (tstamp 54E8C8AA))
+ (segment (start 117.5 115) (end 117.5475 115.0475) (width 0.254) (layer F.Cu) (net 2) (tstamp 54E8C8A9))
+ (via (at 117.5 115) (size 0.889) (layers F.Cu B.Cu) (net 2))
+ (segment (start 108.5 115) (end 117.5 115) (width 0.254) (layer B.Cu) (net 2) (tstamp 54E8C8A2))
+ (segment (start 107.27 116.23) (end 108.5 115) (width 0.254) (layer B.Cu) (net 2) (tstamp 54E8C8A1))
+ (segment (start 115.94958 116) (end 117.3175 116) (width 0.254) (layer F.Cu) (net 2))
+ (segment (start 117.3175 116) (end 117.5475 116.23) (width 0.254) (layer F.Cu) (net 2) (tstamp 54E8C5E9))
+ (segment (start 106 113) (end 110.5 117.5) (width 0.254) (layer F.Cu) (net 3))
+ (segment (start 114.94958 118.94958) (end 116 118.94958) (width 0.254) (layer F.Cu) (net 3) (tstamp 54E8C83B))
+ (segment (start 113.5 117.5) (end 114.94958 118.94958) (width 0.254) (layer F.Cu) (net 3) (tstamp 54E8C832))
+ (segment (start 110.5 117.5) (end 113.5 117.5) (width 0.254) (layer F.Cu) (net 3) (tstamp 54E8C827))
+ (segment (start 116 118.94958) (end 117.3175 119) (width 0.254) (layer F.Cu) (net 3) (status 10))
+ (segment (start 117.3175 119) (end 117.5475 118.77) (width 0.254) (layer F.Cu) (net 3) (tstamp 54E8A7C2))
+ (segment (start 109.81 120) (end 110 120) (width 0.254) (layer F.Cu) (net 4))
+ (segment (start 119.4525 119.5475) (end 119.4525 118.77) (width 0.254) (layer F.Cu) (net 4) (tstamp 54E8C907))
+ (segment (start 119 120) (end 119.4525 119.5475) (width 0.254) (layer F.Cu) (net 4) (tstamp 54E8C903))
+ (segment (start 115 120) (end 119 120) (width 0.254) (layer F.Cu) (net 4) (tstamp 54E8C8FF))
+ (segment (start 113.5 118.5) (end 115 120) (width 0.254) (layer F.Cu) (net 4) (tstamp 54E8C8FD))
+ (segment (start 111.5 118.5) (end 113.5 118.5) (width 0.254) (layer F.Cu) (net 4) (tstamp 54E8C8F8))
+ (segment (start 110 120) (end 111.5 118.5) (width 0.254) (layer F.Cu) (net 4) (tstamp 54E8C8F3))
+ (segment (start 121.05042 119) (end 119.6825 119) (width 0.254) (layer F.Cu) (net 4))
+ (segment (start 119.6825 119) (end 119.4525 118.77) (width 0.254) (layer F.Cu) (net 4) (tstamp 54E8AA30))
+ (segment (start 104 113) (end 105 112) (width 0.254) (layer F.Cu) (net 5))
+ (segment (start 119.4525 114.4525) (end 119.4525 116.23) (width 0.254) (layer F.Cu) (net 5) (tstamp 54E8C57B))
+ (segment (start 119 114) (end 119.4525 114.4525) (width 0.254) (layer F.Cu) (net 5) (tstamp 54E8C578))
+ (segment (start 119 112.5) (end 119 114) (width 0.254) (layer F.Cu) (net 5) (tstamp 54E8C576))
+ (segment (start 118.5 112) (end 119 112.5) (width 0.254) (layer F.Cu) (net 5) (tstamp 54E8C56E))
+ (segment (start 105 112) (end 118.5 112) (width 0.254) (layer F.Cu) (net 5) (tstamp 54E8C56B))
+ (segment (start 119.4525 116.23) (end 120.82042 116.23) (width 0.254) (layer F.Cu) (net 5))
+ (segment (start 120.82042 116.23) (end 121.05042 116) (width 0.254) (layer F.Cu) (net 5) (tstamp 54E8A74C))
+ (segment (start 100 113) (end 100 119.65) (width 0.254) (layer B.Cu) (net 6) (status 20))
+ (segment (start 100 119.65) (end 99.65 120) (width 0.254) (layer B.Cu) (net 6) (tstamp 54E8A3BB) (status 30))
+ (segment (start 100 111) (end 100 113) (width 0.254) (layer B.Cu) (net 6) (status 30))
+ (segment (start 108 121.5) (end 121.5 121.5) (width 0.254) (layer B.Cu) (net 7))
+ (segment (start 121.94958 119.94958) (end 121.94958 119) (width 0.254) (layer F.Cu) (net 7) (tstamp 54E8C91A))
+ (segment (start 122 120) (end 121.94958 119.94958) (width 0.254) (layer F.Cu) (net 7) (tstamp 54E8C919))
+ (via (at 122 120) (size 0.889) (layers F.Cu B.Cu) (net 7))
+ (segment (start 122 121) (end 122 120) (width 0.254) (layer B.Cu) (net 7) (tstamp 54E8C916))
+ (segment (start 121.5 121.5) (end 122 121) (width 0.254) (layer B.Cu) (net 7) (tstamp 54E8C912))
+ (segment (start 104.73 120) (end 104.73 120.23) (width 0.254) (layer B.Cu) (net 7))
+ (segment (start 113.5 116) (end 115.05042 116) (width 0.254) (layer F.Cu) (net 7))
+ (via (at 113.5 116) (size 0.889) (layers F.Cu B.Cu) (net 7))
+ (segment (start 109 116) (end 113.5 116) (width 0.254) (layer B.Cu) (net 7) (tstamp 54E8C8CB))
+ (segment (start 108.5 116.5) (end 109 116) (width 0.254) (layer B.Cu) (net 7) (tstamp 54E8C8C9))
+ (segment (start 108.5 121) (end 108.5 116.5) (width 0.254) (layer B.Cu) (net 7) (tstamp 54E8C8C5))
+ (segment (start 108 121.5) (end 108.5 121) (width 0.254) (layer B.Cu) (net 7) (tstamp 54E8C8C4))
+ (segment (start 106 121.5) (end 108 121.5) (width 0.254) (layer B.Cu) (net 7) (tstamp 54E8C8C2))
+ (segment (start 104.73 120.23) (end 106 121.5) (width 0.254) (layer B.Cu) (net 7) (tstamp 54E8C8C0))
+
+)
diff --git a/96boards-uart.lst b/96boards-uart.lst
new file mode 100644
index 0000000..a06b2b1
--- /dev/null
+++ b/96boards-uart.lst
@@ -0,0 +1,24 @@
+eeschema (22-Jun-2014 BZR 4027)-stable >> Creation date: Fri 20 Feb 2015 21:40:25 PST
+#Cmp ( order = Reference )
+| P1 CONN_20X2
+| P2 CONN_6
+| P3 CONN_8
+| Q1 DMN601DMK
+| R1 R
+| R2 R
+| R3 R
+| R4 R
+#End Cmp
+
+#Cmp ( order = Value )
+| CONN_20X2 P1
+| CONN_6 P2
+| CONN_8 P3
+| DMN601DMK Q1
+| R R1
+| R R2
+| R R3
+| R R4
+#End Cmp
+
+#End List
diff --git a/96boards-uart.mod b/96boards-uart.mod
new file mode 100644
index 0000000..a3e8d60
--- /dev/null
+++ b/96boards-uart.mod
@@ -0,0 +1,381 @@
+PCBNEW-LibModule-V1 Sat 21 Feb 2015 16:16:57 GMT
+# encoding utf-8
+Units mm
+$INDEX
+PIN_ARRAY_2MM_20X2
+SIL2MM-8
+$EndINDEX
+$MODULE PIN_ARRAY_2MM_20X2
+Po 0 0 0 15 54E8AF73 00000000 ~~
+Li PIN_ARRAY_2MM_20X2
+Cd Double rangee de contacts 2 x 12 pins
+Kw CONN
+Sc 0
+AR /54E6538C
+Op 0 0 0
+T0 0 -3.81 1.016 1.016 0 0.27432 N V 21 N "P1"
+T1 0 3.81 1.016 1.016 0 0.2032 N V 21 N "CONN_20X2"
+DS 21.5 3.25 -21.5 3.25 0.3048 21
+DS -21.5 -3.25 21.5 -3.25 0.3048 21
+DS 21.5 -3.25 21.5 3.25 0.3048 21
+DS -21.5 -3.25 -21.5 3.25 0.3048 21
+$PAD
+Sh "1" R 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -19 1
+$EndPAD
+$PAD
+Sh "2" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -19 -1
+$EndPAD
+$PAD
+Sh "11" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -9 1
+$EndPAD
+$PAD
+Sh "4" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -17 -1
+$EndPAD
+$PAD
+Sh "13" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -7 1
+$EndPAD
+$PAD
+Sh "6" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -15 -1
+$EndPAD
+$PAD
+Sh "15" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -5 1
+$EndPAD
+$PAD
+Sh "8" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -13 -1
+$EndPAD
+$PAD
+Sh "17" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -3 1
+$EndPAD
+$PAD
+Sh "10" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -11 -1
+$EndPAD
+$PAD
+Sh "19" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -1 1
+$EndPAD
+$PAD
+Sh "12" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -9 -1
+$EndPAD
+$PAD
+Sh "21" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 1 1
+$EndPAD
+$PAD
+Sh "14" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -7 -1
+$EndPAD
+$PAD
+Sh "23" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 3 1
+$EndPAD
+$PAD
+Sh "16" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -5 -1
+$EndPAD
+$PAD
+Sh "25" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 5 1
+$EndPAD
+$PAD
+Sh "18" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -3 -1
+$EndPAD
+$PAD
+Sh "27" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 7 1
+$EndPAD
+$PAD
+Sh "20" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -1 -1
+$EndPAD
+$PAD
+Sh "29" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 9 1
+$EndPAD
+$PAD
+Sh "22" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 1 -1
+$EndPAD
+$PAD
+Sh "31" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 11 1
+$EndPAD
+$PAD
+Sh "24" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 3 -1
+$EndPAD
+$PAD
+Sh "26" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 5 -1
+$EndPAD
+$PAD
+Sh "33" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 13 1
+$EndPAD
+$PAD
+Sh "28" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 7 -1
+$EndPAD
+$PAD
+Sh "32" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 11 -1
+$EndPAD
+$PAD
+Sh "34" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 13 -1
+$EndPAD
+$PAD
+Sh "36" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 15 -1
+$EndPAD
+$PAD
+Sh "38" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 17 -1
+$EndPAD
+$PAD
+Sh "35" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 15 1
+$EndPAD
+$PAD
+Sh "37" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 17 1
+$EndPAD
+$PAD
+Sh "3" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -17 1
+$EndPAD
+$PAD
+Sh "5" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -15 1
+$EndPAD
+$PAD
+Sh "7" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -13 1
+$EndPAD
+$PAD
+Sh "9" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -11 1
+$EndPAD
+$PAD
+Sh "39" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 19 1
+$EndPAD
+$PAD
+Sh "40" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 19 -1
+$EndPAD
+$PAD
+Sh "30" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 9 -1
+$EndPAD
+$SHAPE3D
+Na "pin_array/pins_array_20x2.wrl"
+Sc 1 1 1
+Of 0 0 0
+Ro 0 0 0
+$EndSHAPE3D
+$EndMODULE PIN_ARRAY_2MM_20X2
+$MODULE SIL2MM-8
+Po 0 0 0 15 54E83160 00000000 ~~
+Li SIL2MM-8
+Cd Connecteur 8 pins
+Kw CONN DEV
+Sc 0
+AR /54E653AA
+Op 0 0 0
+T0 -5.08 -2.54 1.72974 1.08712 0 0.27178 N V 21 N "P3"
+T1 5.08 -2.54 1.524 1.016 0 0.3048 N V 21 N "CONN_8"
+DS -8 -1 8 -1 0.3048 21
+DS 8 -1 8 1 0.3048 21
+DS 8 1 -8 1 0.3048 21
+DS -8 1 -8 -1 0.3048 21
+DS -6 1 -6 -1 0.3048 21
+$PAD
+Sh "1" R 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -7 0
+$EndPAD
+$PAD
+Sh "2" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -5 0
+$EndPAD
+$PAD
+Sh "3" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -3 0
+$EndPAD
+$PAD
+Sh "4" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 2 "N-000003"
+Po -1 0
+$EndPAD
+$PAD
+Sh "5" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 3 "N-000005"
+Po 1 0
+$EndPAD
+$PAD
+Sh "6" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 4 "VCC"
+Po 3 0
+$EndPAD
+$PAD
+Sh "7" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 5 0
+$EndPAD
+$PAD
+Sh "8" C 1.2 1.2 0 0 0
+Dr 0.8 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po 7 0
+$EndPAD
+$EndMODULE SIL2MM-8
+$EndLIBRARY
diff --git a/96boards-uart.net b/96boards-uart.net
new file mode 100644
index 0000000..6fe6074
--- /dev/null
+++ b/96boards-uart.net
@@ -0,0 +1,145 @@
+# EESchema Netlist Version 1.1 created Sat 21 Feb 2015 17:38:28 GMT
+(
+ ( /54E6539B $noname P2 CONN_6 {Lib=CONN_6}
+ ( 1 GND )
+ ( 2 ? )
+ ( 3 VCC )
+ ( 4 /UART0_RXD_HV )
+ ( 5 /UART0_TXD_HV )
+ ( 6 ? )
+ )
+ ( /54E7D31F $noname R1 R {Lib=R}
+ ( 1 +1.8V )
+ ( 2 /UART0_RXD_LV )
+ )
+ ( /54E7D3D1 $noname R3 R {Lib=R}
+ ( 1 VCC )
+ ( 2 /UART0_RXD_HV )
+ )
+ ( /54E7D852 $noname R2 R {Lib=R}
+ ( 1 +1.8V )
+ ( 2 /UART0_TXD_LV )
+ )
+ ( /54E7D85A $noname R4 R {Lib=R}
+ ( 1 VCC )
+ ( 2 /UART0_TXD_HV )
+ )
+ ( /54E7E6E1 SOT-26 Q1 DMN601DMK {Lib=DMN601DMK}
+ ( 1 /UART0_RXD_LV )
+ ( 2 +1.8V )
+ ( 3 /UART0_TXD_HV )
+ ( 4 /UART0_TXD_LV )
+ ( 5 +1.8V )
+ ( 6 /UART0_RXD_HV )
+ )
+ ( /54E6538C $noname P1 CONN_20X2 {Lib=CONN_20X2}
+ ( 1 GND )
+ ( 2 GND )
+ ( 3 ? )
+ ( 4 ? )
+ ( 5 /UART0_TXD_LV )
+ ( 6 ? )
+ ( 7 /UART0_RXD_LV )
+ ( 8 ? )
+ ( 9 ? )
+ ( 10 ? )
+ ( 11 ? )
+ ( 12 ? )
+ ( 13 ? )
+ ( 14 ? )
+ ( 15 ? )
+ ( 16 ? )
+ ( 17 ? )
+ ( 18 ? )
+ ( 19 ? )
+ ( 20 ? )
+ ( 21 ? )
+ ( 22 ? )
+ ( 23 ? )
+ ( 24 ? )
+ ( 25 ? )
+ ( 26 ? )
+ ( 27 ? )
+ ( 28 ? )
+ ( 29 ? )
+ ( 30 ? )
+ ( 31 ? )
+ ( 32 ? )
+ ( 33 ? )
+ ( 34 ? )
+ ( 35 +1.8V )
+ ( 36 ? )
+ ( 37 ? )
+ ( 38 ? )
+ ( 39 ? )
+ ( 40 ? )
+ )
+)
+*
+{ Allowed footprints by component:
+$component R1
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$endlist
+$component R3
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$endlist
+$component R2
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$endlist
+$component R4
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$endlist
+$component Q1
+ SOT-26*
+$endlist
+$endfootprintlist
+}
+{ Pin List by Nets
+Net 14 "/UART0_TXD_LV" "UART0_TXD_LV"
+ R2 2
+ Q1 4
+ P1 5
+Net 16 "/UART0_TXD_HV" "UART0_TXD_HV"
+ Q1 3
+ R4 2
+ P2 5
+Net 17 "GND" "GND"
+ P2 1
+ P1 2
+ P1 1
+Net 29 "+1.8V" "+1.8V"
+ R1 1
+ R2 1
+ Q1 5
+ Q1 2
+ P1 35
+Net 40 "VCC" "VCC"
+ R3 1
+ R4 1
+ P2 3
+Net 43 "/UART0_RXD_HV" "UART0_RXD_HV"
+ R3 2
+ Q1 6
+ P2 4
+Net 44 "/UART0_RXD_LV" "UART0_RXD_LV"
+ R1 2
+ P1 7
+ Q1 1
+}
+#End
diff --git a/96boards-uart.pro b/96boards-uart.pro
new file mode 100644
index 0000000..472a7eb
--- /dev/null
+++ b/96boards-uart.pro
@@ -0,0 +1,88 @@
+update=Fri 20 Feb 2015 22:07:20 PST
+version=1
+last_client=pcbnew
+[cvpcb]
+version=1
+NetIExt=net
+[cvpcb/libraries]
+EquName1=devcms
+[general]
+version=1
+[eeschema]
+version=1
+LibDir=
+NetFmtName=LegacyPcbnew
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=mosfet
+[pcbnew]
+version=1
+LastNetListRead=96boards-uart.net
+UseCmpFile=1
+PadDrill=1.016000000000
+PadDrillOvalY=1.016000000000
+PadSizeH=1.524000000000
+PadSizeV=1.524000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[pcbnew/libraries]
+LibDir=
+LibName1=sockets
+LibName2=connect
+LibName3=discret
+LibName4=pin_array
+LibName5=divers
+LibName6=smd_capacitors
+LibName7=smd_resistors
+LibName8=smd_crystal&oscillator
+LibName9=smd_dil
+LibName10=smd_transistors
+LibName11=libcms
+LibName12=display
+LibName13=led
+LibName14=dip_sockets
+LibName15=pga_sockets
+LibName16=valves
+LibName17=96boards-uart
diff --git a/96boards-uart.sch b/96boards-uart.sch
new file mode 100644
index 0000000..b265680
--- /dev/null
+++ b/96boards-uart.sch
@@ -0,0 +1,317 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:mosfet
+LIBS:96boards-uart-cache
+EELAYER 27 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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diff --git a/mosfet.dcm b/mosfet.dcm
new file mode 100644
index 0000000..22ba887
--- /dev/null
+++ b/mosfet.dcm
@@ -0,0 +1,9 @@
+EESchema-DOCLIB Version 2.0 Date: Fri 20 Feb 2015 17:52:18 PST
+#
+$CMP DMN601DMK
+D DMN601DMK, 20V Vds, N-Channel Dual MOSFET, SOT-26
+K N-Channel MOSFET Logic Level
+F http://www.fairchildsemi.com/ds/BS/BSS138.pdf
+$ENDCMP
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+#End Doc Library
diff --git a/mosfet.lib b/mosfet.lib
new file mode 100644
index 0000000..a954009
--- /dev/null
+++ b/mosfet.lib
@@ -0,0 +1,73 @@
+EESchema-LIBRARY Version 2.3 Date: Fri 20 Feb 2015 17:52:18 PST
+#encoding utf-8
+#
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+#
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+F1 "BSS138" 0 150 40 H V R CNN
+F2 "SOT-23" -130 102 29 H V C CNN
+F3 "~" 0 0 60 H V C CNN
+$FPLIST
+ SOT-23*
+$ENDFPLIST
+DRAW
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+P 6 0 1 0 35 0 75 15 75 -15 35 0 40 0 40 0 F
+X G 1 -200 -50 200 R 40 40 1 1 P
+X S 2 100 -200 100 U 40 40 1 1 P
+X D 3 100 200 100 D 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# DMN601DMK
+#
+DEF DMN601DMK Q 0 0 Y Y 2 F N
+F0 "Q" 0 -149 40 H V R CNN
+F1 "DMN601DMK" 0 150 40 H V R CNN
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+$FPLIST
+ SOT-26*
+$ENDFPLIST
+DRAW
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+C 100 50 5 0 1 0 N
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+P 2 0 1 20 25 15 25 -15 N
+P 2 0 1 20 25 65 25 40 N
+P 2 0 1 0 120 15 115 10 N
+P 2 0 1 0 120 15 140 15 N
+P 2 0 1 0 140 15 145 20 N
+P 3 0 1 10 0 60 0 -60 0 -60 N
+P 4 0 1 0 30 -50 100 -50 100 -100 100 -100 N
+P 4 0 1 0 30 50 100 50 100 100 100 100 N
+P 4 0 1 0 100 50 130 50 130 -50 100 -50 N
+P 4 0 1 0 130 15 120 -10 140 -10 130 15 F
+P 5 0 1 0 30 0 50 0 100 0 100 -50 100 -50 N
+P 6 0 1 0 35 0 75 15 75 -15 35 0 40 0 40 0 F
+X S 1 100 -200 100 U 40 40 1 1 P
+X G 2 -200 -50 200 R 40 40 1 1 P
+X D 6 100 200 100 D 40 40 1 1 P
+X D 3 100 200 100 D 40 40 2 1 P
+X S 4 100 -200 100 U 40 40 2 1 P
+X G 5 -200 -50 200 R 40 40 2 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/notes b/notes
new file mode 100644
index 0000000..83edb8f
--- /dev/null
+++ b/notes
@@ -0,0 +1,8 @@
+N-Channel MOSFET DMN601DMK
+SOT26 package
+
+
+
+1- S1 6-D1
+2- G1 5-G2
+3- D2 4-S2
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-30 11:37:13 +0000