modify the dts based on dowmstream and change the delay in phy drivertopic/eth_qca8k

Signed-off-by: Vinod Koul <vkoul@kernel.org>

3 files changed, 42 insertions, 18 deletions

diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
index e59d171fa7b6..0484cbff7d87 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
@@ -56,21 +56,23 @@
 			reg = <2>;
 		};
 
-		switch0@0 {
+		switch0@16 {
 			compatible = "qca,qca8334";
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			reg = <0>;
+			reg = <16>;
 
 			ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				port@0 {
+				cpu_port1: port@0 {
 					reg = <0>;
 					label = "cpu";
 					ethernet = <&ethernet>;
 					phy-mode = "rgmii";
+					rx-delay-disable;
+					tx-delay-disable;
 					fixed-link {
 						speed = <1000>;
 						full-duplex;
@@ -78,14 +80,16 @@
 				};
 
 				port@2 {
-					reg = <2>;
+					reg = <1>;
 					label = "bottom";
+					cpu = <&cpu_port1>;
 					phy-handle = <&phy_port2>;
 				};
 
 				port@3 {
-					reg = <3>;
+					reg = <2>;
 					label = "top";
+					cpu = <&cpu_port1>;
 					phy-handle = <&phy_port3>;
 				};
 			};
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 7e97e620bd44..5dc7b44fc720 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -420,7 +420,9 @@ qca8k_mib_init(struct qca8k_priv *priv)
 static int
 qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 {
-	u32 reg;
+	u32 reg, val;
+	struct dsa_switch *ds = priv->ds;
+	bool rx_delay_disable, tx_delay_disable;
 
 	switch (port) {
 	case 0:
@@ -439,16 +441,32 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 	 */
 	switch (mode) {
 	case PHY_INTERFACE_MODE_RGMII:
+		rx_delay_disable = of_property_read_bool(ds->dst->cpu_dp->dn,
+							 "rx-delay-disable");
+		tx_delay_disable = of_property_read_bool(ds->dst->cpu_dp->dn,
+							 "tx-delay-disable");
+
+		pr_err("VK: read delays as %d:%d\n", rx_delay_disable, tx_delay_disable);
+		val = QCA8K_PORT_PAD_RGMII_EN;
+		if (!rx_delay_disable)
+			val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(3);
+		if (!tx_delay_disable)
+			val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(3);
+
+#if 0
 		qca8k_write(priv, reg,
 			    QCA8K_PORT_PAD_RGMII_EN |
 			    QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
 			    QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
+#endif
+		qca8k_write(priv, reg, val);
 
 		/* According to the datasheet, RGMII delay is enabled through
 		 * PORT5_PAD_CTRL for all ports, rather than individual port
 		 * registers
 		 */
-		qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
+		if (!rx_delay_disable)
+			qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
 			    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
 		break;
 	case PHY_INTERFACE_MODE_SGMII:
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 61db472b432f..2fa621e55207 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -110,24 +110,24 @@ static void rgmii_updatel(struct qcom_ethqos *ethqos,
 
 static void rgmii_dump(struct qcom_ethqos *ethqos)
 {
-	dev_dbg(&ethqos->pdev->dev, "Rgmii register dump\n");
-	dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n",
+	dev_err(&ethqos->pdev->dev, "Rgmii register dump\n");
+	dev_err(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n",
 		rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
-	dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
+	dev_err(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
 		rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
-	dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
+	dev_err(&ethqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
 		rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
-	dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
+	dev_err(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
 		rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
-	dev_dbg(&ethqos->pdev->dev, "SDC4_STATUS: %x\n",
+	dev_err(&ethqos->pdev->dev, "SDC4_STATUS: %x\n",
 		rgmii_readl(ethqos, SDC4_STATUS));
-	dev_dbg(&ethqos->pdev->dev, "SDCC_USR_CTL: %x\n",
+	dev_err(&ethqos->pdev->dev, "SDCC_USR_CTL: %x\n",
 		rgmii_readl(ethqos, SDCC_USR_CTL));
-	dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
+	dev_err(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
 		rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
-	dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
+	dev_err(&ethqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
 		rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
-	dev_dbg(&ethqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
+	dev_err(&ethqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
 		rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
 }
 
@@ -451,6 +451,8 @@ static void ethqos_set_phy_delay(struct mii_bus *mii, unsigned int addr)
 {
 	unsigned int data, tx_delay = 0, rx_delay = 0;
 
+	pr_err("VK: ethqos_set_phy_delay\n");
+
 	/* set phy registers with delay passed */
 	mii->write(mii, addr, PHY_DEBUG_PORT_ADDR, PHY_TX_DELAY);
 
@@ -537,7 +539,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
 	plat_dat->has_gmac4 = 1;
 	plat_dat->pmt = 1;
 	plat_dat->tso_en = of_property_read_bool(np, "snps,tso");
-	plat_dat->set_phy_quirk = ethqos_set_phy_delay;
+	//plat_dat->set_phy_quirk = ethqos_set_phy_delay;
 
 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
 	if (ret)