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-rw-r--r--ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf4
-rw-r--r--ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c266
-rw-r--r--ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf4
-rw-r--r--ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf4
-rw-r--r--ArmPkg/Library/ArmLib/Arm11/Arm11Support.S524
-rw-r--r--ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm314
6 files changed, 558 insertions, 558 deletions
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf
index b28a4578..5f24ffaf 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf
@@ -22,8 +22,8 @@
LIBRARY_CLASS = ArmLib
[Sources.common]
- ../Common/ArmLibSupport.S | GCC
- ../Common/ArmLibSupport.asm | RVCT
+ ../Common/Arm/ArmLibSupport.S | GCC
+ ../Common/Arm/ArmLibSupport.asm | RVCT
../Common/ArmLib.c
Arm11Support.S | GCC
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c b/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c
index 86427035..c683861c 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c
@@ -1,133 +1,133 @@
-/** @file
-
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Chipset/ARM1176JZ-S.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-
-VOID
-FillTranslationTable (
- IN UINT32 *TranslationTable,
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
- )
-{
- UINT32 *Entry;
- UINTN Sections;
- UINTN Index;
- UINT32 Attributes;
- UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
-
- switch (MemoryRegion->Attributes) {
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
- break;
- default:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
- break;
- }
-
- Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
- Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
-
- for (Index = 0; Index < Sections; Index++)
- {
- *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
- PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
- }
-}
-
-VOID
-EFIAPI
-ArmConfigureMmu (
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
- OUT UINTN *TranslationTableSize OPTIONAL
- )
-{
- VOID *TranslationTable;
-
- // Allocate pages for translation table.
- TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
- TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
-
- if (TranslationTableBase != NULL) {
- *TranslationTableBase = TranslationTable;
- }
-
- if (TranslationTableBase != NULL) {
- *TranslationTableSize = TRANSLATION_TABLE_SIZE;
- }
-
- ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
-
- ArmCleanInvalidateDataCache();
- ArmInvalidateInstructionCache();
- ArmInvalidateTlb();
-
- ArmDisableDataCache();
- ArmDisableInstructionCache();
- ArmDisableMmu();
-
- // Make sure nothing sneaked into the cache
- ArmCleanInvalidateDataCache();
- ArmInvalidateInstructionCache();
-
- while (MemoryTable->Length != 0) {
- FillTranslationTable(TranslationTable, MemoryTable);
- MemoryTable++;
- }
-
- ArmSetTTBR0(TranslationTable);
-
- ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
- DOMAIN_ACCESS_CONTROL_NONE(14) |
- DOMAIN_ACCESS_CONTROL_NONE(13) |
- DOMAIN_ACCESS_CONTROL_NONE(12) |
- DOMAIN_ACCESS_CONTROL_NONE(11) |
- DOMAIN_ACCESS_CONTROL_NONE(10) |
- DOMAIN_ACCESS_CONTROL_NONE( 9) |
- DOMAIN_ACCESS_CONTROL_NONE( 8) |
- DOMAIN_ACCESS_CONTROL_NONE( 7) |
- DOMAIN_ACCESS_CONTROL_NONE( 6) |
- DOMAIN_ACCESS_CONTROL_NONE( 5) |
- DOMAIN_ACCESS_CONTROL_NONE( 4) |
- DOMAIN_ACCESS_CONTROL_NONE( 3) |
- DOMAIN_ACCESS_CONTROL_NONE( 2) |
- DOMAIN_ACCESS_CONTROL_NONE( 1) |
- DOMAIN_ACCESS_CONTROL_MANAGER(0));
-
- ArmEnableInstructionCache();
- ArmEnableDataCache();
- ArmEnableMmu();
-}
-
-
-
-
+/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Chipset/ARM1176JZ-S.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+VOID
+FillTranslationTable (
+ IN UINT32 *TranslationTable,
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
+ )
+{
+ UINT32 *Entry;
+ UINTN Sections;
+ UINTN Index;
+ UINT32 Attributes;
+ UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
+
+ switch (MemoryRegion->Attributes) {
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
+ break;
+ default:
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
+ break;
+ }
+
+ Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+ Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
+
+ for (Index = 0; Index < Sections; Index++)
+ {
+ *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+ PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
+ }
+}
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
+ OUT VOID **TranslationTableBase OPTIONAL,
+ OUT UINTN *TranslationTableSize OPTIONAL
+ )
+{
+ VOID *TranslationTable;
+
+ // Allocate pages for translation table.
+ TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
+ TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
+
+ if (TranslationTableBase != NULL) {
+ *TranslationTableBase = TranslationTable;
+ }
+
+ if (TranslationTableBase != NULL) {
+ *TranslationTableSize = TRANSLATION_TABLE_SIZE;
+ }
+
+ ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
+
+ ArmCleanInvalidateDataCache();
+ ArmInvalidateInstructionCache();
+ ArmInvalidateTlb();
+
+ ArmDisableDataCache();
+ ArmDisableInstructionCache();
+ ArmDisableMmu();
+
+ // Make sure nothing sneaked into the cache
+ ArmCleanInvalidateDataCache();
+ ArmInvalidateInstructionCache();
+
+ while (MemoryTable->Length != 0) {
+ FillTranslationTable(TranslationTable, MemoryTable);
+ MemoryTable++;
+ }
+
+ ArmSetTTBR0(TranslationTable);
+
+ ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
+ DOMAIN_ACCESS_CONTROL_NONE(14) |
+ DOMAIN_ACCESS_CONTROL_NONE(13) |
+ DOMAIN_ACCESS_CONTROL_NONE(12) |
+ DOMAIN_ACCESS_CONTROL_NONE(11) |
+ DOMAIN_ACCESS_CONTROL_NONE(10) |
+ DOMAIN_ACCESS_CONTROL_NONE( 9) |
+ DOMAIN_ACCESS_CONTROL_NONE( 8) |
+ DOMAIN_ACCESS_CONTROL_NONE( 7) |
+ DOMAIN_ACCESS_CONTROL_NONE( 6) |
+ DOMAIN_ACCESS_CONTROL_NONE( 5) |
+ DOMAIN_ACCESS_CONTROL_NONE( 4) |
+ DOMAIN_ACCESS_CONTROL_NONE( 3) |
+ DOMAIN_ACCESS_CONTROL_NONE( 2) |
+ DOMAIN_ACCESS_CONTROL_NONE( 1) |
+ DOMAIN_ACCESS_CONTROL_MANAGER(0));
+
+ ArmEnableInstructionCache();
+ ArmEnableDataCache();
+ ArmEnableMmu();
+}
+
+
+
+
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf
index cd36d8b3..7239acea 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf
@@ -22,8 +22,8 @@
LIBRARY_CLASS = ArmLib
[Sources.common]
- ../Common/ArmLibSupport.S | GCC
- ../Common/ArmLibSupport.asm | RVCT
+ ../Common/Arm/ArmLibSupport.S | GCC
+ ../Common/Arm/ArmLibSupport.asm | RVCT
../Common/ArmLib.c
Arm11Support.S | GCC
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf
index 4c3566e3..e693c46d 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf
@@ -22,8 +22,8 @@
LIBRARY_CLASS = ArmLib
[Sources.common]
- ../Common/ArmLibSupport.S | GCC
- ../Common/ArmLibSupport.asm | RVCT
+ ../Common/Arm/ArmLibSupport.S | GCC
+ ../Common/Arm/ArmLibSupport.asm | RVCT
../Common/ArmLib.c
Arm11Support.S | GCC
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
index 7ff377c0..2f4be7e9 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
@@ -1,262 +1,262 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-
-.text
-.align 2
-GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
-GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
-GCC_ASM_EXPORT(ArmCleanDataCache)
-GCC_ASM_EXPORT(ArmInvalidateDataCache)
-GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
-GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
-GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
-GCC_ASM_EXPORT(ArmEnableMmu)
-GCC_ASM_EXPORT(ArmDisableMmu)
-GCC_ASM_EXPORT(ArmMmuEnabled)
-GCC_ASM_EXPORT(ArmEnableDataCache)
-GCC_ASM_EXPORT(ArmDisableDataCache)
-GCC_ASM_EXPORT(ArmEnableInstructionCache)
-GCC_ASM_EXPORT(ArmDisableInstructionCache)
-GCC_ASM_EXPORT(ArmEnableBranchPrediction)
-GCC_ASM_EXPORT(ArmDisableBranchPrediction)
-GCC_ASM_EXPORT(ArmDataMemoryBarrier)
-GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
-GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
-GCC_ASM_EXPORT(ArmSetLowVectors)
-GCC_ASM_EXPORT(ArmSetHighVectors)
-GCC_ASM_EXPORT(ArmIsMpCore)
-GCC_ASM_EXPORT(ArmCallWFI)
-GCC_ASM_EXPORT(ArmReadMpidr)
-GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
-GCC_ASM_EXPORT(ArmEnableFiq)
-GCC_ASM_EXPORT(ArmDisableFiq)
-GCC_ASM_EXPORT(ArmEnableInterrupts)
-GCC_ASM_EXPORT(ArmDisableInterrupts)
-GCC_ASM_EXPORT (ArmEnableVFP)
-
-Arm11PartNumberMask: .word 0xFFF0
-Arm11PartNumber: .word 0xB020
-
-.set DC_ON, (0x1<<2)
-.set IC_ON, (0x1<<12)
-.set XP_ON, (0x1<<23)
-.set CTRL_M_BIT, (1 << 0)
-.set CTRL_C_BIT, (1 << 2)
-.set CTRL_I_BIT, (1 << 12)
-
-ASM_PFX(ArmDisableCachesAndMmu):
- mrc p15, 0, r0, c1, c0, 0 @ Get control register
- bic r0, r0, #CTRL_M_BIT @ Disable MMU
- bic r0, r0, #CTRL_C_BIT @ Disable D Cache
- bic r0, r0, #CTRL_I_BIT @ Disable I Cache
- mcr p15, 0, r0, c1, c0, 0 @ Write control register
- bx LR
-
-ASM_PFX(ArmInvalidateInstructionAndDataTlb):
- mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
- bx lr
-
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
- bx lr
-
-
-ASM_PFX(ArmCleanDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
- bx lr
-
-
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
- bx lr
-
-
-ASM_PFX(ArmCleanDataCache):
- mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
- bx lr
-
-
-ASM_PFX(ArmCleanInvalidateDataCache):
- mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
- bx lr
-
-
-ASM_PFX(ArmInvalidateDataCache):
- mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
- bx lr
-
-
-ASM_PFX(ArmInvalidateInstructionCache):
- mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
- mov R0,#0
- mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
- bx lr
-
-ASM_PFX(ArmEnableMmu):
- mrc p15,0,R0,c1,c0,0
- orr R0,R0,#1
- mcr p15,0,R0,c1,c0,0
- bx LR
-
-ASM_PFX(ArmMmuEnabled):
- mrc p15,0,R0,c1,c0,0
- and R0,R0,#1
- bx LR
-
-ASM_PFX(ArmDisableMmu):
- mrc p15,0,R0,c1,c0,0
- bic R0,R0,#1
- mcr p15,0,R0,c1,c0,0
- mov R0,#0
- mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
- mov R0,#0
- mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
- bx LR
-
-ASM_PFX(ArmEnableDataCache):
- LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- orr R0,R0,R1 @Set C bit
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- bx LR
-
-ASM_PFX(ArmDisableDataCache):
- LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- bic R0,R0,R1 @Clear C bit
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- bx LR
-
-ASM_PFX(ArmEnableInstructionCache):
- ldr R1,=IC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- orr R0,R0,R1 @Set I bit
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- bx LR
-
-ASM_PFX(ArmDisableInstructionCache):
- ldr R1,=IC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- bic R0,R0,R1 @Clear I bit.
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- bx LR
-
-ASM_PFX(ArmEnableBranchPrediction):
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x00000800
- mcr p15, 0, r0, c1, c0, 0
- bx LR
-
-ASM_PFX(ArmDisableBranchPrediction):
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00000800
- mcr p15, 0, r0, c1, c0, 0
- bx LR
-
-ASM_PFX(ArmDataMemoryBarrier):
- mov R0, #0
- mcr P15, #0, R0, C7, C10, #5
- bx LR
-
-ASM_PFX(ArmDataSyncronizationBarrier):
- mov R0, #0
- mcr P15, #0, R0, C7, C10, #4
- bx LR
-
-ASM_PFX(ArmInstructionSynchronizationBarrier):
- mov R0, #0
- mcr P15, #0, R0, C7, C5, #4
- bx LR
-
-ASM_PFX(ArmSetLowVectors):
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
- bic r0, r0, #0x00002000 @ clear V bit
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
- bx LR
-
-ASM_PFX(ArmSetHighVectors):
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
- orr r0, r0, #0x00002000 @ clear V bit
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
- bx LR
-
-ASM_PFX(ArmIsMpCore):
- push { r1 }
- mrc p15, 0, r0, c0, c0, 0
- # Extract Part Number to check it is an ARM11MP core (0xB02)
- LoadConstantToReg (Arm11PartNumberMask, r1)
- and r0, r0, r1
- LoadConstantToReg (Arm11PartNumber, r1)
- cmp r0, r1
- movne r0, #0
- pop { r1 }
- bx lr
-
-ASM_PFX(ArmCallWFI):
- wfi
- bx lr
-
-ASM_PFX(ArmReadMpidr):
- mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
- bx lr
-
-ASM_PFX(ArmEnableFiq):
- mrs R0,CPSR
- bic R0,R0,#0x40 @Enable FIQ interrupts
- msr CPSR_c,R0
- bx LR
-
-ASM_PFX(ArmDisableFiq):
- mrs R0,CPSR
- orr R1,R0,#0x40 @Disable FIQ interrupts
- msr CPSR_c,R1
- tst R0,#0x80
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ASM_PFX(ArmEnableInterrupts):
- mrs R0,CPSR
- bic R0,R0,#0x80 @Enable IRQ interrupts
- msr CPSR_c,R0
- bx LR
-
-ASM_PFX(ArmDisableInterrupts):
- mrs R0,CPSR
- orr R1,R0,#0x80 @Disable IRQ interrupts
- msr CPSR_c,R1
- tst R0,#0x80
- moveq R0,#1
- movne R0,#0
- bx LR
-
-ASM_PFX(ArmEnableVFP):
- # Read CPACR (Coprocessor Access Control Register)
- mrc p15, 0, r0, c1, c0, 2
- # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
- orr r0, r0, #0x00f00000
- # Write back CPACR (Coprocessor Access Control Register)
- mcr p15, 0, r0, c1, c0, 2
- # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
- mov r0, #0x40000000
- #TODO: Fixme - need compilation flag
- #fmxr FPEXC, r0
- bx lr
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroIoLib.h>
+
+.text
+.align 2
+GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
+GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
+GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
+GCC_ASM_EXPORT(ArmCleanDataCache)
+GCC_ASM_EXPORT(ArmInvalidateDataCache)
+GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
+GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
+GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
+GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
+GCC_ASM_EXPORT(ArmEnableMmu)
+GCC_ASM_EXPORT(ArmDisableMmu)
+GCC_ASM_EXPORT(ArmMmuEnabled)
+GCC_ASM_EXPORT(ArmEnableDataCache)
+GCC_ASM_EXPORT(ArmDisableDataCache)
+GCC_ASM_EXPORT(ArmEnableInstructionCache)
+GCC_ASM_EXPORT(ArmDisableInstructionCache)
+GCC_ASM_EXPORT(ArmEnableBranchPrediction)
+GCC_ASM_EXPORT(ArmDisableBranchPrediction)
+GCC_ASM_EXPORT(ArmDataMemoryBarrier)
+GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
+GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
+GCC_ASM_EXPORT(ArmSetLowVectors)
+GCC_ASM_EXPORT(ArmSetHighVectors)
+GCC_ASM_EXPORT(ArmIsMpCore)
+GCC_ASM_EXPORT(ArmCallWFI)
+GCC_ASM_EXPORT(ArmReadMpidr)
+GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
+GCC_ASM_EXPORT(ArmEnableFiq)
+GCC_ASM_EXPORT(ArmDisableFiq)
+GCC_ASM_EXPORT(ArmEnableInterrupts)
+GCC_ASM_EXPORT(ArmDisableInterrupts)
+GCC_ASM_EXPORT (ArmEnableVFP)
+
+Arm11PartNumberMask: .word 0xFFF0
+Arm11PartNumber: .word 0xB020
+
+.set DC_ON, (0x1<<2)
+.set IC_ON, (0x1<<12)
+.set XP_ON, (0x1<<23)
+.set CTRL_M_BIT, (1 << 0)
+.set CTRL_C_BIT, (1 << 2)
+.set CTRL_I_BIT, (1 << 12)
+
+ASM_PFX(ArmDisableCachesAndMmu):
+ mrc p15, 0, r0, c1, c0, 0 @ Get control register
+ bic r0, r0, #CTRL_M_BIT @ Disable MMU
+ bic r0, r0, #CTRL_C_BIT @ Disable D Cache
+ bic r0, r0, #CTRL_I_BIT @ Disable I Cache
+ mcr p15, 0, r0, c1, c0, 0 @ Write control register
+ bx LR
+
+ASM_PFX(ArmInvalidateInstructionAndDataTlb):
+ mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
+ bx lr
+
+ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
+ bx lr
+
+
+ASM_PFX(ArmCleanDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
+ bx lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
+ bx lr
+
+
+ASM_PFX(ArmCleanDataCache):
+ mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
+ bx lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCache):
+ mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
+ bx lr
+
+
+ASM_PFX(ArmInvalidateDataCache):
+ mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
+ bx lr
+
+
+ASM_PFX(ArmInvalidateInstructionCache):
+ mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
+ bx lr
+
+ASM_PFX(ArmEnableMmu):
+ mrc p15,0,R0,c1,c0,0
+ orr R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ bx LR
+
+ASM_PFX(ArmMmuEnabled):
+ mrc p15,0,R0,c1,c0,0
+ and R0,R0,#1
+ bx LR
+
+ASM_PFX(ArmDisableMmu):
+ mrc p15,0,R0,c1,c0,0
+ bic R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
+ bx LR
+
+ASM_PFX(ArmEnableDataCache):
+ LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ orr R0,R0,R1 @Set C bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmDisableDataCache):
+ LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ bic R0,R0,R1 @Clear C bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmEnableInstructionCache):
+ ldr R1,=IC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ orr R0,R0,R1 @Set I bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmDisableInstructionCache):
+ ldr R1,=IC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ bic R0,R0,R1 @Clear I bit.
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmEnableBranchPrediction):
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ASM_PFX(ArmDisableBranchPrediction):
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ASM_PFX(ArmDataMemoryBarrier):
+ mov R0, #0
+ mcr P15, #0, R0, C7, C10, #5
+ bx LR
+
+ASM_PFX(ArmDataSyncronizationBarrier):
+ mov R0, #0
+ mcr P15, #0, R0, C7, C10, #4
+ bx LR
+
+ASM_PFX(ArmInstructionSynchronizationBarrier):
+ mov R0, #0
+ mcr P15, #0, R0, C7, C5, #4
+ bx LR
+
+ASM_PFX(ArmSetLowVectors):
+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
+ bic r0, r0, #0x00002000 @ clear V bit
+ mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
+ bx LR
+
+ASM_PFX(ArmSetHighVectors):
+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
+ orr r0, r0, #0x00002000 @ clear V bit
+ mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
+ bx LR
+
+ASM_PFX(ArmIsMpCore):
+ push { r1 }
+ mrc p15, 0, r0, c0, c0, 0
+ # Extract Part Number to check it is an ARM11MP core (0xB02)
+ LoadConstantToReg (Arm11PartNumberMask, r1)
+ and r0, r0, r1
+ LoadConstantToReg (Arm11PartNumber, r1)
+ cmp r0, r1
+ movne r0, #0
+ pop { r1 }
+ bx lr
+
+ASM_PFX(ArmCallWFI):
+ wfi
+ bx lr
+
+ASM_PFX(ArmReadMpidr):
+ mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
+ bx lr
+
+ASM_PFX(ArmEnableFiq):
+ mrs R0,CPSR
+ bic R0,R0,#0x40 @Enable FIQ interrupts
+ msr CPSR_c,R0
+ bx LR
+
+ASM_PFX(ArmDisableFiq):
+ mrs R0,CPSR
+ orr R1,R0,#0x40 @Disable FIQ interrupts
+ msr CPSR_c,R1
+ tst R0,#0x80
+ moveq R0,#1
+ movne R0,#0
+ bx LR
+
+ASM_PFX(ArmEnableInterrupts):
+ mrs R0,CPSR
+ bic R0,R0,#0x80 @Enable IRQ interrupts
+ msr CPSR_c,R0
+ bx LR
+
+ASM_PFX(ArmDisableInterrupts):
+ mrs R0,CPSR
+ orr R1,R0,#0x80 @Disable IRQ interrupts
+ msr CPSR_c,R1
+ tst R0,#0x80
+ moveq R0,#1
+ movne R0,#0
+ bx LR
+
+ASM_PFX(ArmEnableVFP):
+ # Read CPACR (Coprocessor Access Control Register)
+ mrc p15, 0, r0, c1, c0, 2
+ # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
+ orr r0, r0, #0x00f00000
+ # Write back CPACR (Coprocessor Access Control Register)
+ mcr p15, 0, r0, c1, c0, 2
+ # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
+ mov r0, #0x40000000
+ #TODO: Fixme - need compilation flag
+ #fmxr FPEXC, r0
+ bx lr
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
index fb3e91b7..8c270930 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
@@ -1,157 +1,157 @@
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
- EXPORT ArmCleanInvalidateDataCache
- EXPORT ArmCleanDataCache
- EXPORT ArmInvalidateDataCache
- EXPORT ArmInvalidateInstructionCache
- EXPORT ArmInvalidateDataCacheEntryByMVA
- EXPORT ArmCleanDataCacheEntryByMVA
- EXPORT ArmCleanInvalidateDataCacheEntryByMVA
- EXPORT ArmEnableMmu
- EXPORT ArmDisableMmu
- EXPORT ArmMmuEnabled
- EXPORT ArmEnableDataCache
- EXPORT ArmDisableDataCache
- EXPORT ArmEnableInstructionCache
- EXPORT ArmDisableInstructionCache
- EXPORT ArmEnableBranchPrediction
- EXPORT ArmDisableBranchPrediction
- EXPORT ArmDataMemoryBarrier
- EXPORT ArmDataSyncronizationBarrier
- EXPORT ArmInstructionSynchronizationBarrier
-
-
-DC_ON EQU ( 0x1:SHL:2 )
-IC_ON EQU ( 0x1:SHL:12 )
-XP_ON EQU ( 0x1:SHL:23 )
-
-
- AREA ArmCacheLib, CODE, READONLY
- PRESERVE8
-
-
-ArmInvalidateDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
- bx lr
-
-
-ArmCleanDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
- bx lr
-
-
-ArmCleanInvalidateDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
- bx lr
-
-
-ArmCleanDataCache
- mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
- bx lr
-
-
-ArmCleanInvalidateDataCache
- mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
- bx lr
-
-
-ArmInvalidateDataCache
- mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
- bx lr
-
-
-ArmInvalidateInstructionCache
- mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
- mov R0,#0
- mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
- bx lr
-
-ArmEnableMmu
- mrc p15,0,R0,c1,c0,0
- orr R0,R0,#1
- mcr p15,0,R0,c1,c0,0
- bx LR
-
-ArmMmuEnabled
- mrc p15,0,R0,c1,c0,0
- and R0,R0,#1
- bx LR
-
-ArmDisableMmu
- mrc p15,0,R0,c1,c0,0
- bic R0,R0,#1
- mcr p15,0,R0,c1,c0,0
- mov R0,#0
- mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
- mov R0,#0
- mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
- bx LR
-
-ArmEnableDataCache
- LDR R1,=DC_ON
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
- ORR R0,R0,R1 ;Set C bit
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
- BX LR
-
-ArmDisableDataCache
- LDR R1,=DC_ON
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
- BIC R0,R0,R1 ;Clear C bit
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
- BX LR
-
-ArmEnableInstructionCache
- LDR R1,=IC_ON
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
- ORR R0,R0,R1 ;Set I bit
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
- BX LR
-
-ArmDisableInstructionCache
- LDR R1,=IC_ON
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
- BIC R0,R0,R1 ;Clear I bit.
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
- BX LR
-
-ArmEnableBranchPrediction
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x00000800
- mcr p15, 0, r0, c1, c0, 0
- bx LR
-
-ArmDisableBranchPrediction
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00000800
- mcr p15, 0, r0, c1, c0, 0
- bx LR
-
-ASM_PFX(ArmDataMemoryBarrier):
- mov R0, #0
- mcr P15, #0, R0, C7, C10, #5
- bx LR
-
-ASM_PFX(ArmDataSyncronizationBarrier):
- mov R0, #0
- mcr P15, #0, R0, C7, C10, #4
- bx LR
-
-ASM_PFX(ArmInstructionSynchronizationBarrier):
- MOV R0, #0
- MCR P15, #0, R0, C7, C5, #4
- bx LR
-
- END
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+ EXPORT ArmCleanInvalidateDataCache
+ EXPORT ArmCleanDataCache
+ EXPORT ArmInvalidateDataCache
+ EXPORT ArmInvalidateInstructionCache
+ EXPORT ArmInvalidateDataCacheEntryByMVA
+ EXPORT ArmCleanDataCacheEntryByMVA
+ EXPORT ArmCleanInvalidateDataCacheEntryByMVA
+ EXPORT ArmEnableMmu
+ EXPORT ArmDisableMmu
+ EXPORT ArmMmuEnabled
+ EXPORT ArmEnableDataCache
+ EXPORT ArmDisableDataCache
+ EXPORT ArmEnableInstructionCache
+ EXPORT ArmDisableInstructionCache
+ EXPORT ArmEnableBranchPrediction
+ EXPORT ArmDisableBranchPrediction
+ EXPORT ArmDataMemoryBarrier
+ EXPORT ArmDataSyncronizationBarrier
+ EXPORT ArmInstructionSynchronizationBarrier
+
+
+DC_ON EQU ( 0x1:SHL:2 )
+IC_ON EQU ( 0x1:SHL:12 )
+XP_ON EQU ( 0x1:SHL:23 )
+
+
+ AREA ArmCacheLib, CODE, READONLY
+ PRESERVE8
+
+
+ArmInvalidateDataCacheEntryByMVA
+ mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
+ bx lr
+
+
+ArmCleanDataCacheEntryByMVA
+ mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
+ bx lr
+
+
+ArmCleanInvalidateDataCacheEntryByMVA
+ mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
+ bx lr
+
+
+ArmCleanDataCache
+ mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
+ bx lr
+
+
+ArmCleanInvalidateDataCache
+ mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
+ bx lr
+
+
+ArmInvalidateDataCache
+ mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
+ bx lr
+
+
+ArmInvalidateInstructionCache
+ mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
+ bx lr
+
+ArmEnableMmu
+ mrc p15,0,R0,c1,c0,0
+ orr R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ bx LR
+
+ArmMmuEnabled
+ mrc p15,0,R0,c1,c0,0
+ and R0,R0,#1
+ bx LR
+
+ArmDisableMmu
+ mrc p15,0,R0,c1,c0,0
+ bic R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
+ bx LR
+
+ArmEnableDataCache
+ LDR R1,=DC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ ORR R0,R0,R1 ;Set C bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmDisableDataCache
+ LDR R1,=DC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ BIC R0,R0,R1 ;Clear C bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmEnableInstructionCache
+ LDR R1,=IC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ ORR R0,R0,R1 ;Set I bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmDisableInstructionCache
+ LDR R1,=IC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ BIC R0,R0,R1 ;Clear I bit.
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmEnableBranchPrediction
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ArmDisableBranchPrediction
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ASM_PFX(ArmDataMemoryBarrier):
+ mov R0, #0
+ mcr P15, #0, R0, C7, C10, #5
+ bx LR
+
+ASM_PFX(ArmDataSyncronizationBarrier):
+ mov R0, #0
+ mcr P15, #0, R0, C7, C10, #4
+ bx LR
+
+ASM_PFX(ArmInstructionSynchronizationBarrier):
+ MOV R0, #0
+ MCR P15, #0, R0, C7, C5, #4
+ bx LR
+
+ END
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-08 13:31:28 +0000