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-rw-r--r--OvmfPkg/AcpiTables/Dsdt.asl46
-rw-r--r--OvmfPkg/AcpiTables/Facp.aslc46
-rw-r--r--OvmfPkg/AcpiTables/Platform.h34
3 files changed, 96 insertions, 30 deletions
diff --git a/OvmfPkg/AcpiTables/Dsdt.asl b/OvmfPkg/AcpiTables/Dsdt.asl
index 12a4f142..519a3125 100644
--- a/OvmfPkg/AcpiTables/Dsdt.asl
+++ b/OvmfPkg/AcpiTables/Dsdt.asl
@@ -203,10 +203,28 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 4) {
Package () {0x0000FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},
Package () {0x0000FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},
- Package () {0x0001FFFF, 0x00, 0x00, 0x09},
//
- // list of IRQs occupied thus far: 9
+ // Bus 0, Device 1, Pin 0 (INTA) is special; it corresponds to the
+ // internally generated SCI (System Control Interrupt), which is
+ // always routed to GSI 9. By setting the third (= Source) field to
+ // zero, we could use the fourth (= Source Index) field to hardwire
+ // the pin to GSI 9 directly.
+ //
+ // That way however, in accordance with the ACPI spec's description
+ // of SCI, the interrupt would be treated as "active low,
+ // shareable, level", and that doesn't match qemu.
//
+ // In QemuInstallAcpiMadtTable() [OvmfPkg/AcpiPlatformDxe/Qemu.c]
+ // we install an Interrupt Override Structure for the identity
+ // mapped IRQ#9 / GSI 9 (the corresponding bit being set in
+ // Pcd8259LegacyModeEdgeLevel), which describes the correct
+ // polarity (active high). As a consequence, some OS'en (eg. Linux)
+ // override the default (active low) polarity originating from the
+ // _PRT; others (eg. FreeBSD) don't. Therefore we need a separate
+ // link device just to specify a polarity that matches the MADT.
+ //
+ Package () {0x0001FFFF, 0x00, \_SB.PCI0.LPC.LNKS, 0x00},
+
Package () {0x0001FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},
Package () {0x0001FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},
Package () {0x0001FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},
@@ -292,6 +310,30 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 4) {
Name (_ADR, 0x00010000)
//
+ // The SCI cannot be rerouted or disabled with PIRQRC[A:D]; we only
+ // need this link device in order to specify the polarity.
+ //
+ Device (LNKS) {
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 0)
+
+ Name (_STA, 0xB) // 0x1: device present
+ // 0x2: enabled and decoding resources
+ // 0x8: functioning properly
+
+ Method (_SRS, 1, NotSerialized) { /* no-op */ }
+ Method (_DIS, 0, NotSerialized) { /* no-op */ }
+
+ Name (_PRS, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { 9 }
+ //
+ // list of IRQs occupied thus far: 9
+ //
+ })
+ Method (_CRS, 0, NotSerialized) { Return (_PRS) }
+ }
+
+ //
// PCI Interrupt Routing Configuration Registers, PIRQRC[A:D]
//
OperationRegion (PRR0, PCI_Config, 0x60, 0x04)
diff --git a/OvmfPkg/AcpiTables/Facp.aslc b/OvmfPkg/AcpiTables/Facp.aslc
index b48af760..df35285c 100644
--- a/OvmfPkg/AcpiTables/Facp.aslc
+++ b/OvmfPkg/AcpiTables/Facp.aslc
@@ -1,6 +1,7 @@
/** @file
FACP Table
+ Copyright (c) 2013, Red Hat, Inc.
Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are
licensed and made available under the terms and conditions of the BSD License
@@ -14,11 +15,11 @@
#include "Platform.h"
-EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
+EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
{
- EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),
- EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
0, // to make sum of entire table == 0
{EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field
EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
@@ -28,8 +29,8 @@ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
},
0, // Physical addesss of FACS
0, // Physical address of DSDT
- INT_MODEL, // System Interrupt Model
- RESERVED, // reserved
+ RESERVED, // System Interrupt Model in ACPI 1.0, eliminated in 2.0
+ EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED, // Preferred PM profile
SCI_INT_VECTOR, // System vector of SCI interrupt
SMI_CMD_IO_PORT, // Port address of SMI command port
ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
@@ -37,20 +38,20 @@ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
0, // PState control
PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk
- PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk
+ 0, // Power Mgt 1b Event Reg Blk unsupported
PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk
- PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk
- PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk
+ 0, // Power Mgt 1b Ctrl Reg Blk unsupported
+ 0, // Power Mgt 2 Ctrl Reg Blk unsupported
PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk
GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk
- GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk
+ 0, // General Purpose Event 1 Reg Blk unsupported
PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
- PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk
+ 0, // Power Mgt 2 Ctrl Reg Blk unsupported
PM_TM_LEN, // Byte Length of ports at pm_tm_blk
GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
- GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
- GPE1_BASE, // offset in gpe model where gpe1 events start
+ 0, // General Purpose Event 1 Reg Blk unsupported
+ 0, // General Purpose Event 1 Reg Blk unsupported
0, // _CST support
P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
@@ -61,10 +62,23 @@ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
CENTURY, // index to century in RTC CMOS RAM
- 0x00, // Boot architecture flag
- 0x00, // Boot architecture flag
+ 0x0000, // Boot architecture flag (16-bit)
RESERVED, // reserved
- FLAG
+ FLAG, // Fixed feature flags
+ GAS2_IO(RESET_REG, 1), // Extended address of the Reset Register
+ RESET_VALUE, // Value for the Reset Register to reset the system
+ { RESERVED }, // reserved[3]
+ 0, // 64-bit physical addesss of FACS, set at installation
+ 0, // 64-bit physical addesss of DSDT, set at installation
+
+ GAS2_IO(PM1a_EVT_BLK, PM1_EVT_LEN), // Ext. addr. of PM 1a Event Reg Blk
+ { 0 }, // PM 1b Event Reg Blk unsupported
+ GAS2_IO(PM1a_CNT_BLK, PM1_CNT_LEN), // Ext. addr. of PM 1a Ctrl Reg Blk
+ { 0 }, // PM 1b Ctrl Reg Blk unsupported
+ { 0 }, // PM 2 Ctrl Reg Blk unsupported
+ GAS2_IO(PM_TMR_BLK, PM_TM_LEN), // Ext. addr. of PM Timer Ctrl Reg Blk
+ GAS2_IO(GPE0_BLK, GPE0_BLK_LEN), // Ext. addr. of GPE 0 Reg Blk
+ { 0 } // GPE 1 Reg Blk unsupported
};
diff --git a/OvmfPkg/AcpiTables/Platform.h b/OvmfPkg/AcpiTables/Platform.h
index e8fae3c8..d96b8472 100644
--- a/OvmfPkg/AcpiTables/Platform.h
+++ b/OvmfPkg/AcpiTables/Platform.h
@@ -1,6 +1,7 @@
/** @file
Platform specific defines for constructing ACPI tables
+ Copyright (c) 2012, 2013, Red Hat, Inc.
Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are
licensed and made available under the terms and conditions of the BSD License
@@ -23,31 +24,23 @@
//
#define EFI_ACPI_OEM_ID 'O','V','M','F',' ',' ' // OEMID 6 bytes long
#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('O','V','M','F','E','D','K','2') // OEM table id 8 bytes long
-#define EFI_ACPI_OEM_REVISION 0x20120804
+#define EFI_ACPI_OEM_REVISION 0x20130221
#define EFI_ACPI_CREATOR_ID SIGNATURE_32('O','V','M','F')
-#define EFI_ACPI_CREATOR_REVISION 0x00000098
+#define EFI_ACPI_CREATOR_REVISION 0x00000099
-#define INT_MODEL 0x01
#define SCI_INT_VECTOR 0x0009
#define SMI_CMD_IO_PORT 0xB2
#define ACPI_ENABLE 0xF1
#define ACPI_DISABLE 0xF0
#define S4BIOS_REQ 0x00
#define PM1a_EVT_BLK 0x0000b000
-#define PM1b_EVT_BLK 0x00000000
#define PM1a_CNT_BLK 0x0000b004
-#define PM1b_CNT_BLK 0x00000000
-#define PM2_CNT_BLK 0x00000000
#define PM_TMR_BLK 0x0000b008
#define GPE0_BLK 0x0000afe0
-#define GPE1_BLK 0x00000000
#define PM1_EVT_LEN 0x04
#define PM1_CNT_LEN 0x02
-#define PM2_CNT_LEN 0x00
#define PM_TM_LEN 0x04
#define GPE0_BLK_LEN 0x04
-#define GPE1_BLK_LEN 0x00
-#define GPE1_BASE 0x00
#define RESERVED 0x00
#define P_LVL2_LAT 0x0065
#define P_LVL3_LAT 0x03E9
@@ -58,7 +51,24 @@
#define DAY_ALRM 0x00
#define MON_ALRM 0x00
#define CENTURY 0x00
-#define FLAG EFI_ACPI_1_0_WBINVD | EFI_ACPI_1_0_PROC_C1 | EFI_ACPI_1_0_SLP_BUTTON | EFI_ACPI_1_0_RTC_S4
+#define FLAG (EFI_ACPI_2_0_WBINVD | \
+ EFI_ACPI_2_0_PROC_C1 | \
+ EFI_ACPI_2_0_SLP_BUTTON | \
+ EFI_ACPI_2_0_RTC_S4 | \
+ EFI_ACPI_2_0_RESET_REG_SUP)
+#define RESET_REG 0xCF9
+#define RESET_VALUE (BIT2 | BIT1) // PIIX3 Reset CPU + System Reset
-#endif
+//
+// Byte-aligned IO port register block initializer for
+// EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE
+//
+#define GAS2_IO(Base, Size) { \
+ EFI_ACPI_2_0_SYSTEM_IO, /* AddressSpaceId */ \
+ (Size) * 8, /* RegisterBitWidth */ \
+ 0, /* RegisterBitOffset */ \
+ 0, /* Reserved */ \
+ (Base) /* Address */ \
+ }
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 01:17:20 +0000