diff options
| author | Greg Bellows <greg.bellows@linaro.org> | 2015-04-08 13:49:29 -0500 |
|---|---|---|
| committer | Greg Bellows <greg.bellows@linaro.org> | 2015-04-08 13:49:29 -0500 |
| commit | 66e359186aed6734487088d491e661ecba1f11c1 (patch) | |
| tree | c1aa60568863ca52d11cfdf7762c4663b858318c | |
| parent | 976633914622721116902c94e46b1f17e379b2f1 (diff) | |
Add EL1 undefined instruction handler
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
| -rw-r--r-- | arm/el1_common/el1_exception.S | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/arm/el1_common/el1_exception.S b/arm/el1_common/el1_exception.S index e05523e..1b871d7 100644 --- a/arm/el1_common/el1_exception.S +++ b/arm/el1_common/el1_exception.S @@ -9,8 +9,8 @@ .global el1_vectors el1_vectors: b . /* Unused */ - b . /* Unused */ - b el1_svc_vect /* System call */ + b el1_undef_vect /* Undefined instr */ + b el1_svc_vect /* System call */ b el1_iabort_vect /* Prefetch abort */ b el1_dabort_vect /* Data abort */ b . /* Unused */ @@ -45,3 +45,14 @@ el1_dabort_vect: bl el1_handle_exception pop {r0-r3} rfefd sp! + +el1_undef_vect: + srsdb sp!, #CPSR_MODE_UND + push {r0-r3} + mov r0, #EC_UNKNOWN /* Treat ARMv7 iaborts as at same level */ + mrc p15, 0, r1, c5, c0, 0 /* ISS = DFSR on ARMv7 */ + mrc p15, 0, r2, c6, c0, 0 /* DFAR */ + ldr r3, [sp, #16] /* Jump back over the saved args for LR */ + bl el1_handle_exception + pop {r0-r3} + rfefd sp! |