Merge branch 'tracking-qcomlt-arm64' into integration-linux-qcomlt

* tracking-qcomlt-arm64: (31 commits)
  defconfig: bt: Disable old SMD TTY for BT and enable new HCI BT.
  arm64: dma-mapping: map sg lists into the SMMU as virtually contiguous
  arm64: dma-mapping: fix DMA_ATTR_STRONGLY_ORDERED in __get_dma_pgprot
  arm64: mm: Fix a bug in iommu dma-mapping
  arm64: dma-mapping: add support for IOMMU mapper
  arm64: Add support for DMA_ATTR_STRONGLY_ORDERED
  arm: Add option to skip buffer zeroing
  common: DMA-mapping: Add strongly ordered memory attribute
  arm64: defconfig: add missing QCOM specific configs
  defconfig: add tsens and spmi regulator support
  arm64: defconfig: Enable drivers for WCNSS
  arm64: defconfig: qcom: enable iommu v1 in defconfig
  arm64: defconfig:  Enable CPU frequency scaling
  arm64: defconfig: Enable CPR driver
  arm64: defconfig: Enable SPMI regulator driver
  arm64: defconfig: Enable A53 CPU clock
  arm64: defconfig: Clean-up defconfig with savedefconfig
  arm64: defconfig: remove 8064 rpm clock controller selection.
  arm64: defconfig: Enable LED drivers
  arm64: Enable Qualcomm SMEM, RPM, and SMD drivers
  ...

3 files changed, 30 insertions, 0 deletions

diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt
index 18dc52c4f2a0..9ac45c33c568 100644
--- a/Documentation/DMA-attributes.txt
+++ b/Documentation/DMA-attributes.txt
@@ -100,3 +100,12 @@ allocated by dma_alloc_attrs() function from individual pages if it can
 be mapped as contiguous chunk into device dma address space. By
 specifying this attribute the allocated buffer is forced to be contiguous
 also in physical memory.
+
+DMA_ATTR_STRONGLY_ORDERED
+-------------------------
+
+DMA_ATTR_STRONGLY_ORDERED allocates memory with a very restrictive type
+of mapping (no unaligned accesses, no re-ordering, no write merging, no
+buffering, no pre-fetching). This has severe performance penalties and
+should not be used for general purpose DMA allocations. It should only
+be used if one of the restrictions on strongly ordered memory is required.
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c478d0..259c50f0a720 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -185,6 +185,8 @@ nodes to be present and contain the properties described below.
 			  be one of:
 			     "psci"
 			     "spin-table"
+			     "qcom,arm-cortex-acc"
+
 			# On ARM 32-bit systems this property is optional and
 			  can be one of:
 			    "allwinner,sun6i-a31"
diff --git a/Documentation/devicetree/bindings/arm/msm/acc.txt b/Documentation/devicetree/bindings/arm/msm/acc.txt
new file mode 100644
index 000000000000..ae2d7253b363
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/acc.txt
@@ -0,0 +1,19 @@
+Application Processor Sub-system (APSS) Application Clock Controller (ACC)
+
+The ACC provides clock, power domain, and reset control to a CPU. There is one ACC
+register region per CPU within the APSS remapped region as well as an alias register
+region that remaps accesses to the ACC associated with the CPU accessing the region.
+
+Required properties:
+- compatible:		Must be "qcom,arm-cortex-acc"
+- reg:			The first element specifies the base address and size of
+			the register region. An optional second element specifies
+			the base address and size of the alias register region.
+
+Example:
+
+	clock-controller@b088000 {
+		compatible = "qcom,arm-cortex-acc";
+		reg = <0x0b088000 0x1000>,
+		      <0x0b008000 0x1000>;
+	}