diff options
| author | Kevin Peng <kevin.peng@arm.com> | 2021-08-12 17:40:17 +0800 |
|---|---|---|
| committer | Kevin Peng <kevin.peng@arm.com> | 2021-09-13 11:23:32 +0800 |
| commit | 300c68da11fda3669d7b80b68dcd67b0b2082cbc (patch) | |
| tree | a3e0cc35b8e7966b94631028d50f91c8c2f6a49e | |
| parent | e863e5ce570c9a76f633a765b22f1d608e24e75a (diff) | |
SPM: Use Main Stack for initialization
On reset, the Main Stack is used by default.
TF-M changes the stack to Processor Stack.
This patch remove the change to PSP in startup.s and:
- Rename the ARM_LIB_STACK to ER_INITIAL_PSP
- Rename the ARM_LIB_STACK_MSP to ARM_LIB_STACK
The renaming is to align the __main function of ARMClang where the
ARM_LIB_STACK is set to the current SP (MSP)
For Library Mode, the stacks are set to back to use PSP before entering
c code to avoid massive corresponding changes.
For FF-M implementations, this patch also:
- Seal the Main Stack before entering c code
- Manually free the Main Stack usage after initialization as the init
function does not return
Change-Id: Ie1b6f2fca1f774c4812a89fa45bb039b16fe5af0
Signed-off-by: Kevin Peng <kevin.peng@arm.com>
Co-authored-by: Summer Qin <summer.qin@arm.com>
63 files changed, 294 insertions, 416 deletions
diff --git a/platform/ext/common/armclang/tfm_common_s.sct b/platform/ext/common/armclang/tfm_common_s.sct index c68fd6292..cce157329 100644 --- a/platform/ext/common/armclang/tfm_common_s.sct +++ b/platform/ext/common/armclang/tfm_common_s.sct @@ -116,19 +116,19 @@ LR_CODE S_CODE_START S_CODE_SIZE { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } # if !defined(TFM_PSA_API) /* PSP is unprivileged in single-core topology. Reserve 8 bytes for seal */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE - 0x8 { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE - 0x8 { } - ARM_LIB_STACK_SEAL +0 EMPTY 0x8 { + ER_INITIAL_PSP_SEAL +0 EMPTY 0x8 { } # else /* PSP is unprivileged in single-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } # endif /* !defined(TFM_PSA_API) */ #endif @@ -181,11 +181,11 @@ LR_CODE S_CODE_START S_CODE_SIZE { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } /* PSP is privileged in multi-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } #endif diff --git a/platform/ext/common/armclang/tfm_isolation_l3.sct.template b/platform/ext/common/armclang/tfm_isolation_l3.sct.template index c546061e0..3c0a23cc6 100644 --- a/platform/ext/common/armclang/tfm_isolation_l3.sct.template +++ b/platform/ext/common/armclang/tfm_isolation_l3.sct.template @@ -124,7 +124,7 @@ LR_CODE S_CODE_START { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { @@ -185,7 +185,7 @@ LR_CODE S_CODE_START { } /* PSP is unprivileged in single-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } {% for partition in partitions %} diff --git a/platform/ext/common/gcc/tfm_common_s.ld b/platform/ext/common/gcc/tfm_common_s.ld index 75de32d15..f2cd42542 100644 --- a/platform/ext/common/gcc/tfm_common_s.ld +++ b/platform/ext/common/gcc/tfm_common_s.ld @@ -248,8 +248,8 @@ SECTIONS { . += __msp_init_stack_size__; } > RAM - Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack); - Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); /* PSP is unprivileged in single-core topology */ .psp_stack : ALIGN(32) @@ -260,16 +260,16 @@ SECTIONS . += (__psp_stack_size__); # endif } > RAM - Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); - Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Base = ADDR(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); # if !defined(TFM_PSA_API) .psp_stack_seal_res : { . += 0x8; } > RAM - Image$$ARM_LIB_STACK_SEAL$$ZI$$Base = ADDR(.psp_stack_seal_res); - Image$$ARM_LIB_STACK_SEAL$$ZI$$Limit = ADDR(.psp_stack_seal_res) + SIZEOF(.psp_stack_seal_res); + Image$$ER_INITIAL_PSP_SEAL$$ZI$$Base = ADDR(.psp_stack_seal_res); + Image$$ER_INITIAL_PSP_SEAL$$ZI$$Limit = ADDR(.psp_stack_seal_res) + SIZEOF(.psp_stack_seal_res); # endif #endif @@ -400,16 +400,16 @@ SECTIONS { . += __msp_init_stack_size__; } > RAM - Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack); - Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); /* PSP is privileged in multi-core topology */ .psp_stack : ALIGN(32) { . += __psp_stack_size__; } > RAM - Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); - Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Base = ADDR(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); #endif /**** PSA RoT DATA start here */ @@ -577,5 +577,5 @@ SECTIONS Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); + PROVIDE(__stack = Image$$ER_INITIAL_PSP$$ZI$$Limit); } diff --git a/platform/ext/common/gcc/tfm_isolation_l3.ld.template b/platform/ext/common/gcc/tfm_isolation_l3.ld.template index 14ef0cabb..3b46bf9d3 100644 --- a/platform/ext/common/gcc/tfm_isolation_l3.ld.template +++ b/platform/ext/common/gcc/tfm_isolation_l3.ld.template @@ -271,8 +271,8 @@ SECTIONS { . += __msp_init_stack_size__; } > RAM - Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack); - Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); /**** PSA RoT DATA start here */ {% for partition in partitions %} @@ -346,8 +346,8 @@ SECTIONS { . += (__psp_stack_size__); } > RAM - Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); - Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Base = ADDR(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); /**** APPLICATION RoT DATA start here */ {% for partition in partitions %} @@ -532,5 +532,5 @@ SECTIONS Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); + PROVIDE(__stack = Image$$ER_INITIAL_PSP$$ZI$$Limit); } diff --git a/platform/ext/common/iar/tfm_common_s.icf b/platform/ext/common/iar/tfm_common_s.icf index 3da205dd3..2286a5254 100644 --- a/platform/ext/common/iar/tfm_common_s.icf +++ b/platform/ext/common/iar/tfm_common_s.icf @@ -94,18 +94,18 @@ define block TFM_SECURE_DATA_START with size = 0 { }; #ifndef TFM_MULTI_CORE_TOPOLOGY /* Shared area between BL2 and runtime to exchange data */ define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { }; -define block ARM_LIB_STACK_MSP with alignment = 32, size = S_MSP_STACK_SIZE { }; +define block ARM_LIB_STACK with alignment = 32, size = S_MSP_STACK_SIZE { }; define overlay STACK_DATA {block TFM_SHARED_DATA}; -define overlay STACK_DATA {block ARM_LIB_STACK_MSP}; +define overlay STACK_DATA {block ARM_LIB_STACK}; # if !defined(TFM_PSA_API) /* Reserve space for stack seal (8 bytes) */ -define block ARM_LIB_STACK with alignment = 32, size = S_PSP_STACK_SIZE - 0x8 { }; -define block ARM_LIB_STACK_SEAL with size = 0x8 { }; +define block ER_INITIAL_PSP with alignment = 32, size = S_PSP_STACK_SIZE - 0x8 { }; +define block ER_INITIAL_PSP_SEAL with size = 0x8 { }; # else -define block ARM_LIB_STACK with alignment = 32, size = S_PSP_STACK_SIZE { }; +define block ER_INITIAL_PSP with alignment = 32, size = S_PSP_STACK_SIZE { }; # endif -keep {block TFM_SHARED_DATA, block ARM_LIB_STACK_MSP}; +keep {block TFM_SHARED_DATA, block ARM_LIB_STACK}; #endif #if !defined(TFM_PSA_API) @@ -146,14 +146,14 @@ define block TFM_SECURE_PRIV_DATA_BOUNDARY with size = 0 { }; define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { }; /* MSP */ -define block ARM_LIB_STACK_MSP with alignment = 32, size = S_MSP_STACK_SIZE { }; +define block ARM_LIB_STACK with alignment = 32, size = S_MSP_STACK_SIZE { }; define overlay STACK_DATA {block TFM_SHARED_DATA}; -define overlay STACK_DATA {block ARM_LIB_STACK_MSP}; +define overlay STACK_DATA {block ARM_LIB_STACK}; /* PSP is privileged in multi-core topology */ -define block ARM_LIB_STACK with alignment = 32, size = S_PSP_STACK_SIZE { }; -keep {block TFM_SHARED_DATA, block ARM_LIB_STACK_MSP}; +define block ER_INITIAL_PSP with alignment = 32, size = S_PSP_STACK_SIZE { }; +keep {block TFM_SHARED_DATA, block ARM_LIB_STACK}; #endif define block HEAP with alignment = 8, size = S_HEAP_SIZE { }; @@ -272,10 +272,10 @@ define block DATA with fixed order { /* Shared area between BL2 and runtime to exchange data */ overlay STACK_DATA, /* PSP is unprivileged in single-core topology */ - block ARM_LIB_STACK, + block ER_INITIAL_PSP, # if !defined(TFM_PSA_API) /* Define stack seal block for Library mode */ - block ARM_LIB_STACK_SEAL, + block ER_INITIAL_PSP_SEAL, # endif #endif @@ -317,7 +317,7 @@ define block PRIV_DATA with fixed order { /* Shared area between BL2 and runtime to exchange data */ overlay STACK_DATA, /* PSP is privileged in multi-core topology */ - block ARM_LIB_STACK, + block ER_INITIAL_PSP, #endif overlay HEAP_OVL, diff --git a/platform/ext/target/arm/diphda/Device/Source/gcc/startup_diphda_s.S b/platform/ext/target/arm/diphda/Device/Source/gcc/startup_diphda_s.S index 28b097979..dd7a8defa 100644 --- a/platform/ext/target/arm/diphda/Device/Source/gcc/startup_diphda_s.S +++ b/platform/ext/target/arm/diphda/Device/Source/gcc/startup_diphda_s.S @@ -25,7 +25,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit/* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* -14 NMI Handler */ .long HardFault_Handler /* -13 Hard Fault Handler */ @@ -215,12 +215,6 @@ Reset_Handler: bl SystemInit - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 #ifndef __START #define __START _start diff --git a/platform/ext/target/arm/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s b/platform/ext/target/arm/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s index 2bcbb6702..fcc94d685 100644 --- a/platform/ext/target/arm/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s +++ b/platform/ext/target/arm/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2018 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -25,7 +25,6 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -37,7 +36,7 @@ PRESERVE8 -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -168,14 +167,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S b/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S index aca6a49af..e151ab6fe 100644 --- a/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S +++ b/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 ARM Limited +; * Copyright (c) 2009-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit/* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -310,13 +310,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s b/platform/ext/target/arm/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s index d1043e92c..149c8a384 100644 --- a/platform/ext/target/arm/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s +++ b/platform/ext/target/arm/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2020 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -28,7 +28,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -43,7 +42,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -171,14 +170,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__iar_program_start BX R0 diff --git a/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c b/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c index a396e51ab..8778592b6 100644 --- a/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c +++ b/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,8 +33,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -64,8 +64,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/platform/ext/target/arm/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s b/platform/ext/target/arm/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s index 23f2cc88d..5db755f21 100644 --- a/platform/ext/target/arm/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s +++ b/platform/ext/target/arm/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2018 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -25,7 +25,7 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -34,7 +34,7 @@ EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -165,9 +165,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S b/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S index b2063174d..5f2e23af5 100644 --- a/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S +++ b/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 ARM Limited +; * Copyright (c) 2009-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -272,12 +272,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s b/platform/ext/target/arm/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s index 713f22ce7..52f8fe95c 100644 --- a/platform/ext/target/arm/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s +++ b/platform/ext/target/arm/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2020 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -28,7 +28,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -43,7 +42,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -171,11 +170,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MSR PSP, R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__iar_program_start BX R0 diff --git a/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c b/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c index dfafd3909..77ece5f6b 100644 --- a/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c +++ b/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c @@ -76,8 +76,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -107,8 +107,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/platform/ext/target/arm/mps2/fvp_sse300/device/source/startup_fvp_sse300_mps2_s.c b/platform/ext/target/arm/mps2/fvp_sse300/device/source/startup_fvp_sse300_mps2_s.c index 8c6046fb2..54be0ac56 100644 --- a/platform/ext/target/arm/mps2/fvp_sse300/device/source/startup_fvp_sse300_mps2_s.c +++ b/platform/ext/target/arm/mps2/fvp_sse300/device/source/startup_fvp_sse300_mps2_s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -33,15 +33,12 @@ typedef void( *pFunc )( void ); External References *----------------------------------------------------------------------------*/ -#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit) -#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base) +#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit) +#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base) extern uint32_t __MSP_INITIAL_SP; extern uint32_t __MSP_STACK_LIMIT; -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; - extern void __PROGRAM_START(void) __NO_RETURN; /*---------------------------------------------------------------------------- @@ -234,11 +231,6 @@ void Reset_Handler(void) __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT)); SystemInit(); /* CMSIS System Initialization */ - __ASM volatile("MRS R0, control\n" /* Get control value */ - "ORR R0, R0, #2\n" /* Select switch to PSP */ - "MSR control, R0\n" /* Load control register */ - : - : - : "r0"); + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } diff --git a/platform/ext/target/arm/mps2/fvp_sse300/tfm_hal_isolation.c b/platform/ext/target/arm/mps2/fvp_sse300/tfm_hal_isolation.c index 4cbce3014..7f18a882c 100644 --- a/platform/ext/target/arm/mps2/fvp_sse300/tfm_hal_isolation.c +++ b/platform/ext/target/arm/mps2/fvp_sse300/tfm_hal_isolation.c @@ -33,8 +33,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -70,8 +70,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/platform/ext/target/arm/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s b/platform/ext/target/arm/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s index ff9a8d322..cfdd1313c 100644 --- a/platform/ext/target/arm/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s +++ b/platform/ext/target/arm/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2019 Arm Limited. All rights reserved. +; * Copyright (c) 2016-2021 Arm Limited. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -25,7 +25,7 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -35,7 +35,7 @@ EXPORT __Vectors_Size __Vectors - DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -200,9 +200,6 @@ Reset_Handler \ CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S b/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S index b8fb9302f..18a4fd4cf 100644 --- a/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S +++ b/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -28,7 +28,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -306,12 +306,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s b/platform/ext/target/arm/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s index 855a7af8e..6064861c7 100644 --- a/platform/ext/target/arm/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s +++ b/platform/ext/target/arm/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s @@ -28,7 +28,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -43,7 +42,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -204,11 +203,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MSR PSP, R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__iar_program_start BX R0 diff --git a/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c index 0f27cba96..a4ad8caf6 100644 --- a/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c +++ b/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -30,8 +30,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -88,9 +88,9 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) /* NSPM PSP */ region_cfg.region_nr = MPU_REGION_NS_STACK; region_cfg.region_base = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); region_cfg.region_limit = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; diff --git a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c index afb5df25f..5d914030b 100644 --- a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c +++ b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c @@ -33,15 +33,12 @@ typedef void( *pFunc )( void ); External References *----------------------------------------------------------------------------*/ -#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit) -#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base) +#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit) +#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base) extern uint32_t __MSP_INITIAL_SP; extern uint32_t __MSP_STACK_LIMIT; -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; - extern void __PROGRAM_START(void) __NO_RETURN; /*---------------------------------------------------------------------------- @@ -346,14 +343,8 @@ extern const pFunc __VECTOR_TABLE[496]; void Reset_Handler(void) { __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT)); - __set_MSP((uint32_t)(&__MSP_INITIAL_SP)); SystemInit(); /* CMSIS System Initialization */ - __ASM volatile("MRS R0, control\n" /* Get control value */ - "ORR R0, R0, #2\n" /* Select switch to PSP */ - "MSR control, R0\n" /* Load control register */ - : - : - : "r0"); + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } diff --git a/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c index 419ad0fe0..20c1c0510 100644 --- a/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c +++ b/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c @@ -33,8 +33,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -70,8 +70,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/armclang/startup_musca_b1_secure_enclave_s.s b/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/armclang/startup_musca_b1_secure_enclave_s.s index 27f1b1778..6739a30e9 100644 --- a/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/armclang/startup_musca_b1_secure_enclave_s.s +++ b/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/armclang/startup_musca_b1_secure_enclave_s.s @@ -26,7 +26,6 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -38,7 +37,7 @@ EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; -14 NMI Handler DCD HardFault_Handler ; -13 Hard Fault Handler @@ -103,14 +102,6 @@ Reset_Handler PROC LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - MSR PSP, R0 - LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S b/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S index bd4c1d956..a62adbf7a 100644 --- a/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S +++ b/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 Arm Limited. All rights reserved. +; * Copyright (c) 2009-2021 Arm Limited. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* -14 NMI Handler */ .long HardFault_Handler /* -13 Hard Fault Handler */ @@ -216,13 +216,6 @@ Reset_Handler: bl SystemInit - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/musca_b1/sse_200/Device/Source/armclang/startup_cmsdk_musca_s.s b/platform/ext/target/arm/musca_b1/sse_200/Device/Source/armclang/startup_cmsdk_musca_s.s index fe00a7f57..c904dfc05 100644 --- a/platform/ext/target/arm/musca_b1/sse_200/Device/Source/armclang/startup_cmsdk_musca_s.s +++ b/platform/ext/target/arm/musca_b1/sse_200/Device/Source/armclang/startup_cmsdk_musca_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2019 Arm Limited +; * Copyright (c) 2009-2021 Arm Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -36,7 +36,7 @@ EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -145,9 +145,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S index 639ce0b74..226f7ed2c 100644 --- a/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S +++ b/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 Arm Limited +; * Copyright (c) 2009-2021 Arm Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -253,12 +253,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c b/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c index d4d2f5488..c2c0de4e9 100644 --- a/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c +++ b/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -71,8 +71,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -149,9 +149,9 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) /* NSPM PSP */ region_cfg.region_nr = MPU_REGION_NS_STACK; region_cfg.region_base = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); region_cfg.region_limit = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; diff --git a/platform/ext/target/arm/musca_s1/Device/Source/armclang/startup_cmsdk_musca_s.s b/platform/ext/target/arm/musca_s1/Device/Source/armclang/startup_cmsdk_musca_s.s index 6293c8d39..d3bb33734 100644 --- a/platform/ext/target/arm/musca_s1/Device/Source/armclang/startup_cmsdk_musca_s.s +++ b/platform/ext/target/arm/musca_s1/Device/Source/armclang/startup_cmsdk_musca_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2017-2019 Arm Limited. All rights reserved. +; * Copyright (c) 2017-2021 Arm Limited. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -36,7 +36,7 @@ EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -145,9 +145,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S index bd4922d28..6cd30d92f 100644 --- a/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S +++ b/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 Arm Limited. All rights reserved. +; * Copyright (c) 2009-2021 Arm Limited. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -253,12 +253,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c b/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c index 5dd8cfc76..8c8d51cf3 100644 --- a/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c +++ b/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -30,8 +30,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -89,9 +89,9 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) /* NSPM PSP */ region_cfg.region_nr = MPU_REGION_NS_STACK; region_cfg.region_base = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); region_cfg.region_limit = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; diff --git a/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s b/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s index 4f35894e5..5e0c6e6a8 100644 --- a/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s +++ b/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2017-2018 ARM Limited +; * Copyright (c) 2017-2021 ARM Limited ; * Copyright (c) 2019-2021, Cypress Semiconductor Corporation. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); @@ -35,7 +35,7 @@ CY_CPU_VTOR_ADDR EQU 0xE000ED08 PRESERVE8 - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -52,7 +52,7 @@ CY_CPU_VTOR_ADDR EQU 0xE000ED08 IMPORT Cy_SysIpcPipeIsrCm0 __Vectors ;Core Interrupts - DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD CY_NMI_HANLDER_ADDR ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler diff --git a/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S b/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S index d66552478..79b5b0503 100644 --- a/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S +++ b/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * Copyright (c) 2009-2021 ARM Limited. All rights reserved. * Copyright (c) 2019-2020, Cypress Semiconductor Corporation. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -35,7 +35,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long CY_NMI_HANLDER_ADDR /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -272,13 +272,6 @@ Reset_Handler: bl SystemInit #endif - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - bl main /* Should never get here */ diff --git a/platform/ext/target/cypress/psoc64/Device/Source/iar/startup_psoc64_s.s b/platform/ext/target/cypress/psoc64/Device/Source/iar/startup_psoc64_s.s index 2f39f0fd7..b2ec922f6 100644 --- a/platform/ext/target/cypress/psoc64/Device/Source/iar/startup_psoc64_s.s +++ b/platform/ext/target/cypress/psoc64/Device/Source/iar/startup_psoc64_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2017-2018 ARM Limited +; * Copyright (c) 2017-2021 ARM Limited ; * Copyright (c) 2019-2020, Cypress Semiconductor Corporation. All rights reserved. ; * Copyright (c) 2020-2021 IAR Systems AB ; * @@ -37,7 +37,6 @@ CY_CPU_VTOR_ADDR EQU 0xE000ED08 ; Vector Table Mapped to Address 0 at Reset - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -59,7 +58,7 @@ CY_CPU_VTOR_ADDR EQU 0xE000ED08 DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD CY_NMI_HANLDER_ADDR ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -133,12 +132,6 @@ Vectors_Copy LDR R0, =SystemInit BLX R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MSR PSP, R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 LDR R0, =__iar_program_start BX R0 End_Of_Main diff --git a/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld b/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld index c5d6fe89d..5b748626f 100644 --- a/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld +++ b/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld @@ -354,8 +354,8 @@ VENEERS() { . += __msp_init_stack_size__; } > RAM - Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack); - Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); /* PSP is unprivileged in single-core topology */ .psp_stack : ALIGN(32) @@ -366,16 +366,16 @@ VENEERS() . += (__psp_stack_size__); # endif } > RAM - Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); - Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Base = ADDR(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); # if !defined(TFM_PSA_API) .psp_stack_seal_res : { . += 0x8; } > RAM - Image$$ARM_LIB_STACK_SEAL$$ZI$$Base = ADDR(.psp_stack_seal_res); - Image$$ARM_LIB_STACK_SEAL$$ZI$$Limit = ADDR(.psp_stack_seal_res) + SIZEOF(.psp_stack_seal_res); + Image$$ER_INITIAL_PSP_SEAL$$ZI$$Base = ADDR(.psp_stack_seal_res); + Image$$ER_INITIAL_PSP_SEAL$$ZI$$Limit = ADDR(.psp_stack_seal_res) + SIZEOF(.psp_stack_seal_res); # endif #endif @@ -506,16 +506,16 @@ VENEERS() { . += __msp_init_stack_size__; } > RAM - Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack); - Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); /* PSP is privileged in multi-core topology */ .psp_stack : ALIGN(32) { . += __psp_stack_size__; } > RAM - Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); - Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Base = ADDR(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); #endif /**** PSA RoT DATA start here */ @@ -642,5 +642,5 @@ VENEERS() Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); + PROVIDE(__stack = Image$$ER_INITIAL_PSP$$ZI$$Limit); } diff --git a/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c b/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c index df0b05b7e..a839c03fc 100644 --- a/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c +++ b/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -29,8 +29,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -89,9 +89,9 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) /* NSPM PSP */ region_cfg.region_nr = MPU_REGION_NS_STACK; region_cfg.region_base = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); region_cfg.region_limit = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/gcc/startup_nrf5340_s.S b/platform/ext/target/nordic_nrf/common/nrf5340/gcc/startup_nrf5340_s.S index 346699cd4..9edc60391 100644 --- a/platform/ext/target/nordic_nrf/common/nrf5340/gcc/startup_nrf5340_s.S +++ b/platform/ext/target/nordic_nrf/common/nrf5340/gcc/startup_nrf5340_s.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * Copyright (c) 2009-2021 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ @@ -254,12 +254,6 @@ Reset_Handler: bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - /* Call _start function provided by libraries. * If those libraries are not accessible, define __START as your entry point. */ diff --git a/platform/ext/target/nordic_nrf/common/nrf9160/gcc/startup_nrf9160_s.S b/platform/ext/target/nordic_nrf/common/nrf9160/gcc/startup_nrf9160_s.S index 00a597c9f..6e27dc5e0 100644 --- a/platform/ext/target/nordic_nrf/common/nrf9160/gcc/startup_nrf9160_s.S +++ b/platform/ext/target/nordic_nrf/common/nrf9160/gcc/startup_nrf9160_s.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * Copyright (c) 2009-2021 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ @@ -250,12 +250,6 @@ Reset_Handler: bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - /* Call _start function provided by libraries. * If those libraries are not accessible, define __START as your entry point. */ diff --git a/platform/ext/target/nuvoton/common/tfm_hal_isolation.c b/platform/ext/target/nuvoton/common/tfm_hal_isolation.c index a7c576294..f5485daf4 100644 --- a/platform/ext/target/nuvoton/common/tfm_hal_isolation.c +++ b/platform/ext/target/nuvoton/common/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,8 +33,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -64,8 +64,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct b/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct index fa3b57f93..822d191e5 100644 --- a/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct +++ b/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct @@ -208,19 +208,19 @@ LR_CODE S_CODE_START { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } # if !defined(TFM_PSA_API) /* PSP is unprivileged in single-core topology. Reserve 8 bytes for seal */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE - 0x8 { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE - 0x8 { } - ARM_LIB_STACK_SEAL +0 EMPTY 0x8 { + ER_INITIAL_PSP_SEAL +0 EMPTY 0x8 { } # else /* PSP is unprivileged in single-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } # endif /* !defined(TFM_PSA_API) */ #endif @@ -347,11 +347,11 @@ LR_CODE S_CODE_START { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } /* PSP is privileged in multi-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } #endif diff --git a/platform/ext/target/nuvoton/m2351/device/source/armclang/startup_cmsdk_m2351_s.s b/platform/ext/target/nuvoton/m2351/device/source/armclang/startup_cmsdk_m2351_s.s index 97d1e7118..9374d1ff6 100644 --- a/platform/ext/target/nuvoton/m2351/device/source/armclang/startup_cmsdk_m2351_s.s +++ b/platform/ext/target/nuvoton/m2351/device/source/armclang/startup_cmsdk_m2351_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2018 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. ; * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,7 +26,6 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -39,7 +38,7 @@ PRESERVE8 -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -176,14 +175,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S b/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S index 58f29dd99..848d3af58 100644 --- a/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S +++ b/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S @@ -27,7 +27,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -289,13 +289,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/nuvoton/m2351/device/source/iar/startup_cmsdk_m2351_s.s b/platform/ext/target/nuvoton/m2351/device/source/iar/startup_cmsdk_m2351_s.s index 57761d420..01327f8d1 100644 --- a/platform/ext/target/nuvoton/m2351/device/source/iar/startup_cmsdk_m2351_s.s +++ b/platform/ext/target/nuvoton/m2351/device/source/iar/startup_cmsdk_m2351_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2020 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -45,7 +44,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -178,14 +177,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__iar_program_start BX R0 diff --git a/platform/ext/target/nuvoton/m2354/device/source/armclang/m2354_s.sct b/platform/ext/target/nuvoton/m2354/device/source/armclang/m2354_s.sct index 86dd8cf26..2007801b9 100644 --- a/platform/ext/target/nuvoton/m2354/device/source/armclang/m2354_s.sct +++ b/platform/ext/target/nuvoton/m2354/device/source/armclang/m2354_s.sct @@ -208,19 +208,19 @@ LR_CODE S_CODE_START { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } # if !defined(TFM_PSA_API) /* PSP is unprivileged in single-core topology. Reserve 8 bytes for seal */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE - 0x8 { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE - 0x8 { } - ARM_LIB_STACK_SEAL +0 EMPTY 0x8 { + ER_INITIAL_PSP_SEAL +0 EMPTY 0x8 { } # else /* PSP is unprivileged in single-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } # endif /* !defined(TFM_PSA_API) */ #endif @@ -341,11 +341,11 @@ LR_CODE S_CODE_START { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } /* PSP is privileged in multi-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } #endif diff --git a/platform/ext/target/nuvoton/m2354/device/source/armclang/startup_cmsdk_m2354_s.s b/platform/ext/target/nuvoton/m2354/device/source/armclang/startup_cmsdk_m2354_s.s index 394fef665..c78dd4eb3 100644 --- a/platform/ext/target/nuvoton/m2354/device/source/armclang/startup_cmsdk_m2354_s.s +++ b/platform/ext/target/nuvoton/m2354/device/source/armclang/startup_cmsdk_m2354_s.s @@ -26,7 +26,6 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -39,7 +38,7 @@ PRESERVE8 -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -176,14 +175,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S b/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S index 196950238..92429464e 100644 --- a/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S +++ b/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2018 ARM Limited +; * Copyright (c) 2009-2021 ARM Limited ; * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. ; * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,7 +27,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -289,13 +289,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/nuvoton/m2354/device/source/iar/startup_cmsdk_m2354_s.s b/platform/ext/target/nuvoton/m2354/device/source/iar/startup_cmsdk_m2354_s.s index 57761d420..01327f8d1 100644 --- a/platform/ext/target/nuvoton/m2354/device/source/iar/startup_cmsdk_m2354_s.s +++ b/platform/ext/target/nuvoton/m2354/device/source/iar/startup_cmsdk_m2354_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2020 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -45,7 +44,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -178,14 +177,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__iar_program_start BX R0 diff --git a/platform/ext/target/nxp/common/tfm_hal_isolation.c b/platform/ext/target/nxp/common/tfm_hal_isolation.c index 425c8d56c..5fc5b1ddc 100644 --- a/platform/ext/target/nxp/common/tfm_hal_isolation.c +++ b/platform/ext/target/nxp/common/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -74,8 +74,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -161,9 +161,9 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) /* NSPM PSP */ region_cfg.region_nr = MPU_REGION_NS_STACK; region_cfg.region_base = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); region_cfg.region_limit = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S index 01aa5961a..23e3dfaa3 100755 --- a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S +++ b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 Arm Limited +; * Copyright (c) 2009-2021 Arm Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler*/ .long HardFault_Handler /* Hard Fault Handler*/ @@ -233,12 +233,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/iar/startup_LPC55S69_cm33_core0_s.s b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/iar/startup_LPC55S69_cm33_core0_s.s index a1b77c6cb..07d8e6985 100755 --- a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/iar/startup_LPC55S69_cm33_core0_s.s +++ b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/iar/startup_LPC55S69_cm33_core0_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2017-2020 ARM Limited +; * Copyright (c) 2017-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -29,7 +29,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -44,7 +43,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -135,11 +134,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MSR PSP, R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__iar_program_start BX R0 End_Of_Main diff --git a/platform/ext/target/nxp/lpcxpresso55s69/README.rst b/platform/ext/target/nxp/lpcxpresso55s69/README.rst index 0cdc3347e..d76641176 100644 --- a/platform/ext/target/nxp/lpcxpresso55s69/README.rst +++ b/platform/ext/target/nxp/lpcxpresso55s69/README.rst @@ -323,7 +323,7 @@ device (``monitor reset``), and continue (``c``) execution. Breakpoint 1, main () at [path]/secure_fw/core/tfm_core.c:189 - 189 tfm_arch_init_secure_msp((uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK_MSP, + 189 tfm_arch_init_secure_msp((uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, 3.2.4 Commonly used GDB commands -------------------------------- @@ -356,5 +356,5 @@ common problems. *Copyright (c) 2021, NXP Semiconductors. All rights reserved.* *Copyright (c) 2020, Linaro. All rights reserved.* -*Copyright (c) 2020, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2021, Arm Limited. All rights reserved.* *SPDX-License-Identifier: BSD-3-Clause*
\ No newline at end of file diff --git a/platform/ext/target/stm/common/stm32l5xx/Device/Source/startup_stm32l5xx_s.c b/platform/ext/target/stm/common/stm32l5xx/Device/Source/startup_stm32l5xx_s.c index 9bdea560c..59c51904c 100644 --- a/platform/ext/target/stm/common/stm32l5xx/Device/Source/startup_stm32l5xx_s.c +++ b/platform/ext/target/stm/common/stm32l5xx/Device/Source/startup_stm32l5xx_s.c @@ -32,13 +32,11 @@ typedef void( *pFunc )( void ); /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ -#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit) -#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base) +#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit) +#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base) extern uint32_t __MSP_INITIAL_SP; extern uint32_t __MSP_STACK_LIMIT; -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; extern void __PROGRAM_START(void) __NO_RETURN; @@ -348,17 +346,8 @@ void Reset_Handler(void) { __disable_irq(); __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT)); -#if defined ( __GNUC__ ) - __set_MSP((uint32_t)(&__MSP_INITIAL_SP)); -#endif + SystemInit(); /* CMSIS System Initialization */ - __set_PSP((uint32_t)(&__INITIAL_SP)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - __ASM volatile("MRS R0, control\n" /* Get control value */ - "ORR R0, R0, #2\n" /* Select switch to PSP */ - "MSR control, R0\n" /* Load control register */ - : - : - : "r0"); + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } diff --git a/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c b/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c index c011cf3b4..1118750ed 100644 --- a/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c +++ b/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -75,8 +75,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -106,8 +106,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/secure_fw/partitions/ns_agent/load_info_ns_agent.c b/secure_fw/partitions/ns_agent/load_info_ns_agent.c index 6e3ec2ae8..960cca2dc 100644 --- a/secure_fw/partitions/ns_agent/load_info_ns_agent.c +++ b/secure_fw/partitions/ns_agent/load_info_ns_agent.c @@ -23,8 +23,8 @@ #endif /* Memory region declaration */ -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); /* Entrypoint function declaration */ extern void tfm_nspm_thread_entry(void); @@ -65,15 +65,15 @@ const struct partition_tfm_sp_ns_agent_load_info_t .nassets = TFM_SP_NS_AGENT_NASSETS, #endif }, - .stack_addr = PART_REGION_ADDR(ARM_LIB_STACK, + .stack_addr = PART_REGION_ADDR(ER_INITIAL_PSP, $$ZI$$Base), .heap_addr = 0, #if TFM_LVL == 3 .assets = { { - .mem.start = PART_REGION_ADDR(ARM_LIB_STACK, + .mem.start = PART_REGION_ADDR(ER_INITIAL_PSP, $$ZI$$Base), - .mem.limit = PART_REGION_ADDR(ARM_LIB_STACK, + .mem.limit = PART_REGION_ADDR(ER_INITIAL_PSP, $$ZI$$Limit), .attr = ASSET_ATTR_READ_WRITE, }, diff --git a/secure_fw/spm/cmsis_func/include/tfm_spm_services.h b/secure_fw/spm/cmsis_func/include/tfm_spm_services.h index a55657332..ff846c007 100644 --- a/secure_fw/spm/cmsis_func/include/tfm_spm_services.h +++ b/secure_fw/spm/cmsis_func/include/tfm_spm_services.h @@ -10,8 +10,6 @@ #include <stdint.h> -typedef uint32_t psa_signal_t; - void tfm_enable_irq(psa_signal_t irq_signal); void tfm_disable_irq(psa_signal_t irq_signal); diff --git a/secure_fw/spm/cmsis_func/main.c b/secure_fw/spm/cmsis_func/main.c index c9ef01191..4cbecd85e 100644 --- a/secure_fw/spm/cmsis_func/main.c +++ b/secure_fw/spm/cmsis_func/main.c @@ -33,7 +33,7 @@ __asm(" .global __ARM_use_no_argv\n"); #error Only TFM_LVL 1 is supported for library model! #endif -REGION_DECLARE(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); static fih_int tfm_core_init(void) { @@ -134,14 +134,33 @@ static fih_int tfm_core_init(void) FIH_RET(fih_int_encode(TFM_SUCCESS)); } +__attribute__((naked)) int main(void) { + __ASM volatile( +#if !defined(__ICCARM__) + ".syntax unified \n" +#endif + "ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" + "msr msp, r0 \n" + "ldr r0, =Image$$ER_INITIAL_PSP$$ZI$$Limit \n" + "msr psp, r0 \n" + "mrs r0, control \n" + "movs r1, #2 \n" + "orrs r0, r0, r1 \n" /* Switch to PSP */ + "msr control, r0 \n" + "bl c_main \n" + ); +} + +int c_main(void) +{ enum spm_err_t spm_err = SPM_ERR_GENERIC_ERR; fih_int fih_rc = FIH_FAILURE; /* set Main Stack Pointer limit */ tfm_arch_init_secure_msp((uint32_t)®ION_NAME(Image$$, - ARM_LIB_STACK_MSP, + ARM_LIB_STACK, $$ZI$$Base)); /* Seal the PSP stacks viz ARM_LIB_STACK and TFM_SECURE_STACK */ @@ -167,9 +186,9 @@ int main(void) tfm_spm_partition_set_state(TFM_SP_CORE_ID, SPM_PARTITION_STATE_RUNNING); - REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base)[]; + REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base)[]; uint32_t psp_stack_bottom = - (uint32_t)REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)REGION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); tfm_arch_set_psplim(psp_stack_bottom); @@ -206,4 +225,6 @@ int main(void) #endif jump_to_ns_code(); + + return 0; } diff --git a/secure_fw/spm/cmsis_func/spm_func.c b/secure_fw/spm/cmsis_func/spm_func.c index 882f517d1..5326f944c 100644 --- a/secure_fw/spm/cmsis_func/spm_func.c +++ b/secure_fw/spm/cmsis_func/spm_func.c @@ -56,7 +56,7 @@ REGION_DECLARE_T(Image$$, TFM_SECURE_STACK, $$ZI$$Limit, struct iovec_args_t)[]; static uint32_t *tfm_secure_stack_seal = ((uint32_t *)®ION_NAME(Image$$, TFM_SECURE_STACK, $$ZI$$Limit)[-1]) - 2; -REGION_DECLARE_T(Image$$, ARM_LIB_STACK_SEAL, $$ZI$$Base, uint32_t)[]; +REGION_DECLARE_T(Image$$, ER_INITIAL_PSP_SEAL, $$ZI$$Base, uint32_t)[]; /* * Function to seal the psp stacks for Function model of TF-M. @@ -84,11 +84,11 @@ void tfm_spm_seal_psp_stacks(void) *(tfm_secure_stack_seal + 1) = TFM_STACK_SEAL_VALUE; /* - * Seal the ARM_LIB_STACK by writing the seal value to the reserved + * Seal the ER_INITIAL_PSP by writing the seal value to the reserved * region. */ uint32_t *arm_lib_stck_seal_base = - ((uint32_t *)®ION_NAME(Image$$, ARM_LIB_STACK_SEAL, $$ZI$$Base)[-1]) - 2; + ((uint32_t *)®ION_NAME(Image$$, ER_INITIAL_PSP_SEAL, $$ZI$$Base)[-1]) - 2; *(arm_lib_stck_seal_base) = TFM_STACK_SEAL_VALUE; *(arm_lib_stck_seal_base + 1) = TFM_STACK_SEAL_VALUE; @@ -652,9 +652,9 @@ static enum tfm_status_e tfm_return_from_partition(uint32_t *excReturn) (struct tfm_state_context_t *)ret_part_data->stack_ptr); *excReturn = ret_part_data->lr; __set_PSP(ret_part_data->stack_ptr); - REGION_DECLARE_T(Image$$, ARM_LIB_STACK, $$ZI$$Base, uint32_t)[]; + REGION_DECLARE_T(Image$$, ER_INITIAL_PSP, $$ZI$$Base, uint32_t)[]; uint32_t psp_stack_bottom = - (uint32_t)REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)REGION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); tfm_arch_set_psplim(psp_stack_bottom); iovec_args = ®ION_NAME(Image$$, TFM_SECURE_STACK, $$ZI$$Limit)[-1]; diff --git a/secure_fw/spm/cmsis_psa/arch/tfm_arch.c b/secure_fw/spm/cmsis_psa/arch/tfm_arch.c index 3d9f07601..1d3e371d9 100644 --- a/secure_fw/spm/cmsis_psa/arch/tfm_arch.c +++ b/secure_fw/spm/cmsis_psa/arch/tfm_arch.c @@ -8,7 +8,23 @@ #include "svc_num.h" #include "tfm_arch.h" #include "tfm_core_utils.h" +#include "utilities.h" +__attribute__((naked)) void tfm_arch_free_msp_and_exc_ret(uint32_t exc_return) +{ + __ASM volatile( +#if !defined(__ICCARM__) + ".syntax unified \n" +#endif + "MOV lr, r0 \n" + "LDR r0, ="M2S(VTOR_BASE)" \n" /* VTOR */ + "LDR r0, [r0] \n" /* MSP address */ + "LDR r0, [r0] \n" /* MSP */ + "SUBS r0, #8 \n" /* Exclude stack seal */ + "MSR msp, r0 \n" /* Free Main Stack space */ + "BX lr \n" + ); +} static void tfm_arch_init_state_ctx(struct tfm_state_context_t *p_stat_ctx, void *param, uintptr_t pfn) diff --git a/secure_fw/spm/cmsis_psa/arch/tfm_arch_v6m_v7m.h b/secure_fw/spm/cmsis_psa/arch/tfm_arch_v6m_v7m.h index b29af05fd..fca3fa0c5 100644 --- a/secure_fw/spm/cmsis_psa/arch/tfm_arch_v6m_v7m.h +++ b/secure_fw/spm/cmsis_psa/arch/tfm_arch_v6m_v7m.h @@ -35,6 +35,8 @@ #define EXC_NUM_SVCALL (11) #define EXC_NUM_PENDSV (14) +#define VTOR_BASE (0xE000ED08) + struct tfm_arch_ctx_t { uint32_t r8; uint32_t r9; @@ -110,6 +112,20 @@ __STATIC_INLINE void tfm_arch_set_psplim(uint32_t psplim) } /** + * \brief Set MSP limit value. + * + * \param[in] msplim MSP limit value to be written. + */ +__STATIC_INLINE void tfm_arch_set_msplim(uint32_t msplim) +{ + /* + * Defined as an empty function now. + * The MSP limit value can be used in more strict memory check. + */ + (void)msplim; +} + +/** * \brief Seal the thread stack. * * \param[in] stk Thread stack address. diff --git a/secure_fw/spm/cmsis_psa/main.c b/secure_fw/spm/cmsis_psa/main.c index 7d34578f5..30cae8bf1 100644 --- a/secure_fw/spm/cmsis_psa/main.c +++ b/secure_fw/spm/cmsis_psa/main.c @@ -31,7 +31,7 @@ __asm(" .global __ARM_use_no_argv\n"); #error Invalid TFM_LVL value. Only TFM_LVL 1, 2 and 3 are supported in IPC model! #endif -REGION_DECLARE(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); static fih_int tfm_core_init(void) { @@ -123,13 +123,24 @@ static fih_int tfm_core_init(void) FIH_RET(fih_int_encode(TFM_SUCCESS)); } +__attribute__((naked)) int main(void) { + __ASM volatile( + "ldr r0, =0xFEF5EDA5 \n" /* Seal Main Stack before using */ + "ldr r1, =0xFEF5EDA5 \n" + "push {r0, r1} \n" + "bl c_main \n" + ); +} + +int c_main(void) +{ fih_int fih_rc = FIH_FAILURE; /* set Main Stack Pointer limit */ - tfm_arch_init_secure_msp((uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK_MSP, - $$ZI$$Base)); + tfm_arch_set_msplim((uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, + $$ZI$$Base)); fih_delay_init(); @@ -152,4 +163,6 @@ int main(void) /* Move to handler mode for further SPM initialization. */ tfm_core_handler_mode(); + + return 0; } diff --git a/secure_fw/spm/cmsis_psa/tfm_core_svcalls_ipc.c b/secure_fw/spm/cmsis_psa/tfm_core_svcalls_ipc.c index dd3c48c3b..0987f078d 100644 --- a/secure_fw/spm/cmsis_psa/tfm_core_svcalls_ipc.c +++ b/secure_fw/spm/cmsis_psa/tfm_core_svcalls_ipc.c @@ -22,7 +22,7 @@ #include "psa/client.h" /* MSP bottom (higher address) */ -REGION_DECLARE(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit); +REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); #ifdef PLATFORM_SVC_HANDLERS extern int32_t platform_svc_handlers(uint8_t svc_num, @@ -176,7 +176,7 @@ uint32_t tfm_flih_return_to_isr(uintptr_t ctx, psa_flih_result_t result) struct partition_t *curr_sp, *prev_sp; struct tfm_svc_flih_ctx_t *flih_ctx; uint32_t msp_top = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); /* Skip one tfm_svc_flih_ctx_t + 8 words (R4- R11) + seals (2 words) */ flih_ctx = (struct tfm_svc_flih_ctx_t *) @@ -257,6 +257,8 @@ uint32_t tfm_core_svc_handler(uint32_t *msp, uint32_t exc_return, case TFM_SVC_SPM_INIT: tfm_arch_clear_fp_status(); exc_return = tfm_spm_init(); + /* The following call does not return */ + tfm_arch_free_msp_and_exc_ret(exc_return); break; case TFM_SVC_GET_BOOT_DATA: tfm_core_get_boot_data_handler(svc_args); @@ -268,7 +270,7 @@ uint32_t tfm_core_svc_handler(uint32_t *msp, uint32_t exc_return, exc_return = tfm_flih_return_to_isr(flih_ctx, svc_args[0]); break; default: - if (((uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit) + if (((uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit) - (uint32_t)msp) > TFM_STACK_SEALED_SIZE) { /* The Main Stack has contents, not calling from Partition thread */ tfm_core_panic(); diff --git a/secure_fw/spm/include/tfm_arch.h b/secure_fw/spm/include/tfm_arch.h index 8a96d9fb3..8eb24b874 100644 --- a/secure_fw/spm/include/tfm_arch.h +++ b/secure_fw/spm/include/tfm_arch.h @@ -103,6 +103,13 @@ void tfm_arch_config_extensions(void); */ void tfm_arch_clear_fp_status(void); +/* + * This function is called after SPM has initialized. + * It frees the stack used by SPM initialization and do Exception Return. + * It does not return. + */ +void tfm_arch_free_msp_and_exc_ret(uint32_t exc_return); + void tfm_arch_init_context(struct tfm_arch_ctx_t *p_actx, void *param, uintptr_t pfn, uintptr_t stk_btm, uintptr_t stk_top); diff --git a/secure_fw/spm/include/tfm_arch_v8m.h b/secure_fw/spm/include/tfm_arch_v8m.h index e615c3ce4..a532a51d5 100644 --- a/secure_fw/spm/include/tfm_arch_v8m.h +++ b/secure_fw/spm/include/tfm_arch_v8m.h @@ -45,6 +45,8 @@ #define EXC_NUM_SVCALL (11) #define EXC_NUM_PENDSV (14) +#define VTOR_BASE (0xE000ED08) + #if defined(__ARM_ARCH_8_1M_MAIN__) || defined(__ARM_ARCH_8M_MAIN__) struct tfm_arch_ctx_t { uint32_t r4; @@ -123,6 +125,16 @@ __STATIC_INLINE void tfm_arch_set_psplim(uint32_t psplim) } /** + * \brief Set MSP limit value. + * + * \param[in] msplim MSP limit value to be written. + */ +__STATIC_INLINE void tfm_arch_set_msplim(uint32_t msplim) +{ + __set_MSPLIM(msplim); +} + +/** * \brief Seal the thread stack. * * This function must be called only when the caller is using MSP. diff --git a/secure_fw/spm/include/utilities.h b/secure_fw/spm/include/utilities.h index f52707140..aec3ea078 100644 --- a/secure_fw/spm/include/utilities.h +++ b/secure_fw/spm/include/utilities.h @@ -37,4 +37,8 @@ void tfm_core_panic(void); /* FixMe: Replace ERROR_MSG() in platform code with a suitable API */ #define ERROR_MSG(msg) SPMLOG_ERRMSG(msg "\r\n") +/* Preprocessor to reference C MACRO to string in inline asm */ +#define M2S_HELPER(x) #x +#define M2S(m) M2S_HELPER(m) + #endif /* __TFM_UTILS_H__ */ |