diff options
Diffstat (limited to 'platform/ext/target')
47 files changed, 146 insertions, 357 deletions
diff --git a/platform/ext/target/arm/diphda/Device/Source/gcc/startup_diphda_s.S b/platform/ext/target/arm/diphda/Device/Source/gcc/startup_diphda_s.S index 28b097979..dd7a8defa 100644 --- a/platform/ext/target/arm/diphda/Device/Source/gcc/startup_diphda_s.S +++ b/platform/ext/target/arm/diphda/Device/Source/gcc/startup_diphda_s.S @@ -25,7 +25,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit/* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* -14 NMI Handler */ .long HardFault_Handler /* -13 Hard Fault Handler */ @@ -215,12 +215,6 @@ Reset_Handler: bl SystemInit - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 #ifndef __START #define __START _start diff --git a/platform/ext/target/arm/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s b/platform/ext/target/arm/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s index 2bcbb6702..fcc94d685 100644 --- a/platform/ext/target/arm/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s +++ b/platform/ext/target/arm/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2018 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -25,7 +25,6 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -37,7 +36,7 @@ PRESERVE8 -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -168,14 +167,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S b/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S index aca6a49af..e151ab6fe 100644 --- a/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S +++ b/platform/ext/target/arm/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 ARM Limited +; * Copyright (c) 2009-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit/* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -310,13 +310,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s b/platform/ext/target/arm/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s index d1043e92c..149c8a384 100644 --- a/platform/ext/target/arm/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s +++ b/platform/ext/target/arm/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2020 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -28,7 +28,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -43,7 +42,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -171,14 +170,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__iar_program_start BX R0 diff --git a/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c b/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c index a396e51ab..8778592b6 100644 --- a/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c +++ b/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,8 +33,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -64,8 +64,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/platform/ext/target/arm/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s b/platform/ext/target/arm/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s index 23f2cc88d..5db755f21 100644 --- a/platform/ext/target/arm/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s +++ b/platform/ext/target/arm/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2018 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -25,7 +25,7 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -34,7 +34,7 @@ EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -165,9 +165,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S b/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S index b2063174d..5f2e23af5 100644 --- a/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S +++ b/platform/ext/target/arm/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 ARM Limited +; * Copyright (c) 2009-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -272,12 +272,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s b/platform/ext/target/arm/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s index 713f22ce7..52f8fe95c 100644 --- a/platform/ext/target/arm/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s +++ b/platform/ext/target/arm/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2020 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -28,7 +28,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -43,7 +42,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -171,11 +170,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MSR PSP, R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__iar_program_start BX R0 diff --git a/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c b/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c index dfafd3909..77ece5f6b 100644 --- a/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c +++ b/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c @@ -76,8 +76,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -107,8 +107,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/platform/ext/target/arm/mps2/fvp_sse300/device/source/startup_fvp_sse300_mps2_s.c b/platform/ext/target/arm/mps2/fvp_sse300/device/source/startup_fvp_sse300_mps2_s.c index 8c6046fb2..54be0ac56 100644 --- a/platform/ext/target/arm/mps2/fvp_sse300/device/source/startup_fvp_sse300_mps2_s.c +++ b/platform/ext/target/arm/mps2/fvp_sse300/device/source/startup_fvp_sse300_mps2_s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -33,15 +33,12 @@ typedef void( *pFunc )( void ); External References *----------------------------------------------------------------------------*/ -#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit) -#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base) +#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit) +#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base) extern uint32_t __MSP_INITIAL_SP; extern uint32_t __MSP_STACK_LIMIT; -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; - extern void __PROGRAM_START(void) __NO_RETURN; /*---------------------------------------------------------------------------- @@ -234,11 +231,6 @@ void Reset_Handler(void) __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT)); SystemInit(); /* CMSIS System Initialization */ - __ASM volatile("MRS R0, control\n" /* Get control value */ - "ORR R0, R0, #2\n" /* Select switch to PSP */ - "MSR control, R0\n" /* Load control register */ - : - : - : "r0"); + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } diff --git a/platform/ext/target/arm/mps2/fvp_sse300/tfm_hal_isolation.c b/platform/ext/target/arm/mps2/fvp_sse300/tfm_hal_isolation.c index 4cbce3014..7f18a882c 100644 --- a/platform/ext/target/arm/mps2/fvp_sse300/tfm_hal_isolation.c +++ b/platform/ext/target/arm/mps2/fvp_sse300/tfm_hal_isolation.c @@ -33,8 +33,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -70,8 +70,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/platform/ext/target/arm/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s b/platform/ext/target/arm/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s index ff9a8d322..cfdd1313c 100644 --- a/platform/ext/target/arm/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s +++ b/platform/ext/target/arm/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2019 Arm Limited. All rights reserved. +; * Copyright (c) 2016-2021 Arm Limited. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -25,7 +25,7 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -35,7 +35,7 @@ EXPORT __Vectors_Size __Vectors - DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -200,9 +200,6 @@ Reset_Handler \ CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S b/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S index b8fb9302f..18a4fd4cf 100644 --- a/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S +++ b/platform/ext/target/arm/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -28,7 +28,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -306,12 +306,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s b/platform/ext/target/arm/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s index 855a7af8e..6064861c7 100644 --- a/platform/ext/target/arm/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s +++ b/platform/ext/target/arm/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s @@ -28,7 +28,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -43,7 +42,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -204,11 +203,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MSR PSP, R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__iar_program_start BX R0 diff --git a/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c index 0f27cba96..a4ad8caf6 100644 --- a/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c +++ b/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -30,8 +30,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -88,9 +88,9 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) /* NSPM PSP */ region_cfg.region_nr = MPU_REGION_NS_STACK; region_cfg.region_base = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); region_cfg.region_limit = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; diff --git a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c index afb5df25f..5d914030b 100644 --- a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c +++ b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c @@ -33,15 +33,12 @@ typedef void( *pFunc )( void ); External References *----------------------------------------------------------------------------*/ -#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit) -#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base) +#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit) +#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base) extern uint32_t __MSP_INITIAL_SP; extern uint32_t __MSP_STACK_LIMIT; -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; - extern void __PROGRAM_START(void) __NO_RETURN; /*---------------------------------------------------------------------------- @@ -346,14 +343,8 @@ extern const pFunc __VECTOR_TABLE[496]; void Reset_Handler(void) { __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT)); - __set_MSP((uint32_t)(&__MSP_INITIAL_SP)); SystemInit(); /* CMSIS System Initialization */ - __ASM volatile("MRS R0, control\n" /* Get control value */ - "ORR R0, R0, #2\n" /* Select switch to PSP */ - "MSR control, R0\n" /* Load control register */ - : - : - : "r0"); + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } diff --git a/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c index 419ad0fe0..20c1c0510 100644 --- a/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c +++ b/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c @@ -33,8 +33,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -70,8 +70,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/armclang/startup_musca_b1_secure_enclave_s.s b/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/armclang/startup_musca_b1_secure_enclave_s.s index 27f1b1778..6739a30e9 100644 --- a/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/armclang/startup_musca_b1_secure_enclave_s.s +++ b/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/armclang/startup_musca_b1_secure_enclave_s.s @@ -26,7 +26,6 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -38,7 +37,7 @@ EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; -14 NMI Handler DCD HardFault_Handler ; -13 Hard Fault Handler @@ -103,14 +102,6 @@ Reset_Handler PROC LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - MSR PSP, R0 - LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S b/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S index bd4c1d956..a62adbf7a 100644 --- a/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S +++ b/platform/ext/target/arm/musca_b1/secure_enclave/Device/Source/gcc/startup_musca_b1_secure_enclave_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 Arm Limited. All rights reserved. +; * Copyright (c) 2009-2021 Arm Limited. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* -14 NMI Handler */ .long HardFault_Handler /* -13 Hard Fault Handler */ @@ -216,13 +216,6 @@ Reset_Handler: bl SystemInit - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/musca_b1/sse_200/Device/Source/armclang/startup_cmsdk_musca_s.s b/platform/ext/target/arm/musca_b1/sse_200/Device/Source/armclang/startup_cmsdk_musca_s.s index fe00a7f57..c904dfc05 100644 --- a/platform/ext/target/arm/musca_b1/sse_200/Device/Source/armclang/startup_cmsdk_musca_s.s +++ b/platform/ext/target/arm/musca_b1/sse_200/Device/Source/armclang/startup_cmsdk_musca_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2019 Arm Limited +; * Copyright (c) 2009-2021 Arm Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -36,7 +36,7 @@ EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -145,9 +145,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S index 639ce0b74..226f7ed2c 100644 --- a/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S +++ b/platform/ext/target/arm/musca_b1/sse_200/Device/Source/gcc/startup_cmsdk_musca_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 Arm Limited +; * Copyright (c) 2009-2021 Arm Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -253,12 +253,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c b/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c index d4d2f5488..c2c0de4e9 100644 --- a/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c +++ b/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -71,8 +71,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -149,9 +149,9 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) /* NSPM PSP */ region_cfg.region_nr = MPU_REGION_NS_STACK; region_cfg.region_base = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); region_cfg.region_limit = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; diff --git a/platform/ext/target/arm/musca_s1/Device/Source/armclang/startup_cmsdk_musca_s.s b/platform/ext/target/arm/musca_s1/Device/Source/armclang/startup_cmsdk_musca_s.s index 6293c8d39..d3bb33734 100644 --- a/platform/ext/target/arm/musca_s1/Device/Source/armclang/startup_cmsdk_musca_s.s +++ b/platform/ext/target/arm/musca_s1/Device/Source/armclang/startup_cmsdk_musca_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2017-2019 Arm Limited. All rights reserved. +; * Copyright (c) 2017-2021 Arm Limited. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -36,7 +36,7 @@ EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -145,9 +145,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S index bd4922d28..6cd30d92f 100644 --- a/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S +++ b/platform/ext/target/arm/musca_s1/Device/Source/gcc/startup_cmsdk_musca_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 Arm Limited. All rights reserved. +; * Copyright (c) 2009-2021 Arm Limited. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -253,12 +253,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c b/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c index 5dd8cfc76..8c8d51cf3 100644 --- a/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c +++ b/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -30,8 +30,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -89,9 +89,9 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) /* NSPM PSP */ region_cfg.region_nr = MPU_REGION_NS_STACK; region_cfg.region_base = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); region_cfg.region_limit = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; diff --git a/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s b/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s index 4f35894e5..5e0c6e6a8 100644 --- a/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s +++ b/platform/ext/target/cypress/psoc64/Device/Source/armclang/startup_psoc64_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2017-2018 ARM Limited +; * Copyright (c) 2017-2021 ARM Limited ; * Copyright (c) 2019-2021, Cypress Semiconductor Corporation. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); @@ -35,7 +35,7 @@ CY_CPU_VTOR_ADDR EQU 0xE000ED08 PRESERVE8 - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -52,7 +52,7 @@ CY_CPU_VTOR_ADDR EQU 0xE000ED08 IMPORT Cy_SysIpcPipeIsrCm0 __Vectors ;Core Interrupts - DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD CY_NMI_HANLDER_ADDR ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler diff --git a/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S b/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S index d66552478..79b5b0503 100644 --- a/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S +++ b/platform/ext/target/cypress/psoc64/Device/Source/gcc/startup_psoc64_s.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * Copyright (c) 2009-2021 ARM Limited. All rights reserved. * Copyright (c) 2019-2020, Cypress Semiconductor Corporation. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -35,7 +35,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long CY_NMI_HANLDER_ADDR /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -272,13 +272,6 @@ Reset_Handler: bl SystemInit #endif - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - bl main /* Should never get here */ diff --git a/platform/ext/target/cypress/psoc64/Device/Source/iar/startup_psoc64_s.s b/platform/ext/target/cypress/psoc64/Device/Source/iar/startup_psoc64_s.s index 2f39f0fd7..b2ec922f6 100644 --- a/platform/ext/target/cypress/psoc64/Device/Source/iar/startup_psoc64_s.s +++ b/platform/ext/target/cypress/psoc64/Device/Source/iar/startup_psoc64_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2017-2018 ARM Limited +; * Copyright (c) 2017-2021 ARM Limited ; * Copyright (c) 2019-2020, Cypress Semiconductor Corporation. All rights reserved. ; * Copyright (c) 2020-2021 IAR Systems AB ; * @@ -37,7 +37,6 @@ CY_CPU_VTOR_ADDR EQU 0xE000ED08 ; Vector Table Mapped to Address 0 at Reset - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -59,7 +58,7 @@ CY_CPU_VTOR_ADDR EQU 0xE000ED08 DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD CY_NMI_HANLDER_ADDR ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -133,12 +132,6 @@ Vectors_Copy LDR R0, =SystemInit BLX R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MSR PSP, R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 LDR R0, =__iar_program_start BX R0 End_Of_Main diff --git a/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld b/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld index c5d6fe89d..5b748626f 100644 --- a/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld +++ b/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld @@ -354,8 +354,8 @@ VENEERS() { . += __msp_init_stack_size__; } > RAM - Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack); - Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); /* PSP is unprivileged in single-core topology */ .psp_stack : ALIGN(32) @@ -366,16 +366,16 @@ VENEERS() . += (__psp_stack_size__); # endif } > RAM - Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); - Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Base = ADDR(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); # if !defined(TFM_PSA_API) .psp_stack_seal_res : { . += 0x8; } > RAM - Image$$ARM_LIB_STACK_SEAL$$ZI$$Base = ADDR(.psp_stack_seal_res); - Image$$ARM_LIB_STACK_SEAL$$ZI$$Limit = ADDR(.psp_stack_seal_res) + SIZEOF(.psp_stack_seal_res); + Image$$ER_INITIAL_PSP_SEAL$$ZI$$Base = ADDR(.psp_stack_seal_res); + Image$$ER_INITIAL_PSP_SEAL$$ZI$$Limit = ADDR(.psp_stack_seal_res) + SIZEOF(.psp_stack_seal_res); # endif #endif @@ -506,16 +506,16 @@ VENEERS() { . += __msp_init_stack_size__; } > RAM - Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack); - Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); /* PSP is privileged in multi-core topology */ .psp_stack : ALIGN(32) { . += __psp_stack_size__; } > RAM - Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); - Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Base = ADDR(.psp_stack); + Image$$ER_INITIAL_PSP$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); #endif /**** PSA RoT DATA start here */ @@ -642,5 +642,5 @@ VENEERS() Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); + PROVIDE(__stack = Image$$ER_INITIAL_PSP$$ZI$$Limit); } diff --git a/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c b/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c index df0b05b7e..a839c03fc 100644 --- a/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c +++ b/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -29,8 +29,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -89,9 +89,9 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) /* NSPM PSP */ region_cfg.region_nr = MPU_REGION_NS_STACK; region_cfg.region_base = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); region_cfg.region_limit = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/gcc/startup_nrf5340_s.S b/platform/ext/target/nordic_nrf/common/nrf5340/gcc/startup_nrf5340_s.S index 346699cd4..9edc60391 100644 --- a/platform/ext/target/nordic_nrf/common/nrf5340/gcc/startup_nrf5340_s.S +++ b/platform/ext/target/nordic_nrf/common/nrf5340/gcc/startup_nrf5340_s.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * Copyright (c) 2009-2021 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ @@ -254,12 +254,6 @@ Reset_Handler: bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - /* Call _start function provided by libraries. * If those libraries are not accessible, define __START as your entry point. */ diff --git a/platform/ext/target/nordic_nrf/common/nrf9160/gcc/startup_nrf9160_s.S b/platform/ext/target/nordic_nrf/common/nrf9160/gcc/startup_nrf9160_s.S index 00a597c9f..6e27dc5e0 100644 --- a/platform/ext/target/nordic_nrf/common/nrf9160/gcc/startup_nrf9160_s.S +++ b/platform/ext/target/nordic_nrf/common/nrf9160/gcc/startup_nrf9160_s.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * Copyright (c) 2009-2021 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ @@ -250,12 +250,6 @@ Reset_Handler: bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - /* Call _start function provided by libraries. * If those libraries are not accessible, define __START as your entry point. */ diff --git a/platform/ext/target/nuvoton/common/tfm_hal_isolation.c b/platform/ext/target/nuvoton/common/tfm_hal_isolation.c index a7c576294..f5485daf4 100644 --- a/platform/ext/target/nuvoton/common/tfm_hal_isolation.c +++ b/platform/ext/target/nuvoton/common/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,8 +33,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -64,8 +64,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, diff --git a/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct b/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct index fa3b57f93..822d191e5 100644 --- a/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct +++ b/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct @@ -208,19 +208,19 @@ LR_CODE S_CODE_START { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } # if !defined(TFM_PSA_API) /* PSP is unprivileged in single-core topology. Reserve 8 bytes for seal */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE - 0x8 { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE - 0x8 { } - ARM_LIB_STACK_SEAL +0 EMPTY 0x8 { + ER_INITIAL_PSP_SEAL +0 EMPTY 0x8 { } # else /* PSP is unprivileged in single-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } # endif /* !defined(TFM_PSA_API) */ #endif @@ -347,11 +347,11 @@ LR_CODE S_CODE_START { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } /* PSP is privileged in multi-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } #endif diff --git a/platform/ext/target/nuvoton/m2351/device/source/armclang/startup_cmsdk_m2351_s.s b/platform/ext/target/nuvoton/m2351/device/source/armclang/startup_cmsdk_m2351_s.s index 97d1e7118..9374d1ff6 100644 --- a/platform/ext/target/nuvoton/m2351/device/source/armclang/startup_cmsdk_m2351_s.s +++ b/platform/ext/target/nuvoton/m2351/device/source/armclang/startup_cmsdk_m2351_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2018 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. ; * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,7 +26,6 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -39,7 +38,7 @@ PRESERVE8 -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -176,14 +175,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S b/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S index 58f29dd99..848d3af58 100644 --- a/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S +++ b/platform/ext/target/nuvoton/m2351/device/source/gcc/startup_cmsdk_m2351_s.S @@ -27,7 +27,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -289,13 +289,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/nuvoton/m2351/device/source/iar/startup_cmsdk_m2351_s.s b/platform/ext/target/nuvoton/m2351/device/source/iar/startup_cmsdk_m2351_s.s index 57761d420..01327f8d1 100644 --- a/platform/ext/target/nuvoton/m2351/device/source/iar/startup_cmsdk_m2351_s.s +++ b/platform/ext/target/nuvoton/m2351/device/source/iar/startup_cmsdk_m2351_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2020 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -45,7 +44,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -178,14 +177,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__iar_program_start BX R0 diff --git a/platform/ext/target/nuvoton/m2354/device/source/armclang/m2354_s.sct b/platform/ext/target/nuvoton/m2354/device/source/armclang/m2354_s.sct index 86dd8cf26..2007801b9 100644 --- a/platform/ext/target/nuvoton/m2354/device/source/armclang/m2354_s.sct +++ b/platform/ext/target/nuvoton/m2354/device/source/armclang/m2354_s.sct @@ -208,19 +208,19 @@ LR_CODE S_CODE_START { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } # if !defined(TFM_PSA_API) /* PSP is unprivileged in single-core topology. Reserve 8 bytes for seal */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE - 0x8 { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE - 0x8 { } - ARM_LIB_STACK_SEAL +0 EMPTY 0x8 { + ER_INITIAL_PSP_SEAL +0 EMPTY 0x8 { } # else /* PSP is unprivileged in single-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } # endif /* !defined(TFM_PSA_API) */ #endif @@ -341,11 +341,11 @@ LR_CODE S_CODE_START { } /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { } /* PSP is privileged in multi-core topology */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + ER_INITIAL_PSP +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { } #endif diff --git a/platform/ext/target/nuvoton/m2354/device/source/armclang/startup_cmsdk_m2354_s.s b/platform/ext/target/nuvoton/m2354/device/source/armclang/startup_cmsdk_m2354_s.s index 394fef665..c78dd4eb3 100644 --- a/platform/ext/target/nuvoton/m2354/device/source/armclang/startup_cmsdk_m2354_s.s +++ b/platform/ext/target/nuvoton/m2354/device/source/armclang/startup_cmsdk_m2354_s.s @@ -26,7 +26,6 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -39,7 +38,7 @@ PRESERVE8 -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -176,14 +175,6 @@ Reset_Handler PROC CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__main BX R0 ENDP diff --git a/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S b/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S index 196950238..92429464e 100644 --- a/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S +++ b/platform/ext/target/nuvoton/m2354/device/source/gcc/startup_cmsdk_m2354_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2018 ARM Limited +; * Copyright (c) 2009-2021 ARM Limited ; * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. ; * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,7 +27,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -289,13 +289,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - movs r1, #2 - orrs r0, r0, r1 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/nuvoton/m2354/device/source/iar/startup_cmsdk_m2354_s.s b/platform/ext/target/nuvoton/m2354/device/source/iar/startup_cmsdk_m2354_s.s index 57761d420..01327f8d1 100644 --- a/platform/ext/target/nuvoton/m2354/device/source/iar/startup_cmsdk_m2354_s.s +++ b/platform/ext/target/nuvoton/m2354/device/source/iar/startup_cmsdk_m2354_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2020 ARM Limited +; * Copyright (c) 2016-2021 ARM Limited ; * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -45,7 +44,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -178,14 +177,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - MRS R0, control ; Get control value - MOVS R1, #2 - ORRS R0, R0, R1 ; Select switch to PSP - MSR control, R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MOVS R1, #7 - BICS R0, R1 ; Make sure that the SP address is aligned to 8 - MOV SP, R0 ; Initialise PSP LDR R0, =__iar_program_start BX R0 diff --git a/platform/ext/target/nxp/common/tfm_hal_isolation.c b/platform/ext/target/nxp/common/tfm_hal_isolation.c index 425c8d56c..5fc5b1ddc 100644 --- a/platform/ext/target/nxp/common/tfm_hal_isolation.c +++ b/platform/ext/target/nxp/common/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -74,8 +74,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -161,9 +161,9 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) /* NSPM PSP */ region_cfg.region_nr = MPU_REGION_NS_STACK; region_cfg.region_base = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base); region_cfg.region_limit = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S index 01aa5961a..23e3dfaa3 100755 --- a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S +++ b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/armgcc/startup_LPC55S69_cm33_core0_s.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2009-2020 Arm Limited +; * Copyright (c) 2009-2021 Arm Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ .align 2 .globl __Vectors __Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler*/ .long HardFault_Handler /* Hard Fault Handler*/ @@ -233,12 +233,6 @@ Reset_Handler: cpsid i /* Disable IRQs */ bl SystemInit - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/iar/startup_LPC55S69_cm33_core0_s.s b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/iar/startup_LPC55S69_cm33_core0_s.s index a1b77c6cb..07d8e6985 100755 --- a/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/iar/startup_LPC55S69_cm33_core0_s.s +++ b/platform/ext/target/nxp/lpcxpresso55s69/Device/Source/iar/startup_LPC55S69_cm33_core0_s.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2017-2020 ARM Limited +; * Copyright (c) 2017-2021 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -29,7 +29,6 @@ MODULE ?cstartup ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) SECTION ARM_LIB_STACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) @@ -44,7 +43,7 @@ DATA __vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack + DCD sfe(ARM_LIB_STACK) ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -135,11 +134,6 @@ Reset_Handler CPSID i ; Disable IRQs LDR R0, =SystemInit BLX R0 - LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK - MSR PSP, R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 LDR R0, =__iar_program_start BX R0 End_Of_Main diff --git a/platform/ext/target/nxp/lpcxpresso55s69/README.rst b/platform/ext/target/nxp/lpcxpresso55s69/README.rst index 0cdc3347e..d76641176 100644 --- a/platform/ext/target/nxp/lpcxpresso55s69/README.rst +++ b/platform/ext/target/nxp/lpcxpresso55s69/README.rst @@ -323,7 +323,7 @@ device (``monitor reset``), and continue (``c``) execution. Breakpoint 1, main () at [path]/secure_fw/core/tfm_core.c:189 - 189 tfm_arch_init_secure_msp((uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK_MSP, + 189 tfm_arch_init_secure_msp((uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, 3.2.4 Commonly used GDB commands -------------------------------- @@ -356,5 +356,5 @@ common problems. *Copyright (c) 2021, NXP Semiconductors. All rights reserved.* *Copyright (c) 2020, Linaro. All rights reserved.* -*Copyright (c) 2020, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2021, Arm Limited. All rights reserved.* *SPDX-License-Identifier: BSD-3-Clause*
\ No newline at end of file diff --git a/platform/ext/target/stm/common/stm32l5xx/Device/Source/startup_stm32l5xx_s.c b/platform/ext/target/stm/common/stm32l5xx/Device/Source/startup_stm32l5xx_s.c index 9bdea560c..59c51904c 100644 --- a/platform/ext/target/stm/common/stm32l5xx/Device/Source/startup_stm32l5xx_s.c +++ b/platform/ext/target/stm/common/stm32l5xx/Device/Source/startup_stm32l5xx_s.c @@ -32,13 +32,11 @@ typedef void( *pFunc )( void ); /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ -#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit) -#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base) +#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit) +#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base) extern uint32_t __MSP_INITIAL_SP; extern uint32_t __MSP_STACK_LIMIT; -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; extern void __PROGRAM_START(void) __NO_RETURN; @@ -348,17 +346,8 @@ void Reset_Handler(void) { __disable_irq(); __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT)); -#if defined ( __GNUC__ ) - __set_MSP((uint32_t)(&__MSP_INITIAL_SP)); -#endif + SystemInit(); /* CMSIS System Initialization */ - __set_PSP((uint32_t)(&__INITIAL_SP)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - __ASM volatile("MRS R0, control\n" /* Get control value */ - "ORR R0, R0, #2\n" /* Select switch to PSP */ - "MSR control, R0\n" /* Load control register */ - : - : - : "r0"); + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } diff --git a/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c b/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c index c011cf3b4..1118750ed 100644 --- a/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c +++ b/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -75,8 +75,8 @@ REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Base); +REGION_DECLARE(Image$$, ER_INITIAL_PSP, $$ZI$$Limit); #ifdef TFM_SP_META_PTR_ENABLE REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); @@ -106,8 +106,8 @@ const struct mpu_armv8m_region_cfg_t region_cfg[] = { /* NSPM PSP */ { MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Base), + (uint32_t)®ION_NAME(Image$$, ER_INITIAL_PSP, $$ZI$$Limit), MPU_ARMV8M_MAIR_ATTR_DATA_IDX, MPU_ARMV8M_XN_EXEC_NEVER, MPU_ARMV8M_AP_RW_PRIV_UNPRIV, |