diff options
| author | Daniel Thompson <daniel.thompson@linaro.org> | 2017-07-31 17:23:07 +0100 |
|---|---|---|
| committer | Daniel Thompson <daniel.thompson@linaro.org> | 2017-07-31 17:23:07 +0100 |
| commit | e5b9b8c8b78096e961f4a45b9d1418e4641f24f9 (patch) | |
| tree | a88f532f386376fca6a376e2c362173f971dc144 /arch/arm/cpu/armv7/omap4/hwinit.c | |
| parent | 415d386877df49eb051b85ef74fa59a16dc17c7d (diff) | |
Orangepi i96 support (mega patch)rda/v2012.04.01-r0
This is https://github.com/orangepi-xunlong/OrangePiRDA_u-boot
5ee06c1afb7c ("add new patch a patch") as a single patch against
a guestimated upstream version.
This is merely a reference tree for later comparisons.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
NOT-Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Diffstat (limited to 'arch/arm/cpu/armv7/omap4/hwinit.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/hwinit.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 91f83205ed..187e93887b 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; -u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; +u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; static const struct gpio_bank gpio_bank_44xx[6] = { { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -59,8 +59,8 @@ void do_io_settings(void) u32 lpddr2io; struct control_lpddr2io_regs *lpddr2io_regs = (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; - struct omap4_sys_ctrl_regs *const ctrl = - (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; + struct omap_sys_ctrl_regs *const ctrl = + (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; u32 omap4_rev = omap_revision(); @@ -129,40 +129,40 @@ void init_omap_revision(void) switch (arm_rev) { case MIDR_CORTEX_A9_R0P1: - *omap4_revision = OMAP4430_ES1_0; + *omap_si_rev = OMAP4430_ES1_0; break; case MIDR_CORTEX_A9_R1P2: switch (readl(CONTROL_ID_CODE)) { case OMAP4_CONTROL_ID_CODE_ES2_0: - *omap4_revision = OMAP4430_ES2_0; + *omap_si_rev = OMAP4430_ES2_0; break; case OMAP4_CONTROL_ID_CODE_ES2_1: - *omap4_revision = OMAP4430_ES2_1; + *omap_si_rev = OMAP4430_ES2_1; break; case OMAP4_CONTROL_ID_CODE_ES2_2: - *omap4_revision = OMAP4430_ES2_2; + *omap_si_rev = OMAP4430_ES2_2; break; default: - *omap4_revision = OMAP4430_ES2_0; + *omap_si_rev = OMAP4430_ES2_0; break; } break; case MIDR_CORTEX_A9_R1P3: - *omap4_revision = OMAP4430_ES2_3; + *omap_si_rev = OMAP4430_ES2_3; break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { case OMAP4460_CONTROL_ID_CODE_ES1_1: - *omap4_revision = OMAP4460_ES1_1; + *omap_si_rev = OMAP4460_ES1_1; break; case OMAP4460_CONTROL_ID_CODE_ES1_0: default: - *omap4_revision = OMAP4460_ES1_0; + *omap_si_rev = OMAP4460_ES1_0; break; } break; default: - *omap4_revision = OMAP4430_SILICON_ID_INVALID; + *omap_si_rev = OMAP4430_SILICON_ID_INVALID; break; } } |