diff options
Diffstat (limited to 'gcc/config/alpha')
| -rw-r--r-- | gcc/config/alpha/alpha.c | 58 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.h | 97 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 333 | ||||
| -rw-r--r-- | gcc/config/alpha/vms.h | 36 | ||||
| -rw-r--r-- | gcc/config/alpha/x-alpha | 2 | ||||
| -rw-r--r-- | gcc/config/alpha/xm-alpha.h | 12 |
6 files changed, 231 insertions, 307 deletions
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 4c3c6c67294..7b809314778 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -21,7 +21,7 @@ Boston, MA 02111-1307, USA. */ #include "config.h" -#include <stdio.h> +#include "system.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" @@ -322,7 +322,7 @@ sext_add_operand (op, mode) return ((unsigned HOST_WIDE_INT) INTVAL (op) < 255 || (unsigned HOST_WIDE_INT) (- INTVAL (op)) < 255); - return register_operand (op, mode); + return reg_not_elim_operand (op, mode); } /* Return 1 if OP is the constant 4 or 8. */ @@ -763,8 +763,8 @@ get_aligned_mem (ref, paligned_mem, pbitnum) if (GET_CODE (base) == PLUS) offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0); - *paligned_mem = gen_rtx (MEM, SImode, - plus_constant (base, offset & ~3)); + *paligned_mem = gen_rtx_MEM (SImode, + plus_constant (base, offset & ~3)); MEM_IN_STRUCT_P (*paligned_mem) = MEM_IN_STRUCT_P (ref); MEM_VOLATILE_P (*paligned_mem) = MEM_VOLATILE_P (ref); RTX_UNCHANGING_P (*paligned_mem) = RTX_UNCHANGING_P (ref); @@ -1628,9 +1628,9 @@ alpha_initialize_trampoline (tramp, fnaddr, cxt) /* Store function address and CXT. */ addr = memory_address (Pmode, plus_constant (tramp, 16)); - emit_move_insn (gen_rtx (MEM, Pmode, addr), fnaddr); + emit_move_insn (gen_rtx_MEM (Pmode, addr), fnaddr); addr = memory_address (Pmode, plus_constant (tramp, 24)); - emit_move_insn (gen_rtx (MEM, Pmode, addr), cxt); + emit_move_insn (gen_rtx_MEM (Pmode, addr), cxt); /* Compute hint value. */ temp = force_operand (plus_constant (tramp, 12), NULL_RTX); @@ -1641,18 +1641,18 @@ alpha_initialize_trampoline (tramp, fnaddr, cxt) /* Merge in the hint. */ addr = memory_address (SImode, plus_constant (tramp, 8)); - temp1 = force_reg (SImode, gen_rtx (MEM, SImode, addr)); + temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr)); temp1 = expand_and (temp1, GEN_INT (0xffffc000), NULL_RTX); temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1, OPTAB_WIDEN); - emit_move_insn (gen_rtx (MEM, SImode, addr), temp1); + emit_move_insn (gen_rtx_MEM (SImode, addr), temp1); #ifdef TRANSFER_FROM_TRAMPOLINE - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), + emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), 0, VOIDmode, 1, addr, Pmode); #endif - emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, - gen_rtvec (1, const0_rtx), 0)); + emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, + gen_rtvec (1, const0_rtx), 0)); } /* Do what is necessary for `va_start'. The argument is ignored; @@ -1722,7 +1722,7 @@ alpha_builtin_saveregs (arglist) dest = change_address (block, ptr_mode, XEXP (block, 0)); emit_move_insn (dest, addr); - if (flag_check_memory_usage) + if (current_function_check_memory_usage) emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, dest, ptr_mode, GEN_INT (GET_MODE_SIZE (ptr_mode)), @@ -1736,7 +1736,7 @@ alpha_builtin_saveregs (arglist) POINTER_SIZE/BITS_PER_UNIT)); emit_move_insn (dest, argsize); - if (flag_check_memory_usage) + if (current_function_check_memory_usage) emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, dest, ptr_mode, GEN_INT (GET_MODE_SIZE @@ -1777,8 +1777,8 @@ alpha_return_addr () { alpha_return_addr_rtx = ret = gen_reg_rtx (Pmode); - emit_insn_after (gen_rtx (SET, VOIDmode, ret, - gen_rtx (REG, Pmode, REG_RA)), + emit_insn_after (gen_rtx_SET (VOIDmode, ret, + gen_rtx_REG (Pmode, REG_RA)), get_insns ()); } @@ -1933,6 +1933,34 @@ alpha_sa_size () #endif /* ! OPEN_VMS */ +/* Returns 1 if OP is a register which is not eliminable (i.e., not SP or FP). + + This is used in the patterns used for the integer multiply-add + insn to avoid creating complex expressions that will cause trouble + during reload and need numerous additional patterns to be + recognized. */ + +int +reg_not_elim_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (op == frame_pointer_rtx || op == arg_pointer_rtx) + return 0; + + return register_operand (op, mode); +} + +/* Likewise, but allow 8 bit constants as well. */ + +int +reg_not_elim_or_8bit_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return reg_not_elim_operand (op, mode) || cint8_operand (op, mode); +} + /* Return 1 if this function can directly return via $26. */ int diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index cbfbf0e52a2..a74731abc25 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -917,25 +917,24 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, $f0 for floating-point functions. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ - gen_rtx (REG, \ - ((INTEGRAL_TYPE_P (VALTYPE) \ - && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ - || POINTER_TYPE_P (VALTYPE)) \ - ? word_mode : TYPE_MODE (VALTYPE), \ - ((TARGET_FPREGS \ - && (TREE_CODE (VALTYPE) == REAL_TYPE \ - || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \ - ? 32 : 0)) + gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \ + && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ + || POINTER_TYPE_P (VALTYPE)) \ + ? word_mode : TYPE_MODE (VALTYPE), \ + ((TARGET_FPREGS \ + && (TREE_CODE (VALTYPE) == REAL_TYPE \ + || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \ + ? 32 : 0)) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) \ - gen_rtx (REG, MODE, \ - (TARGET_FPREGS \ - && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ - || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ - ? 32 : 0)) + gen_rtx_REG (MODE, \ + (TARGET_FPREGS \ + && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ + || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ + ? 32 : 0)) /* The definition of this macro implies that there are cases where a scalar value cannot be returned in registers. @@ -1013,11 +1012,12 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \ - ? gen_rtx(REG, (MODE), \ - (CUM) + 16 + ((TARGET_FPREGS \ - && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ - || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ - * 32)) \ + ? gen_rtx_REG ((MODE), \ + (CUM) + 16 \ + + ((TARGET_FPREGS \ + && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ + || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ + * 32)) \ : 0) /* Specify the padding direction of arguments. @@ -1071,15 +1071,15 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, { \ move_block_from_reg \ (16 + CUM, \ - gen_rtx (MEM, BLKmode, \ - plus_constant (virtual_incoming_args_rtx, \ - ((CUM) + 6)* UNITS_PER_WORD)), \ + gen_rtx_MEM (BLKmode, \ + plus_constant (virtual_incoming_args_rtx, \ + ((CUM) + 6)* UNITS_PER_WORD)), \ 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ move_block_from_reg \ (16 + (TARGET_FPREGS ? 32 : 0) + CUM, \ - gen_rtx (MEM, BLKmode, \ - plus_constant (virtual_incoming_args_rtx, \ - (CUM) * UNITS_PER_WORD)), \ + gen_rtx_MEM (BLKmode, \ + plus_constant (virtual_incoming_args_rtx, \ + (CUM) * UNITS_PER_WORD)), \ 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ } \ PRETEND_SIZE = 12 * UNITS_PER_WORD; \ @@ -1495,9 +1495,8 @@ extern void final_prescan_insn (); #define FIXUNS_TRUNC_LIKE_FIX_TRUNC -/* Max number of bytes we can move to or from memory - in one reasonably fast instruction. */ - +/* If a memory-to-memory move would take MOVE_RATIO or more simple + move-instruction pairs, we will do a movstr or libcall instead. */ #define MOVE_MAX 8 /* Largest number of bytes of an object that can be placed in a register. @@ -2108,35 +2107,37 @@ literal_section () \ /* Define the codes that are matched by predicates in alpha.c. */ #define PREDICATE_CODES \ - {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ - {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \ - {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ - {"cint8_operand", {CONST_INT}}, \ - {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ {"add_operand", {SUBREG, REG, CONST_INT}}, \ - {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \ - {"const48_operand", {CONST_INT}}, \ - {"and_operand", {SUBREG, REG, CONST_INT}}, \ - {"or_operand", {SUBREG, REG, CONST_INT}}, \ - {"mode_mask_operand", {CONST_INT}}, \ - {"mul8_operand", {CONST_INT}}, \ - {"mode_width_operand", {CONST_INT}}, \ - {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \ + {"aligned_memory_operand", {MEM}}, \ {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \ {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \ - {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \ + {"and_operand", {SUBREG, REG, CONST_INT}}, \ + {"any_memory_operand", {MEM}}, \ + {"call_operand", {REG, SYMBOL_REF}}, \ + {"cint8_operand", {CONST_INT}}, \ + {"const48_operand", {CONST_INT}}, \ + {"current_file_function_operand", {SYMBOL_REF}}, \ {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \ {"fp0_operand", {CONST_DOUBLE}}, \ - {"current_file_function_operand", {SYMBOL_REF}}, \ - {"call_operand", {REG, SYMBOL_REF}}, \ {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ SYMBOL_REF, CONST, LABEL_REF}}, \ + {"mode_mask_operand", {CONST_INT}}, \ + {"mode_width_operand", {CONST_INT}}, \ + {"mul8_operand", {CONST_INT}}, \ + {"or_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_not_elim_operand", {SUBREG, REG}}, \ + {"reg_not_elim_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \ + {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \ + {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \ + {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \ {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ SYMBOL_REF, CONST, LABEL_REF}}, \ - {"aligned_memory_operand", {MEM}}, \ - {"unaligned_memory_operand", {MEM}}, \ - {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \ - {"any_memory_operand", {MEM}}, + {"unaligned_memory_operand", {MEM}}, /* Tell collect that the object format is ECOFF. */ #define OBJECT_FORMAT_COFF diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 2f996de8c4c..d49309d6e22 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -234,10 +234,10 @@ (match_operand:SI 2 "add_operand" "")))] "" " -{ emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]), - gen_rtx (PLUS, DImode, - gen_lowpart (DImode, operands[1]), - gen_lowpart (DImode, operands[2])))); +{ emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (DImode, operands[0]), + gen_rtx_PLUS (DImode, + gen_lowpart (DImode, operands[1]), + gen_lowpart (DImode, operands[2])))); DONE; } ") @@ -282,9 +282,9 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (sign_extend:DI - (plus:SI (match_operand:SI 1 "register_operand" "") + (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "") (match_operand:SI 2 "const_int_operand" "")))) - (clobber (match_operand:SI 3 "register_operand" ""))] + (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))] "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) % 4 == 0" [(set (match_dup 3) (match_dup 4)) @@ -354,24 +354,24 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r") - (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ") + (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") (match_operand:SI 2 "const48_operand" "I,I")) (match_operand:SI 3 "sext_add_operand" "rI,O")))] "" "@ - s%2addl %r1,%3,%0 - s%2subl %r1,%n3,%0") + s%2addl %1,%3,%0 + s%2subl %1,%n3,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") (sign_extend:DI - (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ") + (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") (match_operand:SI 2 "const48_operand" "I,I")) (match_operand:SI 3 "sext_add_operand" "rI,O"))))] "" "@ - s%2addl %r1,%3,%0 - s%2subl %r1,%n3,%0") + s%2addl %1,%3,%0 + s%2subl %1,%n3,%0") (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -380,8 +380,8 @@ [(match_operand 2 "" "") (match_operand 3 "" "")]) (match_operand:SI 4 "const48_operand" "")) - (match_operand:SI 5 "add_operand" "")))) - (clobber (match_operand:DI 6 "register_operand" ""))] + (match_operand:SI 5 "sext_add_operand" "")))) + (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))] "" [(set (match_dup 6) (match_dup 7)) (set (match_dup 0) @@ -396,105 +396,14 @@ (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") - (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") + (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r") (match_operand:DI 2 "const48_operand" "I,I")) - (match_operand:DI 3 "reg_or_8bit_operand" "rI,O")))] + (match_operand:DI 3 "reg_not_elim_or_8bit_operand" "rI,O")))] "" "@ - s%2addq %r1,%3,%0 + s%2addq %1,%3,%0 s%2subq %1,%n3,%0") -;; These variants of the above insns can occur if the third operand -;; is the frame pointer. This is a kludge, but there doesn't -;; seem to be a way around it. Only recognize them while reloading. - -(define_insn "" - [(set (match_operand:DI 0 "some_operand" "=&r") - (plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r") - (match_operand:DI 2 "some_operand" "r")) - (match_operand:DI 3 "some_operand" "rIOKL")))] - "reload_in_progress" - "#") - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "register_operand" "")) - (match_operand:DI 3 "add_operand" "")))] - "reload_completed" - [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) - (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] - "") - -(define_insn "" - [(set (match_operand:SI 0 "some_operand" "=&r") - (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ") - (match_operand:SI 2 "const48_operand" "I")) - (match_operand:SI 3 "some_operand" "r")) - (match_operand:SI 4 "some_operand" "rIOKL")))] - "reload_in_progress" - "#") - -(define_split - [(set (match_operand:SI 0 "register_operand" "r") - (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "") - (match_operand:SI 2 "const48_operand" "")) - (match_operand:SI 3 "register_operand" "")) - (match_operand:SI 4 "add_operand" "rIOKL")))] - "reload_completed" - [(set (match_dup 0) - (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] - "") - -(define_insn "" - [(set (match_operand:DI 0 "some_operand" "=&r") - (sign_extend:DI - (plus:SI (plus:SI - (mult:SI (match_operand:SI 1 "some_operand" "rJ") - (match_operand:SI 2 "const48_operand" "I")) - (match_operand:SI 3 "some_operand" "r")) - (match_operand:SI 4 "some_operand" "rIOKL"))))] - "reload_in_progress" - "#") - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI - (plus:SI (plus:SI - (mult:SI (match_operand:SI 1 "reg_or_0_operand" "") - (match_operand:SI 2 "const48_operand" "")) - (match_operand:SI 3 "register_operand" "")) - (match_operand:SI 4 "add_operand" ""))))] - "reload_completed" - [(set (match_dup 5) - (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))] - " -{ operands[5] = gen_lowpart (SImode, operands[0]); -}") - -(define_insn "" - [(set (match_operand:DI 0 "some_operand" "=&r") - (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ") - (match_operand:DI 2 "const48_operand" "I")) - (match_operand:DI 3 "some_operand" "r")) - (match_operand:DI 4 "some_operand" "rIOKL")))] - "reload_in_progress" - "#") - -(define_split - [(set (match_operand:DI 0 "register_operand" "=") - (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "") - (match_operand:DI 2 "const48_operand" "")) - (match_operand:DI 3 "register_operand" "")) - (match_operand:DI 4 "add_operand" "")))] - "reload_completed" - [(set (match_dup 0) - (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3))) - (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] - "") - (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] @@ -520,10 +429,10 @@ (match_operand:SI 2 "reg_or_8bit_operand" "")))] "" " -{ emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]), - gen_rtx (MINUS, DImode, - gen_lowpart (DImode, operands[1]), - gen_lowpart (DImode, operands[2])))); +{ emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (DImode, operands[0]), + gen_rtx_MINUS (DImode, + gen_lowpart (DImode, operands[1]), + gen_lowpart (DImode, operands[2])))); DONE; } ") @@ -551,28 +460,28 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r") (match_operand:SI 2 "const48_operand" "I")) (match_operand:SI 3 "reg_or_8bit_operand" "rI")))] "" - "s%2subl %r1,%3,%0") + "s%2subl %1,%3,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI - (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r") (match_operand:SI 2 "const48_operand" "I")) (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] "" - "s%2subl %r1,%3,%0") + "s%2subl %1,%3,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") + (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r") (match_operand:DI 2 "const48_operand" "I")) (match_operand:DI 3 "reg_or_8bit_operand" "rI")))] "" - "s%2subq %r1,%3,%0") + "s%2subq %1,%3,%0") (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1547,7 +1456,7 @@ "TARGET_FP && reload_completed" [(set (match_dup 2) (fix:DI (match_dup 1))) (set (match_dup 0) (unspec:SI [(match_dup 2)] 5))] - "operands[2] = gen_rtx (REG, DImode, REGNO (operands[0]));") + "operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=f") @@ -1618,7 +1527,7 @@ "TARGET_FP && reload_completed" [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1)))) (set (match_dup 0) (unspec:SI [(match_dup 2)] 5))] - "operands[2] = gen_rtx (REG, DImode, REGNO (operands[0]));") + "operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));") (define_insn "fix_truncsfsi2_tp" [(set (match_operand:SI 0 "register_operand" "=&f") @@ -2785,8 +2694,8 @@ { enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode; operands[1] = gen_reg_rtx (mode); - operands[2] = gen_rtx (LT, mode, alpha_compare_op0, alpha_compare_op1); - operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode)); + operands[2] = gen_rtx_LT (mode, alpha_compare_op0, alpha_compare_op1); + operands[3] = gen_rtx_NE (VOIDmode, operands[1], CONST0_RTX (mode)); }") (define_expand "ble" @@ -2800,8 +2709,8 @@ { enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode; operands[1] = gen_reg_rtx (mode); - operands[2] = gen_rtx (LE, mode, alpha_compare_op0, alpha_compare_op1); - operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode)); + operands[2] = gen_rtx_LE (mode, alpha_compare_op0, alpha_compare_op1); + operands[3] = gen_rtx_NE (VOIDmode, operands[1], CONST0_RTX (mode)); }") (define_expand "bgt" @@ -2816,14 +2725,14 @@ if (alpha_compare_fp_p) { operands[1] = gen_reg_rtx (DFmode); - operands[2] = gen_rtx (LT, DFmode, alpha_compare_op1, alpha_compare_op0); - operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode)); + operands[2] = gen_rtx_LT (DFmode, alpha_compare_op1, alpha_compare_op0); + operands[3] = gen_rtx_NE (VOIDmode, operands[1], CONST0_RTX (DFmode)); } else { operands[1] = gen_reg_rtx (DImode); - operands[2] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1); - operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); + operands[2] = gen_rtx_LE (DImode, alpha_compare_op0, alpha_compare_op1); + operands[3] = gen_rtx_EQ (VOIDmode, operands[1], const0_rtx); } }") @@ -2839,14 +2748,14 @@ if (alpha_compare_fp_p) { operands[1] = gen_reg_rtx (DFmode); - operands[2] = gen_rtx (LE, DFmode, alpha_compare_op1, alpha_compare_op0); - operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode)); + operands[2] = gen_rtx_LE (DFmode, alpha_compare_op1, alpha_compare_op0); + operands[3] = gen_rtx_NE (VOIDmode, operands[1], CONST0_RTX (DFmode)); } else { operands[1] = gen_reg_rtx (DImode); - operands[2] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1); - operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); + operands[2] = gen_rtx_LT (DImode, alpha_compare_op0, alpha_compare_op1); + operands[3] = gen_rtx_EQ (VOIDmode, operands[1], const0_rtx); } }") @@ -2860,8 +2769,8 @@ " { operands[1] = gen_reg_rtx (DImode); - operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1); - operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx); + operands[2] = gen_rtx_LTU (DImode, alpha_compare_op0, alpha_compare_op1); + operands[3] = gen_rtx_NE (VOIDmode, operands[1], const0_rtx); }") (define_expand "bleu" @@ -2874,8 +2783,8 @@ " { operands[1] = gen_reg_rtx (DImode); - operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1); - operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx); + operands[2] = gen_rtx_LEU (DImode, alpha_compare_op0, alpha_compare_op1); + operands[3] = gen_rtx_NE (VOIDmode, operands[1], const0_rtx); }") (define_expand "bgtu" @@ -2888,8 +2797,8 @@ " { operands[1] = gen_reg_rtx (DImode); - operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1); - operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); + operands[2] = gen_rtx_LEU (DImode, alpha_compare_op0, alpha_compare_op1); + operands[3] = gen_rtx_EQ (VOIDmode, operands[1], const0_rtx); }") (define_expand "bgeu" @@ -2902,8 +2811,8 @@ " { operands[1] = gen_reg_rtx (DImode); - operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1); - operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); + operands[2] = gen_rtx_LTU (DImode, alpha_compare_op0, alpha_compare_op1); + operands[3] = gen_rtx_EQ (VOIDmode, operands[1], const0_rtx); }") (define_expand "seq" @@ -2915,7 +2824,7 @@ if (alpha_compare_fp_p) FAIL; - operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1); + operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "sne" @@ -2928,7 +2837,7 @@ if (alpha_compare_fp_p) FAIL; - operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1); + operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "slt" @@ -2940,7 +2849,7 @@ if (alpha_compare_fp_p) FAIL; - operands[1] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1); + operands[1] = gen_rtx_LT (DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "sle" @@ -2952,7 +2861,7 @@ if (alpha_compare_fp_p) FAIL; - operands[1] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1); + operands[1] = gen_rtx_LE (DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "sgt" @@ -2964,8 +2873,8 @@ if (alpha_compare_fp_p) FAIL; - operands[1] = gen_rtx (LT, DImode, force_reg (DImode, alpha_compare_op1), - alpha_compare_op0); + operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare_op1), + alpha_compare_op0); }") (define_expand "sge" @@ -2977,8 +2886,8 @@ if (alpha_compare_fp_p) FAIL; - operands[1] = gen_rtx (LE, DImode, force_reg (DImode, alpha_compare_op1), - alpha_compare_op0); + operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare_op1), + alpha_compare_op0); }") (define_expand "sltu" @@ -2990,7 +2899,7 @@ if (alpha_compare_fp_p) FAIL; - operands[1] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1); + operands[1] = gen_rtx_LTU (DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "sleu" @@ -3002,7 +2911,7 @@ if (alpha_compare_fp_p) FAIL; - operands[1] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1); + operands[1] = gen_rtx_LEU (DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "sgtu" @@ -3014,8 +2923,8 @@ if (alpha_compare_fp_p) FAIL; - operands[1] = gen_rtx (LTU, DImode, force_reg (DImode, alpha_compare_op1), - alpha_compare_op0); + operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare_op1), + alpha_compare_op0); }") (define_expand "sgeu" @@ -3027,8 +2936,8 @@ if (alpha_compare_fp_p) FAIL; - operands[1] = gen_rtx (LEU, DImode, force_reg (DImode, alpha_compare_op1), - alpha_compare_op0); + operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare_op1), + alpha_compare_op0); }") ;; These are the main define_expand's used to make conditional moves. @@ -3133,10 +3042,9 @@ && extended_count (operands[3], DImode, unsignedp) >= 1)) { if (GET_CODE (operands[3]) == CONST_INT) - operands[7] = gen_rtx (PLUS, DImode, operands[2], - GEN_INT (- INTVAL (operands[3]))); + operands[7] = plus_constant (operands[2], - INTVAL (operands[3])); else - operands[7] = gen_rtx (MINUS, DImode, operands[2], operands[3]); + operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]); operands[8] = gen_rtx (code, VOIDmode, operands[6], const0_rtx); } @@ -3145,13 +3053,13 @@ || code == LEU || code == LTU) { operands[7] = gen_rtx (code, DImode, operands[2], operands[3]); - operands[8] = gen_rtx (NE, VOIDmode, operands[6], const0_rtx); + operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx); } else { operands[7] = gen_rtx (reverse_condition (code), DImode, operands[2], operands[3]); - operands[8] = gen_rtx (EQ, VOIDmode, operands[6], const0_rtx); + operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx); } }") @@ -3180,12 +3088,11 @@ FAIL; if (GET_CODE (operands[3]) == CONST_INT) - tem = gen_rtx (PLUS, SImode, operands[2], - GEN_INT (- INTVAL (operands[3]))); + tem = plus_constant (operands[2], - INTVAL (operands[3])); else - tem = gen_rtx (MINUS, SImode, operands[2], operands[3]); + tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); - operands[7] = gen_rtx (SIGN_EXTEND, DImode, tem); + operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem); operands[8] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[6], const0_rtx); }") @@ -3211,10 +3118,9 @@ && extended_count (operands[3], DImode, unsignedp) >= 1)) { if (GET_CODE (operands[3]) == CONST_INT) - operands[5] = gen_rtx (PLUS, DImode, operands[2], - GEN_INT (- INTVAL (operands[3]))); + operands[5] = plus_constant (operands[2], - INTVAL (operands[3])); else - operands[5] = gen_rtx (MINUS, DImode, operands[2], operands[3]); + operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]); operands[6] = gen_rtx (code, VOIDmode, operands[4], const0_rtx); } @@ -3223,13 +3129,13 @@ || code == LEU || code == LTU) { operands[5] = gen_rtx (code, DImode, operands[2], operands[3]); - operands[6] = gen_rtx (NE, VOIDmode, operands[4], const0_rtx); + operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx); } else { operands[5] = gen_rtx (reverse_condition (code), DImode, operands[2], operands[3]); - operands[6] = gen_rtx (EQ, VOIDmode, operands[4], const0_rtx); + operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx); } }") @@ -3250,12 +3156,11 @@ { rtx tem; if (GET_CODE (operands[3]) == CONST_INT) - tem = gen_rtx (PLUS, SImode, operands[2], - GEN_INT (- INTVAL (operands[3]))); + tem = plus_constant (operands[2], - INTVAL (operands[3])); else - tem = gen_rtx (MINUS, SImode, operands[2], operands[3]); + tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); - operands[5] = gen_rtx (SIGN_EXTEND, DImode, tem); + operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem); operands[6] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[4], const0_rtx); }") @@ -3320,7 +3225,7 @@ if (GET_CODE (operands[0]) != SYMBOL_REF && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27)) { - rtx tem = gen_rtx (REG, DImode, 27); + rtx tem = gen_rtx_REG (DImode, 27); emit_move_insn (tem, operands[0]); operands[0] = tem; } @@ -3339,7 +3244,7 @@ if (GET_CODE (operands[1]) != SYMBOL_REF && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27)) { - rtx tem = gen_rtx (REG, DImode, 27); + rtx tem = gen_rtx_REG (DImode, 27); emit_move_insn (tem, operands[1]); operands[1] = tem; } @@ -3368,7 +3273,7 @@ indirect call differently. Load RA and set operands[2] to PV in both cases. */ - emit_move_insn (gen_rtx (REG, DImode, 25), operands[1]); + emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); if (GET_CODE (operands[0]) == SYMBOL_REF) { extern char *savealloc (); @@ -3380,17 +3285,17 @@ strcpy (linksym, symbol); strcat (linksym, \"..lk\"); - linkage = gen_rtx (SYMBOL_REF, Pmode, linksym); - - emit_move_insn (gen_rtx (REG, Pmode, 26), gen_rtx (MEM, Pmode, linkage)); + linkage = gen_rtx_SYMBOL_REF (Pmode, linksym); + emit_move_insn (gen_rtx_REG (Pmode, 26), + gen_rtx_MEM (Pmode, linkage)); operands[2] - = validize_mem (gen_rtx (MEM, Pmode, plus_constant (linkage, 8))); + = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8))); } else { - emit_move_insn (gen_rtx (REG, Pmode, 26), - gen_rtx (MEM, Pmode, plus_constant (operands[0], 8))); + emit_move_insn (gen_rtx_REG (Pmode, 26), + gen_rtx_MEM (Pmode, plus_constant (operands[0], 8))); operands[2] = operands[0]; } @@ -3432,7 +3337,7 @@ if (GET_CODE (operands[1]) != SYMBOL_REF && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27)) { - rtx tem = gen_rtx (REG, DImode, 27); + rtx tem = gen_rtx_REG (DImode, 27); emit_move_insn (tem, operands[1]); operands[1] = tem; } @@ -3452,7 +3357,7 @@ if (GET_CODE (operands[1]) != SYMBOL_REF && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27)) { - rtx tem = gen_rtx (REG, DImode, 27); + rtx tem = gen_rtx_REG (DImode, 27); emit_move_insn (tem, operands[1]); operands[1] = tem; } @@ -3477,7 +3382,7 @@ indirect call differently. Load RA and set operands[3] to PV in both cases. */ - emit_move_insn (gen_rtx (REG, DImode, 25), operands[2]); + emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); if (GET_CODE (operands[1]) == SYMBOL_REF) { extern char *savealloc (); @@ -3488,17 +3393,17 @@ alpha_need_linkage (symbol, 0); strcpy (linksym, symbol); strcat (linksym, \"..lk\"); - linkage = gen_rtx (SYMBOL_REF, Pmode, linksym); + linkage = gen_rtx_SYMBOL_REF (Pmode, linksym); - emit_move_insn (gen_rtx (REG, Pmode, 26), gen_rtx (MEM, Pmode, linkage)); + emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage)); operands[3] - = validize_mem (gen_rtx (MEM, Pmode, plus_constant (linkage, 8))); + = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8))); } else { - emit_move_insn (gen_rtx (REG, Pmode, 26), - gen_rtx (MEM, Pmode, plus_constant (operands[1], 8))); + emit_move_insn (gen_rtx_REG (Pmode, 26), + gen_rtx_MEM (Pmode, plus_constant (operands[1], 8))); operands[3] = operands[1]; } @@ -4349,7 +4254,7 @@ { rtx aligned_mem, bitnum; rtx scratch = (reload_in_progress - ? gen_rtx (REG, SImode, REGNO (operands[0])) + ? gen_rtx_REG (SImode, REGNO (operands[0])) : gen_reg_rtx (SImode)); get_aligned_mem (operands[1], &aligned_mem, &bitnum); @@ -4461,7 +4366,7 @@ { rtx aligned_mem, bitnum; rtx scratch = (reload_in_progress - ? gen_rtx (REG, SImode, REGNO (operands[0])) + ? gen_rtx_REG (SImode, REGNO (operands[0])) : gen_reg_rtx (SImode)); get_aligned_mem (operands[1], &aligned_mem, &bitnum); @@ -4542,11 +4447,11 @@ /* It is possible that one of the registers we got for operands[2] might coincide with that of operands[0] (which is why we made it TImode). Pick the other one to use as our scratch. */ - rtx scratch = gen_rtx (REG, DImode, - REGNO (operands[0]) == REGNO (operands[2]) - ? REGNO (operands[2]) + 1 : REGNO (operands[2])); + rtx scratch = gen_rtx_REG (DImode, + REGNO (operands[0]) == REGNO (operands[2]) + ? REGNO (operands[2]) + 1 : REGNO (operands[2])); rtx seq = gen_unaligned_loadqi (operands[0], addr, scratch, - gen_rtx (REG, DImode, REGNO (operands[0]))); + gen_rtx_REG (DImode, REGNO (operands[0]))); alpha_set_memflags (seq, operands[1]); emit_insn (seq); @@ -4564,11 +4469,11 @@ /* It is possible that one of the registers we got for operands[2] might coincide with that of operands[0] (which is why we made it TImode). Pick the other one to use as our scratch. */ - rtx scratch = gen_rtx (REG, DImode, - REGNO (operands[0]) == REGNO (operands[2]) - ? REGNO (operands[2]) + 1 : REGNO (operands[2])); + rtx scratch = gen_rtx_REG (DImode, + REGNO (operands[0]) == REGNO (operands[2]) + ? REGNO (operands[2]) + 1 : REGNO (operands[2])); rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch, - gen_rtx (REG, DImode, REGNO (operands[0]))); + gen_rtx_REG (DImode, REGNO (operands[0]))); alpha_set_memflags (seq, operands[1]); emit_insn (seq); @@ -4590,15 +4495,15 @@ get_aligned_mem (operands[0], &aligned_mem, &bitnum); emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, - gen_rtx (REG, SImode, REGNO (operands[2])), - gen_rtx (REG, SImode, - REGNO (operands[2]) + 1))); + gen_rtx_REG (SImode, REGNO (operands[2])), + gen_rtx_REG (SImode, + REGNO (operands[2]) + 1))); } else { rtx addr = get_unaligned_address (operands[0], 0); - rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2])); - rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1); + rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2])); + rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1); rtx scratch3 = scratch1; rtx seq; @@ -4629,15 +4534,15 @@ get_aligned_mem (operands[0], &aligned_mem, &bitnum); emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, - gen_rtx (REG, SImode, REGNO (operands[2])), - gen_rtx (REG, SImode, - REGNO (operands[2]) + 1))); + gen_rtx_REG (SImode, REGNO (operands[2])), + gen_rtx_REG (SImode, + REGNO (operands[2]) + 1))); } else { rtx addr = get_unaligned_address (operands[0], 0); - rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2])); - rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1); + rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2])); + rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1); rtx scratch3 = scratch1; rtx seq; @@ -4659,8 +4564,8 @@ "" " { - operands[1] = gen_rtx (MEM, DImode, plus_constant (stack_pointer_rtx, - INTVAL (operands[0]))); + operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, + INTVAL (operands[0]))); MEM_VOLATILE_P (operands[1]) = 1; operands[0] = const0_rtx; @@ -4722,16 +4627,16 @@ } emit_label (loop_label); - memref = gen_rtx (MEM, DImode, tmp); + memref = gen_rtx_MEM (DImode, tmp); MEM_VOLATILE_P (memref) = 1; emit_move_insn (memref, const0_rtx); emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192))); emit_insn (gen_cmpdi (tmp, want)); emit_jump_insn (gen_bgtu (loop_label)); if (obey_regdecls) - gen_rtx (USE, VOIDmode, tmp); + emit_insn (gen_rtx_USE (VOIDmode, tmp)); - memref = gen_rtx (MEM, DImode, want); + memref = gen_rtx_MEM (DImode, want); MEM_VOLATILE_P (memref) = 1; emit_move_insn (memref, const0_rtx); diff --git a/gcc/config/alpha/vms.h b/gcc/config/alpha/vms.h index 8e4fd6dc858..97d7ac249b5 100644 --- a/gcc/config/alpha/vms.h +++ b/gcc/config/alpha/vms.h @@ -1,5 +1,5 @@ /* Output variables, constants and external declarations, for GNU compiler. - Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. This file is part of GNU CC. @@ -135,7 +135,7 @@ Boston, MA 02111-1307, USA. */ Thus 6 or more means all following args should go on the stack. */ enum avms_arg_type {I64, FF, FD, FG, FS, FT}; -typedef struct {char num_args; enum avms_arg_type atypes[6];} avms_arg_info; +typedef struct {int num_args; enum avms_arg_type atypes[6];} avms_arg_info; #undef CUMULATIVE_ARGS #define CUMULATIVE_ARGS avms_arg_info @@ -177,12 +177,12 @@ extern struct rtx_def *alpha_arg_info_reg_val (); #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ((MODE) == VOIDmode ? alpha_arg_info_reg_val (CUM) \ : ((CUM.num_args) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \ - ? gen_rtx(REG, (MODE), \ - ((CUM).num_args + 16 \ - + ((TARGET_FPREGS \ - && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ - || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ - * 32))) \ + ? gen_rtx_REG ((MODE), \ + ((CUM).num_args + 16 \ + + ((TARGET_FPREGS \ + && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ + || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ + * 32))) \ : 0)) #undef FUNCTION_ARG_ADVANCE @@ -234,7 +234,7 @@ extern struct rtx_def *alpha_arg_info_reg_val (); { \ if (! (NO_RTL)) \ { \ - emit_move_insn (gen_rtx (REG, DImode, 1), \ + emit_move_insn (gen_rtx_REG (DImode, 1), \ virtual_incoming_args_rtx); \ emit_insn (gen_arg_home ()); \ } \ @@ -357,16 +357,16 @@ literals_section () \ CXT is an RTX for the static chain value for the function. */ #undef INITIALIZE_TRAMPOLINE -#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -{ \ - emit_move_insn (gen_rtx (MEM, Pmode, \ - memory_address (Pmode, \ - plus_constant ((TRAMP), 16))), \ - (FNADDR)); \ - emit_move_insn (gen_rtx (MEM, Pmode, \ - memory_address (Pmode, \ +#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ +{ \ + emit_move_insn (gen_rtx_MEM (Pmode, \ + memory_address (Pmode, \ + plus_constant ((TRAMP), 16))), \ + (FNADDR)); \ + emit_move_insn (gen_rtx_MEM (Pmode, \ + memory_address (Pmode, \ plus_constant ((TRAMP), 24))), \ - (CXT)); \ + (CXT)); \ } #undef TRANSFER_FROM_TRAMPOLINE diff --git a/gcc/config/alpha/x-alpha b/gcc/config/alpha/x-alpha index 99197479798..86aab854ada 100644 --- a/gcc/config/alpha/x-alpha +++ b/gcc/config/alpha/x-alpha @@ -1 +1 @@ -CLIB=-lmld +CLIB=-lmld -lexc diff --git a/gcc/config/alpha/xm-alpha.h b/gcc/config/alpha/xm-alpha.h index f7e870f5641..fb653e17101 100644 --- a/gcc/config/alpha/xm-alpha.h +++ b/gcc/config/alpha/xm-alpha.h @@ -1,5 +1,5 @@ /* Configuration for GNU C-compiler for DEC Alpha. - Copyright (C) 1990, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. + Copyright (C) 1990, 92, 93, 94, 95, 1998 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu). This file is part of GNU CC. @@ -55,16 +55,6 @@ extern void *alloca (); #define ONLY_INT_FIELDS #endif -/* Declare some functions needed for this machine. We don't want to - include these in the sources since other machines might define them - differently. */ - -extern void *malloc (), *realloc (), *calloc (); - -#ifndef inhibit_libc -#include "string.h" -#endif - /* OSF/1 is POSIX.1 compliant. */ #define POSIX |