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AgeCommit message (Expand)Author
2023-04-10Support Intel AMX-COMPLEXHaochen Jiang
2023-04-04riscv: Fix bootstrap [PR109384]Jakub Jelinek
2023-03-29RISC-V: Add Z*inx imcompatible check in gccJiawei
2023-03-15riscv: Add basic XThead* vendor extension supportChristoph Müllner
2023-02-13arc: Don't use millicode thunks unless asked for.Claudiu Zissulescu
2023-02-12RISC-V: Add vmulh C/C++ supportJu-Zhe Zhong
2023-02-09i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]Jakub Jelinek
2023-02-02RISC-V: Fix bug of TARGET_COMPUTE_MULTILIB implemented in riscv.Jin Ma
2023-02-01AArch64: Fix native detection in the presence of mandatory features which don...Tamar Christina
2023-01-30riscv: Enable -fasynchronous-unwind-tables by default on LinuxAndreas Schwab
2023-01-23[PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64Andrea Corallo
2023-01-16Update copyright years.Jakub Jelinek
2023-01-13arm: Add cde feature support for Cortex-M55 CPU.Srinath Parvathaneni
2023-01-05Add AMD znver4 instruction reservationsTejas Joshi
2023-01-04Initial Emeraldrapids SupportHu, Lin1
2023-01-04i386: Remove Meteorlake's family_modelHu, Lin1
2022-12-27Fixed typo in RISCVjinma
2022-12-27rs6000: Rework option -mpowerpc64 handling [PR106680]Kewen Lin
2022-11-24i386: Only enable small loop unrolling in backend [PR 107692]Hongyu Wang
2022-11-14Revert "sphinx: port .def files to RST"Martin Liska
2022-11-14i386: Add AMX-TILE dependency for AMX related ISAsHaochen Jiang
2022-11-14Enable small loop unrolling for O2Hongyu Wang
2022-11-09sphinx: port .def files to RSTMartin Liska
2022-11-07Initial Grand Ridge supportHu, Lin1
2022-11-07Support Intel RAO-INTkonglin1
2022-11-07Initial Granite Rapids SupportHaochen Jiang
2022-11-07Support Intel prefetchit0/t1Haochen Jiang
2022-11-04Support Intel AMX-FP16 ISAHongyu Wang
2022-11-04Initial Sierra Forest SupportHaochen Jiang
2022-11-04Support Intel CMPccXADDHaochen Jiang
2022-11-02RISC-V: Add Zawrs ISA extension supportChristoph Müllner
2022-10-31Support Intel AVX-NE-CONVERTkonglin1
2022-10-27RISC-V: Minimal support of z*inx extension.Jiawei
2022-10-26i386: add reset_cpu_featureMartin Liska
2022-10-26RISC-V: Recognized Svinval and Svnapot extensionsMonk Chiang
2022-10-26RISC-V: Add h extension supportKito Cheng
2022-10-25Remove znver4 instruction reservationsTejas Joshi
2022-10-25riscv: fix cross compilerMartin Liska
2022-10-25i386: fix pedantic warningMartin Liska
2022-10-24x86: fix VENDOR_MAX enum valueMartin Liska
2022-10-24RISC-V: Support --target-help for -mcpu/-mtuneKito Cheng
2022-10-21Enable AMD znver4 support and add instruction reservationsTejas Joshi
2022-10-21Support Intel AVX-VNNI-INT8Kong Lingling
2022-10-21Support Intel AVX-IFMAHongyu Wang
2022-10-17Enable REE for H8Jeff Law
2022-10-17Initial Meteorlake SupportHu, Lin1
2022-10-17Initial Raptorlake SupportHaochen Jiang
2022-10-10arc: Remove obsolete mRcq and mRcw options.Claudiu Zissulescu
2022-09-29aarch64: Tweak handling of -mgeneral-regs-onlyRichard Sandiford
2022-09-29aarch64: Tweak contents of flags_on/off fieldsRichard Sandiford