Add plat-sunxilinaro-20180524-001linaro-bpi0

Initial version support for Allwinner H2+ platform.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>

5 files changed, 374 insertions, 0 deletions

diff --git a/core/arch/arm/plat-sunxi/conf.mk b/core/arch/arm/plat-sunxi/conf.mk
new file mode 100644
index 00000000..602186a7
--- /dev/null
+++ b/core/arch/arm/plat-sunxi/conf.mk
@@ -0,0 +1,43 @@
+PLATFORM_FLAVOR ?= sun8i_h2_plus_bananapi_m2_zero
+
+sun8i_h2_plus_flavorlist = sun8i_h2_plus_bananapi_m2_zero
+
+ifneq (,$(filter $(PLATFORM_FLAVOR),$(sun8i_h2_plus_flavorlist)))
+include core/arch/arm/cpu/cortex-a7.mk
+$(call force,CFG_SUN8I_H2_PLUS,y)
+endif
+
+ta-targets = ta_arm32
+ifeq ($(CFG_ARM64_core),y)
+$(call force,CFG_WITH_LPAE,y)
+ta-targets += ta_arm64
+else
+$(call force,CFG_ARM32_core,y)
+endif
+
+ifeq ($(filter y,$(CFG_SUN8I_H2_PLUS)),y)
+$(call force,CFG_GENERIC_BOOT,y)
+$(call force,CFG_GIC,y)
+$(call force,CFG_SUNXI_UART,y)
+$(call force,CFG_PM_STUBS,y)
+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
+$(call force,CFG_WITH_LPAE,n)
+$(call force,CFG_WITH_PAGER,n)
+endif
+
+ifneq (,$(filter $(PLATFORM_FLAVOR),sun8i_h2_plus_bananapi_m2_zero))
+CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
+CFG_NUM_THREADS ?= 4
+CFG_CRYPTO_WITH_CE ?= n
+CFG_WITH_STACK_CANARIES ?= y
+#CFG_BOOT_SYNC_CPU ?= y
+CFG_BOOT_SECONDARY_REQUEST ?= y
+CFG_TEE_CORE_EMBED_INTERNAL_TESTS ?= y
+CFG_WITH_STACK_CANARIES ?= y
+CFG_WITH_STATS ?= y
+CFG_NS_ENTRY_ADDR ?= 0x42000000
+CFG_DT ?= y
+endif
+
+arm32-platform-cflags += -Wno-error=cast-align
+arm64-platform-cflags += -Wno-error=cast-align
diff --git a/core/arch/arm/plat-sunxi/main.c b/core/arch/arm/plat-sunxi/main.c
new file mode 100644
index 00000000..3d8d5c11
--- /dev/null
+++ b/core/arch/arm/plat-sunxi/main.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2014, Allwinner Technology Co., Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <console.h>
+#include <io.h>
+#include <drivers/gic.h>
+#include <drivers/sunxi_uart.h>
+#include <kernel/generic_boot.h>
+#include <kernel/misc.h>
+#include <kernel/panic.h>
+#include <kernel/pm_stubs.h>
+#include <mm/core_mmu.h>
+#include <mm/core_memprot.h>
+#include <mm/tee_pager.h>
+#include <platform_config.h>
+#include <stdint.h>
+#include <sm/tee_mon.h>
+#include <sm/optee_smc.h>
+#include <tee/entry_fast.h>
+#include <tee/entry_std.h>
+
+#ifdef GIC_BASE
+register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE);
+#endif
+#ifdef CONSOLE_UART_BASE
+register_phys_mem(MEM_AREA_IO_NSEC,
+		  CONSOLE_UART_BASE, SUNXI_UART_REG_SIZE);
+#endif
+#ifdef SUNXI_TZPC_BASE
+register_phys_mem(MEM_AREA_IO_SEC, SUNXI_TZPC_BASE, SUNXI_TZPC_REG_SIZE);
+#endif
+#ifdef SUNXI_CPUCFG_BASE
+register_phys_mem(MEM_AREA_IO_SEC, SUNXI_CPUCFG_BASE, SUNXI_CPUCFG_REG_SIZE);
+#endif
+#ifdef SUNXI_PRCM_BASE
+register_phys_mem(MEM_AREA_IO_SEC, SUNXI_PRCM_BASE, SUNXI_PRCM_REG_SIZE);
+#endif
+
+static struct gic_data gic_data;
+static TEE_Result tzpc_init(void);
+void platform_sunxi_init(void);
+void reset_secondary(void);
+static void main_tee_entry_std(struct thread_smc_args *args);
+static void main_tee_entry_fast(struct thread_smc_args *args);
+
+static void main_fiq(void)
+{
+	panic();
+}
+
+static const struct thread_handlers handlers = {
+	.std_smc = tee_entry_std,
+	.fast_smc = tee_entry_fast,
+	.nintr = main_fiq,
+#if defined(CFG_WITH_ARM_TRUSTED_FW)
+	.cpu_on = cpu_on_handler,
+	.cpu_off = pm_do_nothing,
+	.cpu_suspend = pm_do_nothing,
+	.cpu_resume = pm_do_nothing,
+	.system_off = pm_do_nothing,
+	.system_reset = pm_do_nothing,
+#else
+	.cpu_on = pm_panic,
+	.cpu_off = pm_panic,
+	.cpu_suspend = pm_panic,
+	.cpu_resume = pm_panic,
+	.system_off = pm_panic,
+	.system_reset = pm_panic,
+#endif
+};
+
+static struct sunxi_uart_data console_data;
+
+const struct thread_handlers *generic_boot_get_handlers(void)
+{
+	return &handlers;
+}
+
+void console_init(void)
+{
+#ifdef CFG_SUN8I_H2_PLUS
+	sunxi_uart_init(&console_data, CONSOLE_UART_BASE);
+	register_serial_console(&console_data.chip);
+#endif
+}
+
+static TEE_Result tzpc_init(void)
+{
+	vaddr_t tzpc;
+	
+	tzpc = (vaddr_t)phys_to_virt(SUNXI_TZPC_BASE, MEM_AREA_IO_SEC);
+	DMSG("SMTA_DECPORT0 = %x", read32(tzpc+0x04));
+	DMSG("SMTA_DECPORT1 = %x", read32(tzpc+0x10));
+	DMSG("SMTA_DECPORT2 = %x", read32(tzpc+0x1c));
+	write32(0xbe, tzpc+0x08);
+	write32(0xff, tzpc+0x14);
+	write32(0x7f, tzpc+0x20);
+	DMSG("SMTA_DECPORT0 = %x", read32(tzpc+0x04));
+	DMSG("SMTA_DECPORT1 = %x", read32(tzpc+0x10));
+	DMSG("SMTA_DECPORT2 = %x", read32(tzpc+0x1c));
+	return TEE_SUCCESS;
+}
+
+driver_init(tzpc_init);
+
+void main_init_gic(void)
+{
+	vaddr_t gicc_base;
+	vaddr_t gicd_base;
+
+	gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC);
+	gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC);
+
+	if (!gicc_base || !gicd_base)
+		panic();
+
+	/* Initialize GIC */
+	gic_init(&gic_data, gicc_base, gicd_base);
+	itr_init(&gic_data.chip);
+
+	/* platform smp initialize */
+	/* Be cool with non-secure */
+	write32(0xff, gicc_base + 0x0004);
+}
+
+void main_secondary_init_gic(void)
+{
+	gic_cpu_init(&gic_data);
+}
diff --git a/core/arch/arm/plat-sunxi/plat_init.S b/core/arch/arm/plat-sunxi/plat_init.S
new file mode 100644
index 00000000..1a3a4e6c
--- /dev/null
+++ b/core/arch/arm/plat-sunxi/plat_init.S
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <asm.S>
+#include <arm.h>
+#include <arm32_macros.S>
+#include <kernel/unwind.h>
+
+FUNC plat_cpu_reset_late , :
+UNWIND(	.fnstart)
+
+        /* NSACR configuration */
+	read_nsacr  r0
+	orr     r0, r0, #NSACR_CP10
+	orr     r0, r0, #NSACR_CP11
+	orr     r0, r0, #NSACR_NS_SMP
+	write_nsacr r0
+
+	/* Enable SMP bit */
+        read_actlr  r0
+	orr     r0, r0, #ACTLR_SMP
+	#if defined(CFG_CORE_WORKAROUND_SPECTRE_BP) || \
+	defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC)
+	orr     r0, r0, #ACTLR_CA15_ENABLE_INVALIDATE_BTB
+	#endif
+	write_actlr  r0
+
+	bx	lr
+
+UNWIND(	.fnend)
+END_FUNC plat_cpu_reset_late
+
diff --git a/core/arch/arm/plat-sunxi/platform_config.h b/core/arch/arm/plat-sunxi/platform_config.h
new file mode 100644
index 00000000..151777ac
--- /dev/null
+++ b/core/arch/arm/plat-sunxi/platform_config.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2014, Allwinner Technology Co., Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PLATFORM_CONFIG_H
+#define PLATFORM_CONFIG_H
+
+/* Make stacks aligned to data cache line length */
+#define STACK_ALIGNMENT		32
+
+#ifdef CFG_WITH_PAGER
+#error "Pager not supported for ARM64"
+#endif
+#ifdef CFG_WITH_LPAE
+#error "LPAE not supported for platform sunxi"
+#endif
+
+/* 16550 UART */
+#define CONSOLE_UART_BASE	0x01c28000 /* UART0 */
+#define SUNXI_UART_REG_SIZE	0x400
+#define GIC_BASE		0x01c80000
+#define GICC_OFFSET		0x2000
+#define GICD_OFFSET		0x1000
+#define SMC_BASE		0x01c1e000
+#define SUNXI_TZPC_BASE		0x01c23400
+#define SUNXI_TZPC_REG_SIZE	0x400
+#define SUNXI_CPUCFG_BASE		0x01f01c00
+#define SUNXI_CPUCFG_REG_SIZE	0x400
+#define SUNXI_PRCM_BASE		0x01f01400
+#define SUNXI_PRCM_REG_SIZE	0x400
+#define PRCM_CPU_SOFT_ENTRY_REG   (0x164)
+
+/*
+ * TEE/TZ RAM layout:
+ *
+ *  +-----------------------------------------+  <- CFG_DDR_TEETZ_RESERVED_START
+ *  | TEETZ private RAM  |  TEE_RAM           |   ^
+ *  |                    +--------------------+   |
+ *  |                    |  TA_RAM            |   |
+ *  +-----------------------------------------+   | CFG_DDR_TEETZ_RESERVED_SIZE
+ *  |                    |      teecore alloc |   |
+ *  |  TEE/TZ and NSec   |  PUB_RAM   --------|   |
+ *  |   shared memory    |         NSec alloc |   |
+ *  +-----------------------------------------+   v
+ *
+ *  TEE_RAM : 1MByte
+ *  PUB_RAM : 1MByte
+ *  TA_RAM  : all what is left (at least 2MByte !)
+ */
+
+#define DRAM0_BASE		0x40000000
+#define DRAM0_SIZE		0x20000000
+
+#define DDR_PHYS_START			DRAM0_BASE
+#define DDR_SIZE			DRAM0_SIZE
+
+#define CFG_DDR_START			DDR_PHYS_START
+#define CFG_DDR_SIZE			DDR_SIZE
+
+#define CFG_DDR_TEETZ_RESERVED_SIZE	0x04000000
+#ifndef CFG_DDR_TEETZ_RESERVED_START
+#define CFG_DDR_TEETZ_RESERVED_START	(DRAM0_BASE+DRAM0_SIZE-CFG_DDR_TEETZ_RESERVED_SIZE)
+#endif
+
+#define CFG_PUB_RAM_SIZE	(2 * 1024 * 1024)
+
+#define TZDRAM_BASE		(CFG_DDR_TEETZ_RESERVED_START)
+#define TZDRAM_SIZE		(CFG_DDR_TEETZ_RESERVED_SIZE-CFG_PUB_RAM_SIZE)
+
+/* Below ARM-TF */
+#define TEE_SHMEM_START		(CFG_DDR_TEETZ_RESERVED_START + TZDRAM_SIZE)
+#define TEE_SHMEM_SIZE		CFG_PUB_RAM_SIZE
+
+#define CFG_TEE_CORE_NB_CORE	4
+
+#define TEE_RAM_VA_SIZE	(4 * 1024 * 1024)
+
+#define TEE_RAM_PH_SIZE	TEE_RAM_VA_SIZE
+#define TEE_RAM_START	TZDRAM_BASE
+
+#define TA_RAM_START	ROUNDUP((TEE_RAM_START + TEE_RAM_VA_SIZE),			\
+					CORE_MMU_DEVICE_SIZE)
+
+#define TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \
+					  CORE_MMU_DEVICE_SIZE)
+
+#ifdef CFG_TEE_LOAD_ADDR
+#define TEE_LOAD_ADDR			CFG_TEE_LOAD_ADDR
+#else
+#define TEE_LOAD_ADDR			TEE_RAM_START
+#endif
+
+#endif /* PLATFORM_CONFIG_H */
diff --git a/core/arch/arm/plat-sunxi/sub.mk b/core/arch/arm/plat-sunxi/sub.mk
new file mode 100644
index 00000000..652c084f
--- /dev/null
+++ b/core/arch/arm/plat-sunxi/sub.mk
@@ -0,0 +1,3 @@
+global-incdirs-y += .
+srcs-y += main.c
+srcs-y += plat_init.S