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authorJun Nie <jun.nie@linaro.org>2018-08-07 09:22:23 +0800
committerJun Nie <jun.nie@linaro.org>2018-09-12 12:00:36 +0800
commit2be86e0cad24e719857db526b84129a6b5b941c2 (patch)
treea210f15bce4ed19f128904440bf9f6e65b10e0c1
parent4f468f972c896571a46800cf58fd694862ee2a2b (diff)
downloadtrusted-firmware-tf-linaro-warp7-pr.tar.gz
warp7: add support to warp7 plat with iMX7S SoClinaro-warp7-pr
Add basic support to warp7 with SoC iMX7S. warp7 is an IoT platform with single cortex-A7 processor. Signed-off-by: Jun Nie <jun.nie@linaro.org>
-rw-r--r--drivers/nxp/timer/nxp_timer.c136
-rw-r--r--drivers/nxp/uart/nxp_console.S297
-rw-r--r--drivers/nxp/uart/nxp_console.h155
-rw-r--r--include/drivers/nxp/nxp_timer.h64
-rw-r--r--include/plat/nxp/common/plat_nxp.h53
-rw-r--r--plat/nxp/board/warp7/aarch32/plat_helpers.S41
-rw-r--r--plat/nxp/board/warp7/include/platform_def.h203
-rw-r--r--plat/nxp/board/warp7/plat_setup.c28
-rw-r--r--plat/nxp/board/warp7/platform.mk56
-rw-r--r--plat/nxp/board/warp7/warp7_def.h72
-rw-r--r--plat/nxp/board/warp7/warp7_pwr_state.c74
-rw-r--r--plat/nxp/board/warp7/warp7_tests_to_skip.txt8
-rw-r--r--plat/nxp/board/warp7/warp7_topology.c60
-rw-r--r--plat/nxp/common/nxp_common.mk43
-rw-r--r--plat/nxp/common/nxp_setup.c68
-rw-r--r--plat/nxp/common/plat_timers.c56
16 files changed, 1414 insertions, 0 deletions
diff --git a/drivers/nxp/timer/nxp_timer.c b/drivers/nxp/timer/nxp_timer.c
new file mode 100644
index 0000000..3f200aa
--- /dev/null
+++ b/drivers/nxp/timer/nxp_timer.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <arm_gic.h>
+#include <assert.h>
+#include <gic_v2.h>
+#include <mmio.h>
+#include <nxp_timer.h>
+
+#define GPTCR_SWR (1 << 15) /* Software reset */
+#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
+#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
+#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
+#define GPTCR_ENMODE (1 << 1) /* Timer enable mode */
+#define GPTCR_TEN 1 /* Timer enable */
+
+#define GPTPR_PRESCL_24M_SHIFT 12
+#define SYS_COUNTER_FREQ_IN_MHZ 3
+#define GPT_OSC_FREQ 3000 /* count in 1ms for 24MHz */
+
+#define IRQ_OCMP2 (1 << 1) /* irq for output compare 2 */
+
+#define GPTPR_TIMER_CTRL (gpt_base + 0x00)
+#define GPTPR_TIMER_PRESCL (gpt_base + 0x04)
+#define GPTPR_TIMER_STS (gpt_base + 0x08)
+#define GPTPR_TIMER_IRQ (gpt_base + 0x0c)
+#define GPTPR_TIMER_CMP1 (gpt_base + 0x10)
+#define GPTPR_TIMER_CMP2 (gpt_base + 0x14)
+#define GPTPR_TIMER_CMP3 (gpt_base + 0x18)
+#define GPTPR_TIMER_CAPT1 (gpt_base + 0x1c)
+#define GPTPR_TIMER_CAPT2 (gpt_base + 0x20)
+#define GPTPR_TIMER_CNTR (gpt_base + 0x24)
+
+static uintptr_t gpt_base;
+
+int nxp_timer_program(unsigned long time_out_ms)
+{
+ unsigned int val;
+
+ assert(gpt_base);
+ assert(time_out_ms);
+
+ /* setup GP Timer */
+ mmio_write_32(GPTPR_TIMER_CTRL, GPTCR_SWR);
+ mmio_write_32(GPTPR_TIMER_CTRL, 0);
+ mmio_write_32(GPTPR_TIMER_STS, 0x3f); /* clear all status */
+
+ /* get 3MHz from 24MHz */
+ mmio_write_32(GPTPR_TIMER_PRESCL, (7 << GPTPR_PRESCL_24M_SHIFT));
+
+
+ /* Calculate the load value */
+ val = (GPT_OSC_FREQ * time_out_ms) * 1000;
+ mmio_write_32(GPTPR_TIMER_CMP2, val);
+
+ /*
+ * Configure the timer in one shot mode via compare channel 2.
+ * timer counter width to 32 bits and un-mask the interrupt.
+ */
+ mmio_write_32(GPTPR_TIMER_IRQ, IRQ_OCMP2);
+
+ /* Enable the timer */
+ val = mmio_read_32(GPTPR_TIMER_CTRL);
+ val &= ~GPTCR_CLKSOURCE_MASK;
+ val |= GPTCR_24MEN | GPTCR_CLKSOURCE_OSC | GPTCR_TEN | GPTCR_ENMODE;
+ mmio_write_32(GPTPR_TIMER_CTRL, val);
+
+ return 0;
+}
+
+static void nxp_timer_disable(void)
+{
+ unsigned int val;
+
+ mmio_write_32(GPTPR_TIMER_IRQ, 0);
+ val = mmio_read_32(GPTPR_TIMER_CTRL);
+ val &= ~GPTCR_TEN;
+ mmio_write_32(GPTPR_TIMER_CTRL, val);
+ mmio_write_32(GPTPR_TIMER_STS, 0x3f); /* clear all status */
+}
+
+int nxp_timer_cancel(void)
+{
+ assert(gpt_base);
+ nxp_timer_disable();
+ return 0;
+}
+
+int nxp_timer_handler(void)
+{
+ assert(gpt_base);
+ nxp_timer_disable();
+ return 0;
+}
+
+int nxp_timer_init(uintptr_t base_addr)
+{
+ /* Check input parameters */
+ assert(base_addr);
+
+ /* Check for duplicate initialization */
+ assert(gpt_base == 0);
+
+ gpt_base = base_addr;
+
+ return 0;
+}
diff --git a/drivers/nxp/uart/nxp_console.S b/drivers/nxp/uart/nxp_console.S
new file mode 100644
index 0000000..77149ae
--- /dev/null
+++ b/drivers/nxp/uart/nxp_console.S
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arch.h>
+#include <asm_macros.S>
+#include "nxp_console.h"
+
+ .globl console_init
+ .globl console_putc
+ .globl console_getc
+ .globl console_flush
+ .globl console_core_init
+ .globl console_core_putc
+ .globl console_core_getc
+ .globl console_core_flush
+
+ /*
+ * The console base is in the data section and not in .bss
+ * even though it is zero-init. In particular, this allows
+ * the console functions to start using this variable before
+ * the runtime memory is initialized for images which do not
+ * need to copy the .data section from ROM to RAM.
+ */
+.section .data.console_base ; .align 2
+ console_base: .word 0x0
+
+ /* -----------------------------------------------
+ * int console_init(uintptr_t base_addr,
+ * unsigned int uart_clk, unsigned int baud_rate)
+ * Function to initialize the console without a
+ * C Runtime to print debug information. It saves
+ * the console base to the data section.
+ * In: r0 - console base address
+ * r1 - Uart clock in Hz
+ * r2 - Baud rate
+ * out: return 1 on success else 0 on error
+ * Clobber list : r1 - r3
+ * -----------------------------------------------
+ */
+func console_init
+ ldr r3, =console_base
+ str r0, [r3]
+ b console_core_init
+endfunc console_init
+
+ /* -----------------------------------------------
+ * int console_core_init(uintptr_t base_addr,
+ * unsigned int uart_clk, unsigned int baud_rate)
+ * Function to initialize the console without a
+ * C Runtime to print debug information. This
+ * function will be accessed by console_init and
+ * crash reporting.
+ * In: r0 - console base address
+ * r1 - Uart clock in Hz
+ * r2 - Baud rate
+ * Out: return 1 on success else 0 on error
+ * Clobber list : r1, r2, r3, r4
+ * -----------------------------------------------
+ */
+func console_core_init
+ push {r4}
+ /* Check the input base address */
+ cmp r0, #0
+ beq core_init_fail
+ /* Check baud rate and uart clock for sanity */
+ cmp r1, #0
+ beq core_init_fail
+ cmp r2, #0
+ beq core_init_fail
+
+ /* Free up r1 as a scratch reg */
+ mov r4, r0
+ mov r0, r1
+
+ /* Reset UART via CR2 */
+ add r1, r4, #MXC_UART_CR2_OFFSET
+ movs r3, #0
+ str r3, [r4, #MXC_UART_CR2_OFFSET]
+
+ /* Wait for reset complete */
+__wait_cr2_reset:
+ ldr r3, [r1, #0]
+ ands r3, #MXC_UART_CR2_SRST
+ beq __wait_cr2_reset
+
+ /* Enable UART */
+ movs r3, #MXC_UART_CR1_UARTEN
+ mov r1, r2
+ str r3, [r4, #MXC_UART_CR1_OFFSET]
+
+ /*
+ * Ignore RTC/CTS - disable reset
+ * Magic value #16423 =>
+ * MXC_UART_CR2_IRTS | MXC_UART_CR2_WS | MXC_UART_CR2_TXEN | MXC_UART_CR2_RXEN | MXC_UART_CR2_SRST
+ */
+ movw r3, #16423
+ str r3, [r4, #MXC_UART_CR2_OFFSET]
+
+ /*
+ * No parity, autobaud detect-old, rxdmuxsel=1 (fixed i.mx7)
+ * Magic value => #132
+ * MXC_UART_CR3_ADNIMP | MXC_UART_CR3_RXDMUXSEL
+ */
+ movs r3, #132
+ str r3, [r4, #MXC_UART_CR3_OFFSET]
+
+ /*
+ * Set CTS FIFO trigger to 32 bytes bits 15:10
+ * Magic value => #32768
+ * FIFO trigger bitmask 100000
+ * */
+ mov r3, #32768
+ str r3, [r4, #MXC_UART_CR4_OFFSET]
+
+ /*
+ * TX/RX-thresh = 2 bytes, DCE (bit6 = 0), refclk @24MHz / 4
+ * Magic value #2562
+ * MXC_UART_FCR_TXTL(TX_RX_THRESH) | MXC_UART_FCR_RXTL(TX_RX_THRESH) | MXC_UART_FCR_RFDIV2
+ */
+ movw r3, #2562
+ str r3, [r4, #MXC_UART_FCR_OFFSET]
+
+ /* This BIR should be set to 0x0F prior to writing the BMR */
+ movs r3, #15
+ str r3, [r4, #MXC_UART_BIR_OFFSET]
+
+ /* Hard-code to 115200 @ 24 MHz */
+ movs r0, #104
+ str r0, [r4, #MXC_UART_BMR_OFFSET]
+
+ /* Indicate success */
+ movs r0, #1
+ pop {r4}
+ bx lr
+core_init_fail:
+ pop {r4}
+ mov r0, #0
+ bx lr
+endfunc console_core_init
+
+ /* ---------------------------------------------
+ * int console_putc(int c)
+ * Function to output a character over the
+ * console. It returns the character printed on
+ * success or -1 on error.
+ * In : r0 - character to be printed
+ * Out : return -1 on error else return character.
+ * Clobber list : r1, r2
+ * ---------------------------------------------
+ */
+func console_putc
+ ldr r2, =console_base
+ ldr r1, [r2]
+ b console_core_putc
+endfunc console_putc
+
+ /* --------------------------------------------------------
+ * int console_core_putc(int c, uintptr_t base_addr)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : r0 - character to be printed
+ * r1 - console base address
+ * Out : return -1 on error else return character.
+ * Clobber list : r2
+ * --------------------------------------------------------
+ */
+func console_core_putc
+ /* Check the input parameter */
+ cmp r1, #0
+ beq putc_error
+
+ /* Output specified character to UART shift-register */
+ str r0, [r1, #MXC_UART_TXD_OFFSET]
+
+ /* Wait for transmit MXC_UART_STAT2_OFFSET.MXC_UART_STAT2_TXDC == 1 */
+__putc_spin_ready:
+ ldr r2, [r1, #MXC_UART_STAT2_OFFSET]
+ ands r2, #MXC_UART_STAT2_TXDC
+ beq __putc_spin_ready
+
+ /* Transmit complete do we need to fixup \n to \n\r */
+ cmp r0, #10
+ beq __putc_fixup_lf
+
+ /* No fixup necessary - exit here */
+ movs r0, #0
+ bx lr
+
+ /* Fixup \n to \n\r */
+__putc_fixup_lf:
+ movs r0, #13
+ b console_core_putc
+putc_error:
+ mov r0, #-1
+ bx lr
+endfunc console_core_putc
+
+ /* ---------------------------------------------
+ * int console_getc(void)
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 on error.
+ * Out : return -1 on error else return character.
+ * Clobber list : r0, r1
+ * ---------------------------------------------
+ */
+func console_getc
+ ldr r1, =console_base
+ ldr r0, [r1]
+ b console_core_getc
+endfunc console_getc
+
+ /* ---------------------------------------------
+ * int console_core_getc(void)
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 on error.
+ * In : r0 - console base address
+ * Out : return -1 on error else return character.
+ * Clobber list : r0, r1
+ * ---------------------------------------------
+ */
+func console_core_getc
+ cmp r0, #0
+ beq getc_error
+1:
+ /* Check if the receive FIFO is empty */
+/* TODO */
+getc_error:
+ mov r0, #-1
+ bx lr
+endfunc console_core_getc
+
+ /* ---------------------------------------------
+ * int console_flush(void)
+ * Function to force a write of all buffered
+ * data that hasn't been output. It returns 0
+ * upon successful completion, otherwise it
+ * returns -1.
+ * Clobber list : r0, r1
+ * ---------------------------------------------
+ */
+func console_flush
+ ldr r1, =console_base
+ ldr r0, [r1]
+ b console_core_flush
+endfunc console_flush
+
+ /* ---------------------------------------------
+ * int console_core_flush(uintptr_t base_addr)
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : r0 - console base address
+ * Out : return -1 on error else return 0.
+ * Clobber list : r0, r1
+ * ---------------------------------------------
+ */
+func console_core_flush
+ cmp r0, #0
+ beq flush_error
+
+1:
+ /* Loop while the transmit FIFO is busy */
+/* TODO */
+
+ mov r0, #0
+ bx lr
+flush_error:
+ mov r0, #-1
+ bx lr
+endfunc console_core_flush
diff --git a/drivers/nxp/uart/nxp_console.h b/drivers/nxp/uart/nxp_console.h
new file mode 100644
index 0000000..38f2f05
--- /dev/null
+++ b/drivers/nxp/uart/nxp_console.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __MXC_CONSOLE_H__
+#define __MXC_CONSOLE_H__
+
+#define BIT(x) (1 << (x))
+
+#define MXC_UART_RXD_OFFSET 0x00
+#define MXC_UART_RXD_CHARRDY BIT(15)
+#define MXC_UART_RXD_ERR BIT(14)
+#define MXC_UART_RXD_OVERRUN BIT(13)
+#define MXC_UART_RXD_FRMERR BIT(12)
+#define MXC_UART_RXD_BRK BIT(11)
+#define MXC_UART_RXD_PRERR BIT(10)
+
+#define MXC_UART_TXD_OFFSET 0x40
+
+#define MXC_UART_CR1_OFFSET 0x80
+#define MXC_UART_CR1_ADEN BIT(15)
+#define MXC_UART_CR1_ADBR BIT(14)
+#define MXC_UART_CR1_TRDYEN BIT(13)
+#define MXC_UART_CR1_IDEN BIT(12)
+#define MXC_UART_CR1_RRDYEN BIT(9)
+#define MXC_UART_CR1_RXDMAEN BIT(8)
+#define MXC_UART_CR1_IREN BIT(7)
+#define MXC_UART_CR1_TXMPTYEN BIT(6)
+#define MXC_UART_CR1_RTSDEN BIT(5)
+#define MXC_UART_CR1_SNDBRK BIT(4)
+#define MXC_UART_CR1_TXDMAEN BIT(3)
+#define MXC_UART_CR1_ATDMAEN BIT(2)
+#define MXC_UART_CR1_DOZE BIT(1)
+#define MXC_UART_CR1_UARTEN BIT(0)
+
+#define MXC_UART_CR2_OFFSET 0x84
+#define MXC_UART_CR2_ESCI BIT(15)
+#define MXC_UART_CR2_IRTS BIT(14)
+#define MXC_UART_CR2_CTSC BIT(13)
+#define MXC_UART_CR2_CTS BIT(12)
+#define MXC_UART_CR2_ESCEN BIT(11)
+#define MXC_UART_CR2_PREN BIT(8)
+#define MXC_UART_CR2_PROE BIT(7)
+#define MXC_UART_CR2_STPB BIT(6)
+#define MXC_UART_CR2_WS BIT(5)
+#define MXC_UART_CR2_RTSEN BIT(4)
+#define MXC_UART_CR2_ATEN BIT(3)
+#define MXC_UART_CR2_TXEN BIT(2)
+#define MXC_UART_CR2_RXEN BIT(1)
+#define MXC_UART_CR2_SRST BIT(0)
+
+#define MXC_UART_CR3_OFFSET 0x88
+#define MXC_UART_CR3_DTREN BIT(13)
+#define MXC_UART_CR3_PARERREN BIT(12)
+#define MXC_UART_CR3_FARERREN BIT(11)
+#define MXC_UART_CR3_DSD BIT(10)
+#define MXC_UART_CR3_DCD BIT(9)
+#define MXC_UART_CR3_RI BIT(8)
+#define MXC_UART_CR3_ADNIMP BIT(7)
+#define MXC_UART_CR3_RXDSEN BIT(6)
+#define MXC_UART_CR3_AIRINTEN BIT(5)
+#define MXC_UART_CR3_AWAKEN BIT(4)
+#define MXC_UART_CR3_DTRDEN BIT(3)
+#define MXC_UART_CR3_RXDMUXSEL BIT(2)
+#define MXC_UART_CR3_INVT BIT(1)
+#define MXC_UART_CR3_ACIEN BIT(0)
+
+#define MXC_UART_CR4_OFFSET 0x8c
+#define MXC_UART_CR4_INVR BIT(9)
+#define MXC_UART_CR4_ENIRI BIT(8)
+#define MXC_UART_CR4_WKEN BIT(7)
+#define MXC_UART_CR4_IDDMAEN BIT(6)
+#define MXC_UART_CR4_IRSC BIT(5)
+#define MXC_UART_CR4_LPBYP BIT(4)
+#define MXC_UART_CR4_TCEN BIT(3)
+#define MXC_UART_CR4_BKEN BIT(2)
+#define MXC_UART_CR4_OREN BIT(1)
+#define MXC_UART_CR4_DREN BIT(0)
+
+#define MXC_UART_FCR_OFFSET 0x90
+#define MXC_UART_FCR_TXTL_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12) |\
+ BIT(11) | BIT(10))
+#define MXC_UART_FCR_TXTL(x) (x << 10)
+#define MXC_UART_FCR_RFDIV_MASK (BIT(9) | BIT(8) | BIT(7))
+#define MXC_UART_FCR_RFDIV7 (BIT(9) | BIT(8))
+#define MXC_UART_FCR_RFDIV1 (BIT(9) | BIT(7))
+#define MXC_UART_FCR_RFDIV2 BIT(9)
+#define MXC_UART_FCR_RFDIV3 (BIT(8) | BIT(7))
+#define MXC_UART_FCR_RFDIV4 BIT(8)
+#define MXC_UART_FCR_RFDIV5 BIT(7)
+#define MXC_UART_FCR_RFDIV6 0
+#define MXC_UART_FCR_DCEDTE BIT(6)
+#define MXC_UART_FCR_RXTL_MASK (BIT(5) | BIT(4) | BIT(3) | BIT(2) |\
+ BIT(1) | BIT(0))
+#define MXC_UART_FCR_RXTL(x) x
+
+#define MXC_UART_STAT1_OFFSET 0x94
+#define MXC_UART_STAT1_PARITYERR BIT(15)
+#define MXC_UART_STAT1_RTSS BIT(14)
+#define MXC_UART_STAT1_TRDY BIT(13)
+#define MXC_UART_STAT1_RTSD BIT(12)
+#define MXC_UART_STAT1_ESCF BIT(11)
+#define MXC_UART_STAT1_FRAMEERR BIT(10)
+#define MXC_UART_STAT1_RRDY BIT(9)
+#define MXC_UART_STAT1_AGTIM BIT(8)
+#define MXC_UART_STAT1_DTRD BIT(7)
+#define MXC_UART_STAT1_RXDS BIT(6)
+#define MXC_UART_STAT1_AIRINT BIT(5)
+#define MXC_UART_STAT1_AWAKE BIT(4)
+#define MXC_UART_STAT1_SAD BIT(3)
+
+#define MXC_UART_STAT2_OFFSET 0x98
+#define MXC_UART_STAT2_ADET BIT(15)
+#define MXC_UART_STAT2_TXFE BIT(14)
+#define MXC_UART_STAT2_DTRF BIT(13)
+#define MXC_UART_STAT2_IDLE BIT(12)
+#define MXC_UART_STAT2_ACST BIT(11)
+#define MXC_UART_STAT2_RIDELT BIT(10)
+#define MXC_UART_STAT2_RIIN BIT(9)
+#define MXC_UART_STAT2_IRINT BIT(8)
+#define MXC_UART_STAT2_WAKE BIT(7)
+#define MXC_UART_STAT2_DCDDELT BIT(6)
+#define MXC_UART_STAT2_DCDIN BIT(5)
+#define MXC_UART_STAT2_RTSF BIT(4)
+#define MXC_UART_STAT2_TXDC BIT(3)
+#define MXC_UART_STAT2_BRCD BIT(2)
+#define MXC_UART_STAT2_ORE BIT(1)
+#define MXC_UART_STAT2_RCR BIT(0)
+
+#define MXC_UART_ESC_OFFSET 0x9c
+
+#define MXC_UART_TIM_OFFSET 0xa0
+
+#define MXC_UART_BIR_OFFSET 0xa4
+
+#define MXC_UART_BMR_OFFSET 0xa8
+
+#define MXC_UART_BRC_OFFSET 0xac
+
+#define MXC_UART_ONEMS_OFFSET 0xb0
+
+#define MXC_UART_TS_OFFSET 0xb4
+#define MXC_UART_TS_FRCPERR BIT(13)
+#define MXC_UART_TS_LOOP BIT(12)
+#define MXC_UART_TS_DBGEN BIT(11)
+#define MXC_UART_TS_LOOPIR BIT(10)
+#define MXC_UART_TS_RXDBG BIT(9)
+#define MXC_UART_TS_TXEMPTY BIT(6)
+#define MXC_UART_TS_RXEMPTY BIT(5)
+#define MXC_UART_TS_TXFULL BIT(4)
+#define MXC_UART_TS_RXFULL BIT(3)
+#define MXC_UART_TS_SOFTRST BIT(0)
+
+#endif /* __MXC_CONSOLE_H__ */
diff --git a/include/drivers/nxp/nxp_timer.h b/include/drivers/nxp/nxp_timer.h
new file mode 100644
index 0000000..cf3ec23
--- /dev/null
+++ b/include/drivers/nxp/nxp_timer.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NXP_TIMER_H__
+#define __NXP_TIMER_H__
+
+/*
+ * Program nxp timer to fire an interrupt after `time_out_ms` milliseconds.
+ *
+ * Always return 0
+ */
+int nxp_timer_program(unsigned long time_out_ms);
+
+/*
+ * Cancel the currently programmed nxp timer interrupt
+ *
+ * Always return 0
+ */
+int nxp_timer_cancel(void);
+
+/*
+ * Initializes the nxp timer so that it can be used for programming
+ * timer interrupt.
+ * Must be called by the primary CPU only.
+ *
+ * Always return 0
+ */
+int nxp_timer_init(uintptr_t base_addr);
+
+/*
+ * Handler to acknowledge and de-activate the nxp timer interrupt
+ *
+ * Always return 0
+ */
+int nxp_timer_handler(void);
+
+#endif /* __NXP_TIMER_H__ */
diff --git a/include/plat/nxp/common/plat_nxp.h b/include/plat/nxp/common/plat_nxp.h
new file mode 100644
index 0000000..e00b3a3
--- /dev/null
+++ b/include/plat/nxp/common/plat_nxp.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLAT_NXP_H__
+#define __PLAT_NXP_H__
+
+/*
+ * Initialises the IO
+ * Returns: IO_SUCCESS
+ * IO_FAIL
+ * IO_NOT_SUPPORTED
+ * IO_RESOURCES_EXHAUSTED
+ */
+int nxp_io_setup(void);
+
+/* Initialises the IO and the GIC. */
+void nxp_platform_setup(void);
+
+/*******************************************************************************
+ * NXP platforms porting interfaces are located below.
+ ******************************************************************************/
+
+/* Initialises the Generic Interrupt Controller (GIC). */
+void plat_nxp_gic_init(void);
+
+#endif /* __PLAT_NXP_H__ */
diff --git a/plat/nxp/board/warp7/aarch32/plat_helpers.S b/plat/nxp/board/warp7/aarch32/plat_helpers.S
new file mode 100644
index 0000000..8aec9aa
--- /dev/null
+++ b/plat/nxp/board/warp7/aarch32/plat_helpers.S
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+
+ .globl platform_get_core_pos
+ /*
+ * Return 0 because imx7s only has one A7 core
+ */
+func platform_get_core_pos
+ mov r0, #0
+ bx lr
+endfunc platform_get_core_pos
diff --git a/plat/nxp/board/warp7/include/platform_def.h b/plat/nxp/board/warp7/include/platform_def.h
new file mode 100644
index 0000000..a6077b6
--- /dev/null
+++ b/plat/nxp/board/warp7/include/platform_def.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include "../warp7_def.h"
+
+/*******************************************************************************
+ * Platform definitions used by common code
+ ******************************************************************************/
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#ifndef AARCH32
+#error "Error: AARCH32 should be defined for Warp7"
+#else
+#define PLATFORM_LINKER_FORMAT "elf32-littlearm"
+#define PLATFORM_LINKER_ARCH arm
+#endif
+
+/*******************************************************************************
+ * Run-time address of the TFTF image.
+ * It has to match the location where the trusted firmware loads the BL3-3
+ * image.
+ ******************************************************************************/
+#define TFTF_BASE 0x9f000000
+
+#define DRAM_BASE 0x80000000
+#define DRAM_SIZE 0x20000000
+
+/* Base address of non-trusted watchdog */
+#define IMX7S_WDOG_BASE 0x30280000
+
+/* general timer1 */
+#define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000)
+#define IRQ_GPT1 87
+
+/* Memory mapped Generic timer(system counter) interfaces. */
+#define SYS_CNT_BASE1 (AIPS2_BASE + 0x2c0000)
+
+/* Size of a block as mapped by a second-level translation table */
+#define L2_BLOCK_SIZE 0x80000
+
+/*
+ * Size of memory region configured as secure DRAM by the trusted firmware
+ * through the TrustZone Controller.
+ * TODO: Get rid of this constant once tsp_crash_reporting_test1() function has
+ * been fixed.
+ */
+#define DRAM_TZ_SIZE 0x01000000ull
+
+/*******************************************************************************
+ * Base address and size for non-trusted SRAM.
+ ******************************************************************************/
+#define NSRAM_BASE (0x2e000000)
+#define NSRAM_SIZE (0x00008000)
+
+/*******************************************************************************
+ * Corresponds to the function ID of the BL1 SMC handler for FWU process.
+ ******************************************************************************/
+#define BL1_SMC_CALL_COUNT 0x0
+#define BL1_SMC_UID 0x1
+/* SMC #0x2 reserved */
+#define BL1_SMC_VERSION 0x3
+#define FWU_SMC_IMAGE_COPY 0x10
+#define FWU_SMC_IMAGE_AUTH 0x11
+#define FWU_SMC_IMAGE_EXECUTE 0x12
+#define FWU_SMC_IMAGE_RESUME 0x13
+#define FWU_SMC_SEC_IMAGE_DONE 0x14
+#define FWU_SMC_UPDATE_DONE 0x15
+#define FWU_SMC_IMAGE_RESET 0x16
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+
+#define PLATFORM_STACK_SIZE 0xb80
+
+/* Size of coherent stacks for debug and release builds */
+#if DEBUG
+#define PCPU_DV_MEM_STACK_SIZE 0x400
+#else
+#define PCPU_DV_MEM_STACK_SIZE 0x300
+#endif
+
+#define IRQ_STACK_SIZE 0x800
+
+#define PLATFORM_SYSTEM_COUNT 1
+#define PLATFORM_CLUSTER_COUNT 1
+#define PLATFORM_CLUSTER1_CORE_COUNT 1
+#define PLATFORM_CORE_COUNT 1
+#define PLATFORM_MAX_CPUS_PER_CLUSTER 1
+
+#ifdef MPIDR_MAX_AFFLVL
+#undef MPIDR_MAX_AFFLVL
+#endif
+#define MPIDR_MAX_AFFLVL 1
+#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \
+ PLATFORM_CORE_COUNT)
+#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
+#define PLAT_MAX_PWR_LEVEL PLATFORM_MAX_AFFLVL
+#define PLAT_MAX_PWR_STATES_PER_LVL 2
+
+/* Local state bit width for each level in the state-ID field of power state */
+#define PLAT_LOCAL_PSTATE_WIDTH 4
+
+#define MAX_IO_DEVICES 1
+#define MAX_IO_HANDLES 1
+
+/*
+ * If you want to run without support for non-volatile memory (due to e.g.
+ * unavailability of a flash driver), DRAM can be used instead as workaround.
+ * The TFTF binary itself is loaded at 0xE0000000 so we have plenty of free
+ * memory at the beginning of the DRAM. Let's use the first 128MB.
+ *
+ * Please note that this won't be suitable for all test scenarios and
+ * for this reason some tests will be disabled in this configuration.
+ */
+#define TFTF_NVM_OFFSET 0x0
+#define TFTF_NVM_SIZE 0x8000000 /* 128 MB */
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define ADDR_SPACE_SIZE (1ull << 32)
+#define MAX_XLAT_TABLES 4
+#define MAX_MMAP_REGIONS 16
+
+/*******************************************************************************
+ * Used to align variables on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT 6
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+/*******************************************************************************
+ * Non-Secure Software Generated Interupts IDs
+ ******************************************************************************/
+#define IRQ_NS_SGI_0 0
+#define IRQ_NS_SGI_1 1
+#define IRQ_NS_SGI_2 2
+#define IRQ_NS_SGI_3 3
+#define IRQ_NS_SGI_4 4
+#define IRQ_NS_SGI_5 5
+#define IRQ_NS_SGI_6 6
+#define IRQ_NS_SGI_7 7
+
+/* Per Table 7-1 of iMX7S reference manual */
+#define PLAT_MAX_SPI_OFFSET_ID 127
+
+#define IRQ_CNTPSIRQ1 92
+/* Per-CPU Hypervisor Timer Interrupt ID */
+#define IRQ_PCPU_HP_TIMER 26
+/* Per-CPU Non-Secure Timer Interrupt ID */
+#define IRQ_PCPU_NS_TIMER 30
+
+/*
+ * Times(in ms) used by test code for completion of different events.
+ * Suspend entry time for debug build is high due to the time taken
+ * by the VERBOSE/INFO prints. The value considers the worst case scenario
+ * where all CPUs are going and coming out of suspend continuously.
+ */
+#if DEBUG
+#define PLAT_SUSPEND_ENTRY_TIME 0x100
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME 0x200
+#else
+#define PLAT_SUSPEND_ENTRY_TIME 10
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME 20
+#endif
+
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/nxp/board/warp7/plat_setup.c b/plat/nxp/board/warp7/plat_setup.c
new file mode 100644
index 0000000..f68a653
--- /dev/null
+++ b/plat/nxp/board/warp7/plat_setup.c
@@ -0,0 +1,28 @@
+/** @file
+*
+* Copyright (c) 2018, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <arm_gic.h>
+#include <mmio.h>
+#include <plat_nxp.h>
+#include <platform.h>
+
+void tftf_platform_setup(void)
+{
+ nxp_platform_setup();
+}
+
+void plat_nxp_gic_init(void)
+{
+ arm_gic_init(GICC_BASE, GICD_BASE, GICR_BASE);
+}
diff --git a/plat/nxp/board/warp7/platform.mk b/plat/nxp/board/warp7/platform.mk
new file mode 100644
index 0000000..b202361
--- /dev/null
+++ b/plat/nxp/board/warp7/platform.mk
@@ -0,0 +1,56 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+PLAT_INCLUDES := -Iplat/nxp/board/warp7/include/ -Iinclude/drivers/nxp
+
+PLAT_SOURCES := drivers/arm/gic/arm_gic_v2.c \
+ drivers/arm/gic/gic_v2.c \
+ drivers/arm/timer/private_timer.c \
+ plat/nxp/board/warp7/aarch32/plat_helpers.S \
+ plat/nxp/board/warp7/warp7_pwr_state.c \
+ plat/nxp/board/warp7/warp7_topology.c \
+ plat/nxp/board/warp7/plat_setup.c
+
+TESTS_SOURCES += tests/runtime_services/trusted_os/tsp/test_irq_spurious_gicv2.c
+
+# Some tests are not supported on warp7.
+PLAT_TESTS_SKIP_LIST := plat/nxp/board/warp7/warp7_tests_to_skip.txt
+
+PLAT_SUPPORTS_NS_RESET := 1
+
+# Process PLAT_SUPPORTS_NS_RESET flag
+$(eval $(call assert_boolean,PLAT_SUPPORTS_NS_RESET))
+$(eval $(call add_define,PLAT_SUPPORTS_NS_RESET))
+
+ifeq (${FIRMWARE_UPDATE},1)
+$(error "FIRMWARE_UPDATE is not supported on Warp7")
+endif
+
+include plat/nxp/common/nxp_common.mk
diff --git a/plat/nxp/board/warp7/warp7_def.h b/plat/nxp/board/warp7/warp7_def.h
new file mode 100644
index 0000000..0e4a156
--- /dev/null
+++ b/plat/nxp/board/warp7/warp7_def.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __WARP7_DEF_H__
+#define __WARP7_DEF_H__
+
+#include <platform_def.h>
+
+/*******************************************************************************
+ * Warp7 memory map related constants
+ ******************************************************************************/
+/* Following covers AIPS Peripherals and ARM Peripherals */
+#define DEVICE0_BASE 0x30000000
+#define DEVICE0_SIZE 0x01400000
+
+/* Peripherals like GPIO live in the AIPS range */
+#define AIPS1_BASE 0x30000000 /* AIPS1 */
+#define AIPS2_BASE 0x30400000 /* AIPS2 */
+#define AIPS3_BASE 0x30800000 /* AIPS3 */
+#define AIPS4_BASE 0x30c00000 /* AIPS4 */
+/*******************************************************************************
+ * GIC-400 & interrupt handling related constants
+ ******************************************************************************/
+#define GICD_BASE 0x31001000
+#define GICC_BASE 0x31002000
+/* Warp7 doesn't support GIC Redistributor, it's a GICv3 feature */
+#define GICR_BASE 0
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+/* SoC UART0 */
+#define PLAT_WARP7_BOOT_UART_BASE 0x30860000
+#define PLAT_WARP7_BOOT_UART_CLK_IN_HZ 24000000
+#define PLAT_WARP7_BOOT_UART_BAUDRATE 115200
+
+#define PLAT_ARM_UART_BASE PLAT_WARP7_BOOT_UART_BASE
+#define PLAT_ARM_UART_CLK_IN_HZ PLAT_WARP7_BOOT_UART_CLK_IN_HZ
+
+/*******************************************************************************
+ * timer related constants
+ ******************************************************************************/
+#define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000)
+
+#endif /* __WARP7_DEF_H__ */
diff --git a/plat/nxp/board/warp7/warp7_pwr_state.c b/plat/nxp/board/warp7/warp7_pwr_state.c
new file mode 100644
index 0000000..8c0b035
--- /dev/null
+++ b/plat/nxp/board/warp7/warp7_pwr_state.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arch.h>
+#include <platform.h>
+#include <psci.h>
+#include <stddef.h>
+
+/*
+ * State IDs for local power states on Warp7.
+ */
+#define WARP7_RUN_STATE_ID 0 /* Valid for CPUs and Clusters */
+#define WARP7_RETENTION_STATE_ID 1 /* Valid for only CPUs */
+#define WARP7_OFF_STATE_ID 2 /* Valid for CPUs and Clusters */
+
+/*
+ * Suspend depth definitions for each power state
+ */
+typedef enum {
+ WARP7_RUN_DEPTH = 0,
+ WARP7_RETENTION_DEPTH,
+ WARP7_OFF_DEPTH,
+} suspend_depth_t;
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+ {WARP7_RETENTION_DEPTH, WARP7_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY},
+ {WARP7_OFF_DEPTH, WARP7_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+static const plat_state_prop_t system_state_prop[] = {
+ {WARP7_RETENTION_DEPTH, WARP7_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY},
+ {WARP7_OFF_DEPTH, WARP7_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+ switch (level) {
+ case MPIDR_AFFLVL0:
+ return core_state_prop;
+ case MPIDR_AFFLVL1:
+ return system_state_prop;
+ default:
+ return NULL;
+ }
+}
diff --git a/plat/nxp/board/warp7/warp7_tests_to_skip.txt b/plat/nxp/board/warp7/warp7_tests_to_skip.txt
new file mode 100644
index 0000000..173c3f9
--- /dev/null
+++ b/plat/nxp/board/warp7/warp7_tests_to_skip.txt
@@ -0,0 +1,8 @@
+# Skip features that are not supported on Warp7.
+PSCI System Suspend Validation
+PSCI STAT/Stats test cases after system suspend
+IRQ support in TSP/Resume preempted STD SMC after PSCI SYSTEM SUSPEND
+PSCI SYSTEM SUSPEND stress tests
+PSCI Affinity Info
+Query runtime services
+CPU Hotplug
diff --git a/plat/nxp/board/warp7/warp7_topology.c b/plat/nxp/board/warp7/warp7_topology.c
new file mode 100644
index 0000000..e3be8f0
--- /dev/null
+++ b/plat/nxp/board/warp7/warp7_topology.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <assert.h>
+#include <plat_topology.h>
+#include <platform_def.h>
+#include <stddef.h>
+#include <tftf_lib.h>
+
+/*
+ * The Warp7 power domain tree descriptor. Warp7 implements a system
+ * power domain at the level 2. The first entry in the power domain descriptor
+ * specifies the number of power domains at the highest power level. For Warp7
+ * this is 1 i.e. the number of system power domain.
+ */
+static const unsigned char warp7_power_domain_tree_desc[] = {
+ PLATFORM_CLUSTER_COUNT,
+ /* Number of children for the first cluster */
+ PLATFORM_CLUSTER1_CORE_COUNT,
+};
+
+const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
+{
+ return warp7_power_domain_tree_desc;
+}
+
+uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
+{
+ assert(core_pos < PLATFORM_CORE_COUNT);
+
+ return 0;
+}
diff --git a/plat/nxp/common/nxp_common.mk b/plat/nxp/common/nxp_common.mk
new file mode 100644
index 0000000..9ea6457
--- /dev/null
+++ b/plat/nxp/common/nxp_common.mk
@@ -0,0 +1,43 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+PLAT_INCLUDES += -Iinclude/plat/nxp/common/
+
+PLAT_SOURCES += drivers/arm/gic/gic_common.c \
+ drivers/nxp/timer/nxp_timer.c \
+ drivers/nxp/uart/nxp_console.S \
+ plat/nxp/common/nxp_setup.c \
+ plat/nxp/common/plat_timers.c
+
+ifeq (${USE_NVM},1)
+PLAT_SOURCES += drivers/io/io_storage.c \
+ drivers/io/nxp/mmc.c \
+ plat/nxp/common/nxp_io_storage.c
+endif
diff --git a/plat/nxp/common/nxp_setup.c b/plat/nxp/common/nxp_setup.c
new file mode 100644
index 0000000..055720d
--- /dev/null
+++ b/plat/nxp/common/nxp_setup.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm_gic.h>
+#include <console.h>
+#include <debug.h>
+#include <io_storage.h>
+#include <plat_nxp.h>
+#include <platform_def.h>
+#include <platform.h>
+
+#pragma weak tftf_platform_setup
+
+void nxp_platform_setup(void)
+{
+ plat_nxp_gic_init();
+
+ arm_gic_setup_global();
+ arm_gic_setup_local();
+}
+
+void tftf_platform_setup(void)
+{
+ nxp_platform_setup();
+}
+
+void tftf_plat_arch_setup(void)
+{
+}
+
+void tftf_early_platform_setup(void)
+{
+ console_init(PLAT_WARP7_BOOT_UART_BASE, PLAT_WARP7_BOOT_UART_CLK_IN_HZ,
+ PLAT_WARP7_BOOT_UART_BAUDRATE);
+ printf("TFTP nxp console init finished\n");
+}
+
+void tftf_plat_reset(void)
+{
+ //nxp_wdog_start(1);
+}
diff --git a/plat/nxp/common/plat_timers.c b/plat/nxp/common/plat_timers.c
new file mode 100644
index 0000000..9137601
--- /dev/null
+++ b/plat/nxp/common/plat_timers.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <platform.h>
+#include <stddef.h>
+#include <nxp_timer.h>
+#include <timer.h>
+
+#pragma weak plat_initialise_timer_ops
+
+static const plat_timer_t plat_timers = {
+ .program = nxp_timer_program,
+ .cancel = nxp_timer_cancel,
+ .handler = nxp_timer_handler,
+ .timer_step_value = 2,
+ .timer_irq = IRQ_GPT1
+};
+
+int plat_initialise_timer_ops(const plat_timer_t **timer_ops)
+{
+ assert(timer_ops != NULL);
+ *timer_ops = &plat_timers;
+
+ /* Initialise the system timer */
+ nxp_timer_init(GPT1_BASE_ADDR);
+
+ return 0;
+}