diff options
Diffstat (limited to 'plat/nxp/board/warp7')
| -rw-r--r-- | plat/nxp/board/warp7/aarch32/plat_helpers.S | 41 | ||||
| -rw-r--r-- | plat/nxp/board/warp7/include/platform_def.h | 203 | ||||
| -rw-r--r-- | plat/nxp/board/warp7/plat_setup.c | 28 | ||||
| -rw-r--r-- | plat/nxp/board/warp7/platform.mk | 56 | ||||
| -rw-r--r-- | plat/nxp/board/warp7/warp7_def.h | 72 | ||||
| -rw-r--r-- | plat/nxp/board/warp7/warp7_pwr_state.c | 74 | ||||
| -rw-r--r-- | plat/nxp/board/warp7/warp7_tests_to_skip.txt | 8 | ||||
| -rw-r--r-- | plat/nxp/board/warp7/warp7_topology.c | 60 |
8 files changed, 542 insertions, 0 deletions
diff --git a/plat/nxp/board/warp7/aarch32/plat_helpers.S b/plat/nxp/board/warp7/aarch32/plat_helpers.S new file mode 100644 index 0000000..8aec9aa --- /dev/null +++ b/plat/nxp/board/warp7/aarch32/plat_helpers.S @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include <asm_macros.S> + + .globl platform_get_core_pos + /* + * Return 0 because imx7s only has one A7 core + */ +func platform_get_core_pos + mov r0, #0 + bx lr +endfunc platform_get_core_pos diff --git a/plat/nxp/board/warp7/include/platform_def.h b/plat/nxp/board/warp7/include/platform_def.h new file mode 100644 index 0000000..a6077b6 --- /dev/null +++ b/plat/nxp/board/warp7/include/platform_def.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include "../warp7_def.h" + +/******************************************************************************* + * Platform definitions used by common code + ******************************************************************************/ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#ifndef AARCH32 +#error "Error: AARCH32 should be defined for Warp7" +#else +#define PLATFORM_LINKER_FORMAT "elf32-littlearm" +#define PLATFORM_LINKER_ARCH arm +#endif + +/******************************************************************************* + * Run-time address of the TFTF image. + * It has to match the location where the trusted firmware loads the BL3-3 + * image. + ******************************************************************************/ +#define TFTF_BASE 0x9f000000 + +#define DRAM_BASE 0x80000000 +#define DRAM_SIZE 0x20000000 + +/* Base address of non-trusted watchdog */ +#define IMX7S_WDOG_BASE 0x30280000 + +/* general timer1 */ +#define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000) +#define IRQ_GPT1 87 + +/* Memory mapped Generic timer(system counter) interfaces. */ +#define SYS_CNT_BASE1 (AIPS2_BASE + 0x2c0000) + +/* Size of a block as mapped by a second-level translation table */ +#define L2_BLOCK_SIZE 0x80000 + +/* + * Size of memory region configured as secure DRAM by the trusted firmware + * through the TrustZone Controller. + * TODO: Get rid of this constant once tsp_crash_reporting_test1() function has + * been fixed. + */ +#define DRAM_TZ_SIZE 0x01000000ull + +/******************************************************************************* + * Base address and size for non-trusted SRAM. + ******************************************************************************/ +#define NSRAM_BASE (0x2e000000) +#define NSRAM_SIZE (0x00008000) + +/******************************************************************************* + * Corresponds to the function ID of the BL1 SMC handler for FWU process. + ******************************************************************************/ +#define BL1_SMC_CALL_COUNT 0x0 +#define BL1_SMC_UID 0x1 +/* SMC #0x2 reserved */ +#define BL1_SMC_VERSION 0x3 +#define FWU_SMC_IMAGE_COPY 0x10 +#define FWU_SMC_IMAGE_AUTH 0x11 +#define FWU_SMC_IMAGE_EXECUTE 0x12 +#define FWU_SMC_IMAGE_RESUME 0x13 +#define FWU_SMC_SEC_IMAGE_DONE 0x14 +#define FWU_SMC_UPDATE_DONE 0x15 +#define FWU_SMC_IMAGE_RESET 0x16 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +#define PLATFORM_STACK_SIZE 0xb80 + +/* Size of coherent stacks for debug and release builds */ +#if DEBUG +#define PCPU_DV_MEM_STACK_SIZE 0x400 +#else +#define PCPU_DV_MEM_STACK_SIZE 0x300 +#endif + +#define IRQ_STACK_SIZE 0x800 + +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_CLUSTER1_CORE_COUNT 1 +#define PLATFORM_CORE_COUNT 1 +#define PLATFORM_MAX_CPUS_PER_CLUSTER 1 + +#ifdef MPIDR_MAX_AFFLVL +#undef MPIDR_MAX_AFFLVL +#endif +#define MPIDR_MAX_AFFLVL 1 +#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 +#define PLAT_MAX_PWR_LEVEL PLATFORM_MAX_AFFLVL +#define PLAT_MAX_PWR_STATES_PER_LVL 2 + +/* Local state bit width for each level in the state-ID field of power state */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 + +#define MAX_IO_DEVICES 1 +#define MAX_IO_HANDLES 1 + +/* + * If you want to run without support for non-volatile memory (due to e.g. + * unavailability of a flash driver), DRAM can be used instead as workaround. + * The TFTF binary itself is loaded at 0xE0000000 so we have plenty of free + * memory at the beginning of the DRAM. Let's use the first 128MB. + * + * Please note that this won't be suitable for all test scenarios and + * for this reason some tests will be disabled in this configuration. + */ +#define TFTF_NVM_OFFSET 0x0 +#define TFTF_NVM_SIZE 0x8000000 /* 128 MB */ + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 4 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * Used to align variables on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/******************************************************************************* + * Non-Secure Software Generated Interupts IDs + ******************************************************************************/ +#define IRQ_NS_SGI_0 0 +#define IRQ_NS_SGI_1 1 +#define IRQ_NS_SGI_2 2 +#define IRQ_NS_SGI_3 3 +#define IRQ_NS_SGI_4 4 +#define IRQ_NS_SGI_5 5 +#define IRQ_NS_SGI_6 6 +#define IRQ_NS_SGI_7 7 + +/* Per Table 7-1 of iMX7S reference manual */ +#define PLAT_MAX_SPI_OFFSET_ID 127 + +#define IRQ_CNTPSIRQ1 92 +/* Per-CPU Hypervisor Timer Interrupt ID */ +#define IRQ_PCPU_HP_TIMER 26 +/* Per-CPU Non-Secure Timer Interrupt ID */ +#define IRQ_PCPU_NS_TIMER 30 + +/* + * Times(in ms) used by test code for completion of different events. + * Suspend entry time for debug build is high due to the time taken + * by the VERBOSE/INFO prints. The value considers the worst case scenario + * where all CPUs are going and coming out of suspend continuously. + */ +#if DEBUG +#define PLAT_SUSPEND_ENTRY_TIME 0x100 +#define PLAT_SUSPEND_ENTRY_EXIT_TIME 0x200 +#else +#define PLAT_SUSPEND_ENTRY_TIME 10 +#define PLAT_SUSPEND_ENTRY_EXIT_TIME 20 +#endif + + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/nxp/board/warp7/plat_setup.c b/plat/nxp/board/warp7/plat_setup.c new file mode 100644 index 0000000..f68a653 --- /dev/null +++ b/plat/nxp/board/warp7/plat_setup.c @@ -0,0 +1,28 @@ +/** @file +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <arm_gic.h> +#include <mmio.h> +#include <plat_nxp.h> +#include <platform.h> + +void tftf_platform_setup(void) +{ + nxp_platform_setup(); +} + +void plat_nxp_gic_init(void) +{ + arm_gic_init(GICC_BASE, GICD_BASE, GICR_BASE); +} diff --git a/plat/nxp/board/warp7/platform.mk b/plat/nxp/board/warp7/platform.mk new file mode 100644 index 0000000..b202361 --- /dev/null +++ b/plat/nxp/board/warp7/platform.mk @@ -0,0 +1,56 @@ +# +# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PLAT_INCLUDES := -Iplat/nxp/board/warp7/include/ -Iinclude/drivers/nxp + +PLAT_SOURCES := drivers/arm/gic/arm_gic_v2.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/timer/private_timer.c \ + plat/nxp/board/warp7/aarch32/plat_helpers.S \ + plat/nxp/board/warp7/warp7_pwr_state.c \ + plat/nxp/board/warp7/warp7_topology.c \ + plat/nxp/board/warp7/plat_setup.c + +TESTS_SOURCES += tests/runtime_services/trusted_os/tsp/test_irq_spurious_gicv2.c + +# Some tests are not supported on warp7. +PLAT_TESTS_SKIP_LIST := plat/nxp/board/warp7/warp7_tests_to_skip.txt + +PLAT_SUPPORTS_NS_RESET := 1 + +# Process PLAT_SUPPORTS_NS_RESET flag +$(eval $(call assert_boolean,PLAT_SUPPORTS_NS_RESET)) +$(eval $(call add_define,PLAT_SUPPORTS_NS_RESET)) + +ifeq (${FIRMWARE_UPDATE},1) +$(error "FIRMWARE_UPDATE is not supported on Warp7") +endif + +include plat/nxp/common/nxp_common.mk diff --git a/plat/nxp/board/warp7/warp7_def.h b/plat/nxp/board/warp7/warp7_def.h new file mode 100644 index 0000000..0e4a156 --- /dev/null +++ b/plat/nxp/board/warp7/warp7_def.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __WARP7_DEF_H__ +#define __WARP7_DEF_H__ + +#include <platform_def.h> + +/******************************************************************************* + * Warp7 memory map related constants + ******************************************************************************/ +/* Following covers AIPS Peripherals and ARM Peripherals */ +#define DEVICE0_BASE 0x30000000 +#define DEVICE0_SIZE 0x01400000 + +/* Peripherals like GPIO live in the AIPS range */ +#define AIPS1_BASE 0x30000000 /* AIPS1 */ +#define AIPS2_BASE 0x30400000 /* AIPS2 */ +#define AIPS3_BASE 0x30800000 /* AIPS3 */ +#define AIPS4_BASE 0x30c00000 /* AIPS4 */ +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ +#define GICD_BASE 0x31001000 +#define GICC_BASE 0x31002000 +/* Warp7 doesn't support GIC Redistributor, it's a GICv3 feature */ +#define GICR_BASE 0 + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +/* SoC UART0 */ +#define PLAT_WARP7_BOOT_UART_BASE 0x30860000 +#define PLAT_WARP7_BOOT_UART_CLK_IN_HZ 24000000 +#define PLAT_WARP7_BOOT_UART_BAUDRATE 115200 + +#define PLAT_ARM_UART_BASE PLAT_WARP7_BOOT_UART_BASE +#define PLAT_ARM_UART_CLK_IN_HZ PLAT_WARP7_BOOT_UART_CLK_IN_HZ + +/******************************************************************************* + * timer related constants + ******************************************************************************/ +#define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000) + +#endif /* __WARP7_DEF_H__ */ diff --git a/plat/nxp/board/warp7/warp7_pwr_state.c b/plat/nxp/board/warp7/warp7_pwr_state.c new file mode 100644 index 0000000..8c0b035 --- /dev/null +++ b/plat/nxp/board/warp7/warp7_pwr_state.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include <arch.h> +#include <platform.h> +#include <psci.h> +#include <stddef.h> + +/* + * State IDs for local power states on Warp7. + */ +#define WARP7_RUN_STATE_ID 0 /* Valid for CPUs and Clusters */ +#define WARP7_RETENTION_STATE_ID 1 /* Valid for only CPUs */ +#define WARP7_OFF_STATE_ID 2 /* Valid for CPUs and Clusters */ + +/* + * Suspend depth definitions for each power state + */ +typedef enum { + WARP7_RUN_DEPTH = 0, + WARP7_RETENTION_DEPTH, + WARP7_OFF_DEPTH, +} suspend_depth_t; + +/* The state property array with details of idle state possible for the core */ +static const plat_state_prop_t core_state_prop[] = { + {WARP7_RETENTION_DEPTH, WARP7_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY}, + {WARP7_OFF_DEPTH, WARP7_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN}, + {0}, +}; + +static const plat_state_prop_t system_state_prop[] = { + {WARP7_RETENTION_DEPTH, WARP7_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY}, + {WARP7_OFF_DEPTH, WARP7_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN}, + {0}, +}; + +const plat_state_prop_t *plat_get_state_prop(unsigned int level) +{ + switch (level) { + case MPIDR_AFFLVL0: + return core_state_prop; + case MPIDR_AFFLVL1: + return system_state_prop; + default: + return NULL; + } +} diff --git a/plat/nxp/board/warp7/warp7_tests_to_skip.txt b/plat/nxp/board/warp7/warp7_tests_to_skip.txt new file mode 100644 index 0000000..173c3f9 --- /dev/null +++ b/plat/nxp/board/warp7/warp7_tests_to_skip.txt @@ -0,0 +1,8 @@ +# Skip features that are not supported on Warp7. +PSCI System Suspend Validation +PSCI STAT/Stats test cases after system suspend +IRQ support in TSP/Resume preempted STD SMC after PSCI SYSTEM SUSPEND +PSCI SYSTEM SUSPEND stress tests +PSCI Affinity Info +Query runtime services +CPU Hotplug diff --git a/plat/nxp/board/warp7/warp7_topology.c b/plat/nxp/board/warp7/warp7_topology.c new file mode 100644 index 0000000..e3be8f0 --- /dev/null +++ b/plat/nxp/board/warp7/warp7_topology.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include <assert.h> +#include <plat_topology.h> +#include <platform_def.h> +#include <stddef.h> +#include <tftf_lib.h> + +/* + * The Warp7 power domain tree descriptor. Warp7 implements a system + * power domain at the level 2. The first entry in the power domain descriptor + * specifies the number of power domains at the highest power level. For Warp7 + * this is 1 i.e. the number of system power domain. + */ +static const unsigned char warp7_power_domain_tree_desc[] = { + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first cluster */ + PLATFORM_CLUSTER1_CORE_COUNT, +}; + +const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void) +{ + return warp7_power_domain_tree_desc; +} + +uint64_t tftf_plat_get_mpidr(unsigned int core_pos) +{ + assert(core_pos < PLATFORM_CORE_COUNT); + + return 0; +} |