diff options
| author | Mourad Goumrhar <Mourad.Goumrhar@se.com> | 2020-10-12 17:06:39 +0200 |
|---|---|---|
| committer | Mourad Goumrhar <Mourad.Goumrhar@se.com> | 2021-02-16 16:48:07 +0100 |
| commit | 09773bb16437033258705dd14134d183e4e7a4d1 (patch) | |
| tree | 9a02a63e9b5ec7710bcfa214802fe6b7121fa823 | |
| parent | e786fb75401bf5232c2ae4b00df3433230cb67f8 (diff) | |
plat-rzn1: Add Cortex-M3 startlinaro-rel-2021.08-dunfelllinaro-rel-2020.09-dunfell.3-rc2linaro-rel-2020.09-dunfell.3-rc1linaro-rel-2020.09-dunfell.3linaro-rel-2020.09-dunfell.2-rc2linaro-rel-2020.09-dunfell.2-rc1linaro-rel-2020.09-dunfell.2
Add CFG_BOOT_CM3 flag (default=y) to start the Cortex-M3 after
intialization.
Signed-off-by: Mourad Goumrhar <Mourad.Goumrhar@se.com>
| -rw-r--r-- | core/arch/arm/plat-rzn1/conf.mk | 2 | ||||
| -rw-r--r-- | core/arch/arm/plat-rzn1/main.c | 36 | ||||
| -rw-r--r-- | core/arch/arm/plat-rzn1/platform_config.h | 6 |
3 files changed, 41 insertions, 3 deletions
diff --git a/core/arch/arm/plat-rzn1/conf.mk b/core/arch/arm/plat-rzn1/conf.mk index 488d1d6c..2a5b68e0 100644 --- a/core/arch/arm/plat-rzn1/conf.mk +++ b/core/arch/arm/plat-rzn1/conf.mk @@ -31,3 +31,5 @@ arm32-platform-cflags += -Wno-error=cast-align #$(call force,CFG_CRYPTO_SHA256_ARM32_CE,n) #$(call force,CFG_CRYPTO_SHA1_ARM32_CE,n) +# Start Cortex-M3 +CFG_BOOT_CM3 ?= y
\ No newline at end of file diff --git a/core/arch/arm/plat-rzn1/main.c b/core/arch/arm/plat-rzn1/main.c index 87b1c9ec..cdda545a 100644 --- a/core/arch/arm/plat-rzn1/main.c +++ b/core/arch/arm/plat-rzn1/main.c @@ -51,9 +51,12 @@ #include <rzn1_tz.h> #define SYSCTRL_BASE 0x4000C000 -#define SYSCTRL_REG_RSTEN (SYSCTRL_BASE + 0x120) -#define SYSCTRL_REG_RSTCTRL (SYSCTRL_BASE + 0x198) -#define SYSCTRL_BOOTADDR_REG (SYSCTRL_BASE + 0x204) +#define SYSCTRL_REG_RSTEN (SYSCTRL_BASE + 0x120) +#define SYSCTRL_PWRCTRL_CM3 (SYSCTRL_BASE + 0x174) +#define SYSCTRL_PWRSTAT_CM3 (SYSCTRL_BASE + 0x178) +#define SYSCTRL_REG_RSTCTRL (SYSCTRL_BASE + 0x198) +#define SYSCTRL_BOOTADDR_REG (SYSCTRL_BASE + 0x204) + #define SYSCTRL_REG_RSTEN_MRESET_EN 0 #define SYSCTRL_REG_RSTEN_SWRST_EN 6 @@ -61,6 +64,9 @@ void rzn1_init(void); static void rzn1_tz_init(void); +#ifdef CFG_BOOT_CM3 +static void rzn1_cm3_start(void); +#endif static struct rzn1_ns16550_data console_data; static struct gic_data gic_data; @@ -258,7 +264,31 @@ static void rzn1_tz_init(void) TZ_TARG_UA_SEC); } +#ifdef CFG_BOOT_CM3 +static void rzn1_cm3_start(void) +{ + vaddr_t cm3_pwrctrl_reg = core_mmu_get_va(SYSCTRL_PWRCTRL_CM3, MEM_AREA_IO_SEC); + vaddr_t cm3_pwrstat_reg = core_mmu_get_va(SYSCTRL_PWRSTAT_CM3, MEM_AREA_IO_SEC); + + IMSG("Starting Cortex-M3"); + // Master Idle Request to the interconnect for CM3. + io_clrbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_MIREQ_A); + + // Wait for Master Idle Request Acknowledge for CM3 + while (io_read32(cm3_pwrstat_reg) & SYSCTRL_PWRSTAT_CM3_MIRACK_A) { + // wait + } + + // Clock Enable for CM3_HCLK & Active low Reset to CM3 + io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_CLKEN_A); + io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_RSTN_A); +} +#endif + void rzn1_init(void) { rzn1_tz_init(); +#ifdef CFG_BOOT_CM3 + rzn1_cm3_start(); +#endif } diff --git a/core/arch/arm/plat-rzn1/platform_config.h b/core/arch/arm/plat-rzn1/platform_config.h index 860bf339..03da0e34 100644 --- a/core/arch/arm/plat-rzn1/platform_config.h +++ b/core/arch/arm/plat-rzn1/platform_config.h @@ -44,6 +44,12 @@ #define CFG_FW_STATIC_TZA_INIT 0x4000C0D0 #define CFG_FW_STATIC_TZA_TARG 0x4000C0D4 +/* Cortex-M3 System Control bits */ +#define SYSCTRL_PWRCTRL_CM3_CLKEN_A BIT(0) +#define SYSCTRL_PWRCTRL_CM3_RSTN_A BIT(1) +#define SYSCTRL_PWRCTRL_CM3_MIREQ_A BIT(2) +#define SYSCTRL_PWRSTAT_CM3_MIRACK_A BIT(0) + // The LCES memory map is designed as if there are two DRAM banks // DRAM0 is always 128 MB // DRAM1 stand for the remaining DRAM up to the maximum |