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-rw-r--r--arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series2
-rw-r--r--arch/arm/soc/st_stm32/stm32f4/Kconfig.soc6
-rw-r--r--arch/arm/soc/st_stm32/stm32f4/flash_registers.h107
-rw-r--r--arch/arm/soc/st_stm32/stm32f4/rcc_registers.h159
-rw-r--r--arch/arm/soc/st_stm32/stm32f4/soc.c6
-rw-r--r--arch/arm/soc/st_stm32/stm32f4/soc.h7
-rw-r--r--arch/arm/soc/st_stm32/stm32f4/soc_gpio.c6
-rw-r--r--arch/arm/soc/st_stm32/stm32f4/soc_registers.h1
8 files changed, 20 insertions, 274 deletions
diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series
index f25719859..cc581d520 100644
--- a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series
+++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series
@@ -42,7 +42,7 @@ endif #SERIAL
if CLOCK_CONTROL
-config CLOCK_CONTROL_STM32F4X
+config CLOCK_CONTROL_STM32_CUBE
def_bool y
endif #CLOCK_CONTROL
diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc b/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
index 7cc99c4d3..01e9d6d9c 100644
--- a/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
+++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
@@ -12,12 +12,12 @@ depends on SOC_SERIES_STM32F4X
config SOC_STM32F401XE
bool "STM32F401XE"
-config SOC_STM32F411XE
- bool "STM32F411XE"
-
config SOC_STM32F407XX
bool "STM32F407XX"
+config SOC_STM32F411XE
+ bool "STM32F411XE"
+
config SOC_STM32F429XX
bool "STM32F429XX"
diff --git a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h
index 8b9ae4e7b..67c887348 100644
--- a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h
+++ b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h
@@ -15,15 +15,6 @@
* Chapter 3.4: Embedded Flash Memory
*/
-enum {
- STM32F4X_FLASH_LATENCY_0 = 0x0,
- STM32F4X_FLASH_LATENCY_1 = 0x1,
- STM32F4X_FLASH_LATENCY_2 = 0x2,
- STM32F4X_FLASH_LATENCY_3 = 0x3,
- STM32F4X_FLASH_LATENCY_4 = 0x4,
- STM32F4X_FLASH_LATENCY_5 = 0x5,
-};
-
union __flash_acr {
u32_t val;
struct {
@@ -48,102 +39,4 @@ struct stm32f4x_flash {
volatile u32_t optctrl;
};
-/**
- * @brief setup embedded flash controller
- *
- * Configure flash access time latency (wait states) depending on
- * SYSCLK. This code assumes that we're using a supply voltage of
- * 2.7V or higher, for lower voltages this code must be changed.
- *
- * The following tables show the required latency value required for a
- * certain CPU frequency (HCLK) and supply voltage. See the section
- * "Relation between CPU clock frequency and Flash memory read time"
- * in the reference manual for more information.
- *
- * Note that the highest frequency might be limited for other reaasons
- * than wait states, for example the STM32F405xx is limited to 168MHz
- * even with 5 wait states and the highest supply voltage.
- *
- * STM32F401xx:
- *
- * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V
- * ------- | ----------- | ----------- | ----------- | -----------
- * 0 | 30 MHz | 24 MHz | 18 MHz | 16 MHz
- * 1 | 60 MHz | 48 MHz | 36 MHz | 32 MHz
- * 2 | 84 MHz | 72 MHz | 54 MHz | 48 MHz
- * 3 | | 84 MHz | 72 MHz | 64 MHz
- * 4 | | | 84 MHz | 80 MHz
- * 5 | | | | 84 MHz
- *
- * STM32F405xx/407xx/415xx/417xx/42xxx/43xxx:
- *
- * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V
- * ------- | ----------- | ----------- | ----------- | -----------
- * 0 | 30 MHz | 24 MHz | 22 MHz | 20 MHz
- * 1 | 60 MHz | 48 MHz | 44 MHz | 40 MHz
- * 2 | 90 MHz | 72 MHz | 66 MHz | 60 MHz
- * 3 | 120 MHz | 96 MHz | 88 MHz | 80 MHz
- * 4 | 150 MHz | 120 MHz | 110 MHz | 100 MHz
- * 5 | 180 MHz | 144 MHz | 132 MHz | 120 MHz
- * 6 | | 168 MHz | 154 MHz | 140 MHz
- * 7 | | 180 MHz | 176 MHz | 160 MHz
- * 8 | | | 180 MHz | 168 MHz
- *
- * STM32F411x:
- *
- * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.7V - 2.1V
- * ------- | ----------- | ----------- | ----------- | -----------
- * 0 | 30 MHz | 24 MHz | 18 MHz | 16 MHz
- * 1 | 64 MHz | 48 MHz | 36 MHz | 32 MHz
- * 2 | 90 MHz | 72 MHz | 54 MHz | 48 MHz
- * 3 | 100 MHz | 96 MHz | 72 MHz | 64 MHz
- * 4 | | 100 MHz | 90 MHz | 80 MHz
- * 5 | | | 100 MHz | 96 MHz
- * 6 | | | | 100 MHz
- */
-static inline void __setup_flash(void)
-{
- volatile struct stm32f4x_flash *regs;
- u32_t tmpreg = 0;
-
- regs = (struct stm32f4x_flash *) FLASH_R_BASE;
-
- if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 30000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_0;
- }
-#ifdef CONFIG_SOC_STM32F401XE
- else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 84000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
- }
-#elif CONFIG_SOC_STM32F411XE
- else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 64000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 100000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3;
- }
-#elif defined(CONFIG_SOC_STM32F407XX) || defined(CONFIG_SOC_STM32F429XX)
- else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 120000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 150000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_4;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 180000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_5;
- }
-#else
-#error Flash latency configuration for MCU model is missing
-#endif
-
- /* Make sure latency was set */
- tmpreg = regs->acr.bit.latency;
-
-}
-
#endif /* _STM32F4X_FLASHREGISTERS_H_ */
diff --git a/arch/arm/soc/st_stm32/stm32f4/rcc_registers.h b/arch/arm/soc/st_stm32/stm32f4/rcc_registers.h
deleted file mode 100644
index 6cd0a97bf..000000000
--- a/arch/arm/soc/st_stm32/stm32f4/rcc_registers.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2016 Linaro Limited.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _STM32F4X_CLOCK_H_
-#define _STM32F4X_CLOCK_H_
-
-/**
- * @brief Driver for Reset & Clock Control of STM32F4X family processor.
- *
- * Based on reference manual:
- * RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
- * advanced ARM ® -based 32-bit MCUs
- *
- * Chapter 6. Reset and Clock control (RCC) for STM43F401xB/C and STM32F401xD/E
- */
-
-/* 6.3.1 Clock control register (RCC_CR) */
-enum {
- STM32F4X_RCC_CFG_PLL_SRC_HSI = 0x0,
- STM32F4X_RCC_CFG_PLL_SRC_HSE = 0x1,
-};
-
-enum {
- STM32F4X_RCC_CFG_SYSCLK_SRC_HSI = 0x0,
- STM32F4X_RCC_CFG_SYSCLK_SRC_HSE = 0x1,
- STM32F4X_RCC_CFG_SYSCLK_SRC_PLL = 0x2,
-};
-
-enum {
- STM32F4X_RCC_CFG_PLLP_DIV_2 = 0x0,
- STM32F4X_RCC_CFG_PLLP_DIV_4 = 0x1,
- STM32F4X_RCC_CFG_PLLP_DIV_6 = 0x2,
- STM32F4X_RCC_CFG_PLLP_DIV_8 = 0x3,
-};
-
-enum {
- STM32F4X_RCC_CFG_HCLK_DIV_0 = 0x0,
- STM32F4X_RCC_CFG_HCLK_DIV_2 = 0x4,
- STM32F4X_RCC_CFG_HCLK_DIV_4 = 0x5,
- STM32F4X_RCC_CFG_HCLK_DIV_8 = 0x6,
- STM32F4X_RCC_CFG_HCLK_DIV_16 = 0x7,
-};
-
-enum {
- STM32F4X_RCC_CFG_SYSCLK_DIV_0 = 0x0,
- STM32F4X_RCC_CFG_SYSCLK_DIV_2 = 0x8,
- STM32F4X_RCC_CFG_SYSCLK_DIV_4 = 0x9,
- STM32F4X_RCC_CFG_SYSCLK_DIV_8 = 0xa,
- STM32F4X_RCC_CFG_SYSCLK_DIV_16 = 0xb,
- STM32F4X_RCC_CFG_SYSCLK_DIV_64 = 0xc,
- STM32F4X_RCC_CFG_SYSCLK_DIV_128 = 0xd,
- STM32F4X_RCC_CFG_SYSCLK_DIV_256 = 0xe,
- STM32F4X_RCC_CFG_SYSCLK_DIV_512 = 0xf,
-};
-
-/**
- * @brief Reset and Clock Control
- */
-
-/* Helpers */
-enum {
- STM32F4X_RCC_APB1ENR_PWREN = 0x10000000U,
-};
-
-union __rcc_cr {
- u32_t val;
- struct {
- u32_t hsion :1 __packed;
- u32_t hsirdy :1 __packed;
- u32_t rsvd__2 :1 __packed;
- u32_t hsitrim :5 __packed;
- u32_t hsical :8 __packed;
- u32_t hseon :1 __packed;
- u32_t hserdy :1 __packed;
- u32_t hsebyp :1 __packed;
- u32_t csson :1 __packed;
- u32_t rsvd__20_23 :4 __packed;
- u32_t pllon :1 __packed;
- u32_t pllrdy :1 __packed;
- u32_t plli2son :1 __packed;
- u32_t plli2srdy :1 __packed;
- u32_t pllsaion :1 __packed;
- u32_t pllsairdy :1 __packed;
- u32_t rsvd__30_31 :2 __packed;
- } bit;
-};
-
-union __rcc_pllcfgr {
- u32_t val;
- struct {
- u32_t pllm :6 __packed;
- u32_t plln :9 __packed;
- u32_t rsvd__15 :1 __packed;
- u32_t pllp :2 __packed;
- u32_t rsvd__18_21 :4 __packed;
- u32_t pllsrc :1 __packed;
- u32_t rsvd__23 :1 __packed;
- u32_t pllq :4 __packed;
- u32_t rsvd__28_31 :4 __packed;
- } bit;
-};
-
-union __rcc_cfgr {
- u32_t val;
- struct {
- u32_t sw :2 __packed;
- u32_t sws :2 __packed;
- u32_t hpre :4 __packed;
- u32_t rsvd__8_9 :2 __packed;
- u32_t ppre1 :3 __packed;
- u32_t ppre2 :3 __packed;
- u32_t rtcpre :5 __packed;
- u32_t mco1 :2 __packed;
- u32_t i2sscr :1 __packed;
- u32_t mco1pre :3 __packed;
- u32_t mco2pre :3 __packed;
- u32_t mco2 :2 __packed;
- } bit;
-};
-
-struct stm32f4x_rcc {
- union __rcc_cr cr;
- union __rcc_pllcfgr pllcfgr;
- union __rcc_cfgr cfgr;
- u32_t cir;
- u32_t ahb1rstr;
- u32_t ahb2rstr;
- u32_t ahb3rstr;
- u32_t rsvd0;
- u32_t apb1rstr;
- u32_t apb2rstr;
- u32_t rsvd1[2];
- u32_t ahb1enr;
- u32_t ahb2enr;
- u32_t ahb3enr;
- u32_t rsvd2;
- u32_t apb1enr;
- u32_t apb2enr;
- u32_t rsvd3[2];
- u32_t ahb1lpenr;
- u32_t ahb2lpenr;
- u32_t ahb3lpenr;
- u32_t rsvd4;
- u32_t apb1lpenr;
- u32_t apb2lpenr;
- u32_t rsvd5[2];
- u32_t bdcr;
- u32_t csr;
- u32_t rsvd6[2];
- u32_t sscgr;
- u32_t plli2scfgr;
- u32_t rsvd7;
- u32_t dckcfgr;
-};
-
-#endif /* _STM32F4X_CLOCK_H_ */
diff --git a/arch/arm/soc/st_stm32/stm32f4/soc.c b/arch/arm/soc/st_stm32/stm32f4/soc.c
index f1e4d693a..e2e27cee9 100644
--- a/arch/arm/soc/st_stm32/stm32f4/soc.c
+++ b/arch/arm/soc/st_stm32/stm32f4/soc.c
@@ -53,8 +53,14 @@ static int st_stm32f4_init(struct device *arg)
irq_unlock(key);
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+ /* Update CMSIS SystemCoreClock variable (HCLK) */
+ /* At reset, System core clock is set to 4MHz */
+ SystemCoreClock = 4000000;
+#else
/* Update CMSIS SystemCoreClock variable (HCLK) */
SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
return 0;
}
diff --git a/arch/arm/soc/st_stm32/stm32f4/soc.h b/arch/arm/soc/st_stm32/stm32f4/soc.h
index 372d2afcf..d611d1b07 100644
--- a/arch/arm/soc/st_stm32/stm32f4/soc.h
+++ b/arch/arm/soc/st_stm32/stm32f4/soc.h
@@ -52,6 +52,13 @@ enum stm32f4x_pin_config_mode {
#include "soc_irq.h"
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32f4xx_ll_utils.h>
+#include <stm32f4xx_ll_bus.h>
+#include <stm32f4xx_ll_rcc.h>
+#include <stm32f4xx_ll_system.h>
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
+
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F4_SOC_H_ */
diff --git a/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c b/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c
index 388be1512..8a0bd865b 100644
--- a/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c
+++ b/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c
@@ -234,9 +234,9 @@ int stm32_gpio_enable_int(int port, int pin)
(struct stm32f4x_syscfg *)SYSCFG_BASE;
volatile union syscfg_exticr *exticr;
struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
- struct stm32f4x_pclken pclken = {
- .bus = STM32F4X_CLOCK_BUS_APB2,
- .enr = STM32F4X_CLOCK_ENABLE_SYSCFG
+ struct stm32_pclken pclken = {
+ .bus = STM32_CLOCK_BUS_APB2,
+ .enr = LL_APB2_GRP1_PERIPH_SYSCFG
};
int shift = 0;
diff --git a/arch/arm/soc/st_stm32/stm32f4/soc_registers.h b/arch/arm/soc/st_stm32/stm32f4/soc_registers.h
index 1ad979890..c7a2d5cb7 100644
--- a/arch/arm/soc/st_stm32/stm32f4/soc_registers.h
+++ b/arch/arm/soc/st_stm32/stm32f4/soc_registers.h
@@ -8,7 +8,6 @@
#define _STM32F4_SOC_REGISTERS_H_
/* include register mapping headers */
-#include "rcc_registers.h"
#include "flash_registers.h"
#include "gpio_registers.h"
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 00:21:08 +0000