diff options
Diffstat (limited to 'boards/arm')
41 files changed, 1463 insertions, 33 deletions
diff --git a/boards/arm/96b_carbon/96b_carbon_defconfig b/boards/arm/96b_carbon/96b_carbon_defconfig index ae11c05c2..28afa4498 100644 --- a/boards/arm/96b_carbon/96b_carbon_defconfig +++ b/boards/arm/96b_carbon/96b_carbon_defconfig @@ -23,18 +23,21 @@ CONFIG_GPIO_STM32_PORTD=y # clock configuration CONFIG_CLOCK_CONTROL=y -CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL=y + +# Clock configuration for Cube Clock control driver +CONFIG_CLOCK_STM32_HSE_CLOCK=16000000 +CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y # use HSE as PLL input -CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE=y -# CONFIG_CLOCK_STM32F4X_HSE_BYPASS=y +CONFIG_CLOCK_STM32_PLL_SRC_HSE=y +# CONFIG_CLOCK_STM32_HSE_BYPASS=y # produce 84MHz clock at PLL output -CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR=16 -CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER=336 -CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR=4 -CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR=7 -CONFIG_CLOCK_STM32F4X_AHB_PRESCALER=0 -CONFIG_CLOCK_STM32F4X_APB1_PRESCALER=2 -CONFIG_CLOCK_STM32F4X_APB2_PRESCALER=0 +CONFIG_CLOCK_STM32_PLL_M_DIVISOR=16 +CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336 +CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4 +CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7 +CONFIG_CLOCK_STM32_AHB_PRESCALER=1 +CONFIG_CLOCK_STM32_APB1_PRESCALER=2 +CONFIG_CLOCK_STM32_APB2_PRESCALER=1 #enable DTS CONFIG_HAS_DTS=y diff --git a/boards/arm/96b_nitrogen/96b_nitrogen_defconfig b/boards/arm/96b_nitrogen/96b_nitrogen_defconfig index 11612ee65..b0f571dff 100644 --- a/boards/arm/96b_nitrogen/96b_nitrogen_defconfig +++ b/boards/arm/96b_nitrogen/96b_nitrogen_defconfig @@ -17,3 +17,6 @@ CONFIG_GPIO_AS_PINRESET=y # bluetooth CONFIG_BLUETOOTH=y CONFIG_BLUETOOTH_CONTROLLER=y + +#enable DTS +CONFIG_HAS_DTS=y diff --git a/boards/arm/arduino_101_ble/arduino_101_ble_defconfig b/boards/arm/arduino_101_ble/arduino_101_ble_defconfig index 95291a95c..8d7cbcc21 100644 --- a/boards/arm/arduino_101_ble/arduino_101_ble_defconfig +++ b/boards/arm/arduino_101_ble/arduino_101_ble_defconfig @@ -11,3 +11,6 @@ CONFIG_UART_NRF5=y # bluetooth CONFIG_BLUETOOTH=y CONFIG_BLUETOOTH_CONTROLLER=y + +#enable DTS +CONFIG_HAS_DTS=y diff --git a/boards/arm/bbc_microbit/bbc_microbit_defconfig b/boards/arm/bbc_microbit/bbc_microbit_defconfig index da7eef89a..58a942280 100644 --- a/boards/arm/bbc_microbit/bbc_microbit_defconfig +++ b/boards/arm/bbc_microbit/bbc_microbit_defconfig @@ -19,3 +19,6 @@ CONFIG_UART_CONSOLE=y # bluetooth CONFIG_BLUETOOTH=y CONFIG_BLUETOOTH_CONTROLLER=y + +#enable DTS +CONFIG_HAS_DTS=y diff --git a/boards/arm/cc3200_launchxl/Kconfig.defconfig b/boards/arm/cc3200_launchxl/Kconfig.defconfig index 065e30277..3c069b750 100644 --- a/boards/arm/cc3200_launchxl/Kconfig.defconfig +++ b/boards/arm/cc3200_launchxl/Kconfig.defconfig @@ -6,4 +6,7 @@ if BOARD_CC3200_LAUNCHXL config BOARD default cc3200_launchxl +config BOARD_DEPRECATED + default "1.8" + endif # BOARD_CC3200_LAUNCHXL diff --git a/boards/arm/cc3220sf_launchxl/Kconfig.board b/boards/arm/cc3220sf_launchxl/Kconfig.board new file mode 100644 index 000000000..6ebecc778 --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/Kconfig.board @@ -0,0 +1,6 @@ +# Kconfig - TI SimpleLink CC3220SF LaunchXL Board +# + +config BOARD_CC3220SF_LAUNCHXL + bool "TI CC3220SF LAUNCHXL" + depends on SOC_CC3220SF diff --git a/boards/arm/cc3220sf_launchxl/Kconfig.defconfig b/boards/arm/cc3220sf_launchxl/Kconfig.defconfig new file mode 100644 index 000000000..e8705b1ca --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Kconfig - TI CC3220SF LaunchXL board configuration +# + +if BOARD_CC3220SF_LAUNCHXL + +config BOARD + default cc3220sf_launchxl + +endif # BOARD_CC3220SF_LAUNCHXL diff --git a/boards/arm/cc3220sf_launchxl/Makefile b/boards/arm/cc3220sf_launchxl/Makefile new file mode 100644 index 000000000..1bfb9d7d0 --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/Makefile @@ -0,0 +1,4 @@ +ccflags-y += -I$(srctree)/include/drivers +ccflags-y += -I$(srctree)/drivers +obj-y += pinmux.o +obj-$(CONFIG_CC3220SF_DEBUG) += dbghdr.o diff --git a/boards/arm/cc3220sf_launchxl/board.h b/boards/arm/cc3220sf_launchxl/board.h new file mode 100644 index 000000000..fab3006b3 --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/board.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __INC_BOARD_H +#define __INC_BOARD_H + +/* Push button switch 2 */ +#define SW2_GPIO_PIN 6 /* GPIO22/Pin15 */ +#define SW2_GPIO_NAME "GPIO_A2" + +/* Push button switch 3 */ +#define SW3_GPIO_PIN 5 /* GPIO13/Pin4 */ +#define SW3_GPIO_NAME "GPIO_A1" + +/* Push button switch 0: Map to SW2 so zephyr button example works */ +#define SW0_GPIO_PIN SW2_GPIO_PIN +#define SW0_GPIO_NAME SW2_GPIO_NAME + +/* Onboard GREEN LED */ +#define LED0_GPIO_PIN 3 /*GPIO11/Pin2 */ +#define LED0_GPIO_PORT "GPIO_A1" + +#endif /* __INC_BOARD_H */ diff --git a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig b/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig new file mode 100644 index 000000000..f9a705b6a --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_BOARD_CC3220SF_LAUNCHXL=y +CONFIG_SOC_FAMILY_TISIMPLELINK=y +CONFIG_SOC_SERIES_CC32XX=y +CONFIG_SOC_CC3220SF=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_FLASH=y +CONFIG_XIP=n + +CONFIG_PRINTK=y + +#enable GPIO driver +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y +CONFIG_SERIAL_HAS_DRIVER=y +CONFIG_UART_CC32XX=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable CC3220 SDK +CONFIG_HAS_CC3220SDK=y + +# Enable DTS parsing +CONFIG_HAS_DTS=y diff --git a/boards/arm/cc3220sf_launchxl/dbghdr.c b/boards/arm/cc3220sf_launchxl/dbghdr.c new file mode 100644 index 000000000..cb8972733 --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/dbghdr.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This debug header, located at the start of flash, indicates + * to the bootloader that this is a debug image, allowing + * debuggers and flash-loaders to access the chip over JTAG. + * Also, on subsequent reboots, the bootloader skips the integrity + * check, preventing the image from being mass erased. + * + * See section 21.10: "Debugging Flash User Application Using JTAG" + * in the CC3220 TRM: http://www.ti.com/lit/ug/swru465/swru465.pdf + */ +#ifdef CONFIG_CC3220SF_DEBUG +__attribute__ ((section(".dbghdr"))) +const unsigned long ulDebugHeader[] = { + 0x5AA5A55A, + 0x000FF800, + 0xEFA3247D +}; +#endif diff --git a/boards/arm/cc3220sf_launchxl/doc/cc3220sf_launchxl.rst b/boards/arm/cc3220sf_launchxl/doc/cc3220sf_launchxl.rst new file mode 100644 index 000000000..a62c4d549 --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/doc/cc3220sf_launchxl.rst @@ -0,0 +1,222 @@ +.. _cc3220sf_launchxl: + +CC3220SF LaunchXL +################# + +Overview +******** +The SimpleLink Wi-Fi CC3220SF LaunchPad development kit (CC3220SF-LAUNCHXL) +highlights CC3220SF, a single-chip wireless microcontroller (MCU) with +1MB Flash, 256KB of RAM and enhanced security features. + +See the `TI CC3220 Product Page`_ for details. + +Features: +========= + +* Two separate execution environments: a user application dedicated ARM + Cortex-M4 MCU and a network processor MCU to run all Wi-Fi and + internet logical layers +* 40-pin LaunchPad standard leveraging the BoosterPack ecosystem +* On-board accelerometer and temperature sensor +* Two buttons and three LEDs for user interaction +* UART through USB to PC +* BoosterPack plug-in module for adding graphical displays, audio + codecs, antenna selection, environmental sensing, and more +* Power from USB for the LaunchPad and optional external BoosterPack +* XDS110-based JTAG emulation with serial port for flash programming + +Details on the CC3220SF LaunchXL development board can be found in the +`CC3220SF LaunchXL User's Guide`_. + +Hardware +******** + +The CC3220SF SoC has two MCUs: + +#. Applications MCU - an ARM® Cortex®-M4 Core at 80 MHz, with 256Kb RAM, + and access to external serial 1Mb flash with bootloader and peripheral + drivers in ROM. + +#. Network Coprocessor (NWP) - a dedicated ARM MCU, which completely + offloads Wi-Fi and internet protocols from the application MCU. + +Complete details of the CC3220SF SoC can be found in the `CC3220 TRM`_. + +Supported Features +================== + +Zephyr has been ported to the Applications MCU, with basic peripheral +driver support. + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| UART | on-chip | serial port-interrupt | ++-----------+------------+-----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------+ + +The accelerometer, temperature sensors, or other peripherals +accessible through the BoosterPack, are not currently supported. + +Connections and IOs +==================== + +Peripherals on the CC3220SF LaunchXL are mapped to the following pins in +the file :file:`boards/arm/cc3220sf_launchxl/pinmux.c`. + ++------------+-------+-------+ +| Function | PIN | GPIO | ++============+=======+=======+ +| UART0_TX | 55 | N/A | ++------------+-------+-------+ +| UART0_RX | 57 | N/A | ++------------+-------+-------+ +| LED D7 (R) | 64 | 9 | ++------------+-------+-------+ +| LED D6 (O) | 01 | 10 | ++------------+-------+-------+ +| LED D5 (G) | 02 | 11 | ++------------+-------+-------+ +| Switch SW2 | 15 | 22 | ++------------+-------+-------+ +| Switch SW3 | 04 | 13 | ++------------+-------+-------+ + +The default configuration can be found in the Kconfig file at +:file:`boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig`. + + +Programming and Debugging +************************* + +TI officially supports development on the CC3220SF using the TI +`CC3220 SDK`_ on Windows and Linux using TI tools: Code Composer +Studio for debugging and `UniFlash`_ for flashing. + +For Windows developers, see the `CC3220 Getting Started Guide`_ for +instructions on installation of tools, and how to flash the board using +UniFlash. + +The following instructions are geared towards Linux developers who +prefer command line tools to an IDE. + +Flashing +======== + +The TI UniFlash tool can be used to download a program into flash, which +will persist over subsequent reboots. + +Prerequisites: +-------------- + +#. Python 2.7 (the DSLite tool does not work with Python v 3.x). +#. Download and install `UniFlash`_ version 4.1 for Linux. +#. Jumper SOP[2..0] (J15) to 010, and connect the USB cable to the PC. + + This should result in a new device "Texas Instruments XDS110 Embed + with CMSIS-DAP" appearing at /dev/ttyACM1 and /dev/ttyACM0. + +#. Update the service pack, and place board in "Development Mode". + + Follow the instructions in Section 3.4 "Download the Application", + in the `CC3220 Getting Started Guide`_, except for steps 5 and 6 which + select an MCU image. + +#. Ensure the XDS-110 emulation firmware is updated. + + Download and install the latest `XDS-110 emulation package`_. + Follow the directions here to update the firmware: + http://processors.wiki.ti.com/index.php/XDS110#Updating_the_XDS110_Firmware + +#. Ensure CONFIG_XIP=y is set. + + The default board configuration file can be found at + :file:`boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig`. + + This locates the program into flash, and sets CONFIG_CC3220SF_DEBUG=y, + which prepends a debug header enabling the flash to persist over + subsequent reboots, bypassing the bootloader flash signature + verification. + + See Section of the 21.10 of the `CC3220 TRM`_ for details on the + secure flash boot process. + +Flashing Command: +----------------- + +Once the above prerequisites are met, use the UniFlash command line tool +to flash the Zephyr image: + +.. code-block:: console + + % dslite.sh -c $ZEPHYR_BASE/boards/arm/cc3220sf_launchxl/support/CC3220SF.ccxml \ + -e -f zephyr.elf + +The CC3220SF.ccxml is a configuration file written by TI's Code Composer +Studio IDE, and required for the dslite.sh tool. + +To see program output from UART0, one can execute in a separate terminal +window: + +.. code-block:: console + + % screen /dev/ttyACM0 115200 8N1 + +Debugging +========= + +It is possible to enable loading and debugging of an application via +OpenOCD and gdb, by linking and locating the program completely in SRAM. + +Prerequisites: +-------------- + +Follow the same prerequisites as in Flashing above, in addition: + +#. Ensure OpenOCD v0.9+ is configured/built with CMSIS-DAP support. +#. Power off the board, jumper SOP[2..0] (J15) to 001, and reconnect + the USB cable to the PC. +#. Set CONFIG_XIP=n and build the Zephyr elf file. + +The necessary OpenOCD CFG and sample gdbinit scripts can be found in +:file:`boards/arm/cc3220sf_launchxl/support/`. + +Debugging Command +----------------- + +.. code-block:: console + + % arm-none-eabi-gdb -x $ZEPHYR_BASE/boards/arm/cc3220sf_launchxl/support/gdbinit_xds110 \ + zephyr.elf + +References +********** + +CC32xx Wiki: + http://processors.wiki.ti.com/index.php/CC31xx_%26_CC32xx + +.. _TI CC3220 Product Page: + http://www.ti.com/product/cc3220 + +.. _CC3220 TRM: + http://www.ti.com/lit/ug/swru465/swru465.pdf + +.. _CC3220 Programmer's Guide: + http://www.ti.com/lit/ug/swru464/swru464.pdf + +.. _CC3220 Getting Started Guide: + http://www.ti.com/lit/ug/swru461/swru461.pdf + +.. _UniFlash: + http://processors.wiki.ti.com/index.php/Category:CCS_UniFlash + +.. _CC3220 SDK: + http://www.ti.com/tool/download/SIMPLELINK-CC3220-SDK + +.. _CC3220SF LaunchXL User's Guide: + http://www.ti.com/lit/ug/swru463/swru463.pdf + +.. _XDS-110 emulation package: + http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS110_Reset_Download diff --git a/boards/arm/cc3220sf_launchxl/pinmux.c b/boards/arm/cc3220sf_launchxl/pinmux.c new file mode 100644 index 000000000..f24602841 --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/pinmux.c @@ -0,0 +1,121 @@ +/* + * pinmux.c + * + * configure the device pins for different peripheral signals + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file was automatically generated on 7/21/2014 at 3:06:20 PM + * by TI PinMux version 3.0.334 + * (Then modified to meet Zephyr coding style) + */ + +/* + * TI Recommends use of the PinMux utility to ensure consistent configuration + * of pins: http://processors.wiki.ti.com/index.php/TI_PinMux_Tool + * + * Zephyr GPIO API however allows runtime configuration by applications. + * + * For the TI CC32XX port we leverage this output file + * from the PinMux tool, and guard sections based on Kconfig variables. + * + * The individual (uart/gpio) driver init/configuration functions + * therefore assume pinmux initialization is done here rather in the drivers + * at runtime. + */ + +#include <init.h> + +#include "pinmux.h" + +#include <inc/hw_types.h> +#include <inc/hw_memmap.h> +#include <inc/hw_gpio.h> +#include <driverlib/pin.h> +#include <driverlib/rom.h> +#include <driverlib/rom_map.h> +#include <driverlib/gpio.h> +#include <driverlib/prcm.h> + +int pinmux_initialize(struct device *port) +{ + ARG_UNUSED(port); + +#ifdef CONFIG_UART_CC32XX + /* Configure PIN_55 for UART0 UART0_TX */ + MAP_PinTypeUART(PIN_55, PIN_MODE_3); + + /* Configure PIN_57 for UART0 UART0_RX */ + MAP_PinTypeUART(PIN_57, PIN_MODE_3); +#endif + +#ifdef CONFIG_GPIO_CC32XX_A1 + /* Enable Peripheral Clocks */ + MAP_PRCMPeripheralClkEnable(PRCM_GPIOA1, PRCM_RUN_MODE_CLK); + + /* The following enables the 3 LEDs for the blinking samples */ + + /* Configure PIN_64 for GPIOOutput */ + MAP_PinTypeGPIO(PIN_64, PIN_MODE_0, false); + MAP_GPIODirModeSet(GPIOA1_BASE, 0x2, GPIO_DIR_MODE_OUT); + + /* Configure PIN_01 for GPIOOutput */ + MAP_PinTypeGPIO(PIN_01, PIN_MODE_0, false); + MAP_GPIODirModeSet(GPIOA1_BASE, 0x4, GPIO_DIR_MODE_OUT); + + /* Configure PIN_02 for GPIOOutput */ + MAP_PinTypeGPIO(PIN_02, PIN_MODE_0, false); + MAP_GPIODirModeSet(GPIOA1_BASE, 0x8, GPIO_DIR_MODE_OUT); + + /* SW3: Configure PIN_04 (GPIO13) for GPIOInput */ + MAP_PinTypeGPIO(PIN_04, PIN_MODE_0, false); + MAP_GPIODirModeSet(GPIOA1_BASE, 0x20, GPIO_DIR_MODE_IN); +#endif + +#ifdef CONFIG_GPIO_CC32XX_A2 + MAP_PRCMPeripheralClkEnable(PRCM_GPIOA2, PRCM_RUN_MODE_CLK); + + /* SW2: Configure PIN_15 (GPIO22) for GPIOInput */ + MAP_PinTypeGPIO(PIN_15, PIN_MODE_0, false); + MAP_GPIODirModeSet(GPIOA2_BASE, 0x40, GPIO_DIR_MODE_IN); +#endif + +#ifdef CONFIG_GPIO_CC32XX_A3 + MAP_PRCMPeripheralClkEnable(PRCM_GPIOA3, PRCM_RUN_MODE_CLK); +#endif + + return 0; +} + +SYS_INIT(pinmux_initialize, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/boards/arm/cc3220sf_launchxl/support/CC3220SF.ccxml b/boards/arm/cc3220sf_launchxl/support/CC3220SF.ccxml new file mode 100644 index 000000000..def6e22c8 --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/support/CC3220SF.ccxml @@ -0,0 +1,14 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<configurations XML_version="1.2" id="configurations_0"> + <configuration XML_version="1.2" id="configuration_0"> + <instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/> + <connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe"> + <instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/> + <instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/> + <instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/> + <platform XML_version="1.2" id="platform_0"> + <instance XML_version="1.2" desc="CC3220SF" href="devices/CC3220SF.xml" id="CC3220SF" xml="CC3220SF.xml" xmlpath="devices"/> + </platform> + </connection> + </configuration> +</configurations> diff --git a/boards/arm/cc3220sf_launchxl/support/cc3220_xds110.cfg b/boards/arm/cc3220sf_launchxl/support/cc3220_xds110.cfg new file mode 100644 index 000000000..4d2532b23 --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/support/cc3220_xds110.cfg @@ -0,0 +1,45 @@ +#***************************************************************************** +# +# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: Apache-2.0 +# +#***************************************************************************** + +# +# CC3220 via CMSIS-DAP interface on XDS110 debug probe +# +# CMSIS-DAP support in OpenOCD can only use SWD mode. So +# jumper SOP0 only, and reset the target before connect. +# + +interface cmsis-dap +cmsis_dap_vid_pid 0x0451 0xbef3 +adapter_khz 2500 + +set _ENDIAN little + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cc3220 +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x0b97c02f +} + +swd newdap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_CHIPNAME.cpu cortex_m -endian little -chain-position $_CHIPNAME.dap +$_CHIPNAME.cpu configure -work-area-phys 0x20000000 -work-area-size 0x30000 -work-area-backup 0 -coreid 0 + +source [find mem_helper.tcl] + +$_TARGETNAME configure -event gdb-attach { + halt +} diff --git a/boards/arm/cc3220sf_launchxl/support/gdbinit_xds110 b/boards/arm/cc3220sf_launchxl/support/gdbinit_xds110 new file mode 100644 index 000000000..51dae1c28 --- /dev/null +++ b/boards/arm/cc3220sf_launchxl/support/gdbinit_xds110 @@ -0,0 +1,16 @@ +#***************************************************************************** +# +# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: Apache-2.0 +# +#***************************************************************************** + +# Modify to point to your own Zephyr base: +target remote | openocd -c "gdb_port pipe; log_output openocd.log" -f ~/zephyr/boards/arm/cc3220sf_launchxl/support/cc3220_xds110.cfg + +monitor soft_reset_halt +load + +break _Cstart +set remotetimeout 10000 diff --git a/boards/arm/curie_ble/curie_ble_defconfig b/boards/arm/curie_ble/curie_ble_defconfig index 2ebcb393c..0183def5a 100644 --- a/boards/arm/curie_ble/curie_ble_defconfig +++ b/boards/arm/curie_ble/curie_ble_defconfig @@ -11,3 +11,6 @@ CONFIG_UART_NRF5=y # bluetooth CONFIG_BLUETOOTH=y CONFIG_BLUETOOTH_CONTROLLER=y + +#enable DTS +CONFIG_HAS_DTS=y diff --git a/boards/arm/disco_l475_iot1/Kconfig.board b/boards/arm/disco_l475_iot1/Kconfig.board new file mode 100644 index 000000000..0d9f243e0 --- /dev/null +++ b/boards/arm/disco_l475_iot1/Kconfig.board @@ -0,0 +1,10 @@ +# Kconfig - Discovery IoT L475 board configuration +# +# Copyright (c) 2017 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_DISCO_L475_IOT1 + bool "Discovery IoT L475 Development Board" + depends on SOC_STM32L475XG diff --git a/boards/arm/disco_l475_iot1/Kconfig.defconfig b/boards/arm/disco_l475_iot1/Kconfig.defconfig new file mode 100644 index 000000000..76fb57a8b --- /dev/null +++ b/boards/arm/disco_l475_iot1/Kconfig.defconfig @@ -0,0 +1,90 @@ +# Kconfig - Discovery IoT L475 board configuration +# +# Copyright (c) 2017 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_DISCO_L475_IOT1 + +config BOARD + default disco_l475_iot1 + +if GPIO + +config GPIO_STM32_PORTA + def_bool y + +config GPIO_STM32_PORTB + def_bool y + +config GPIO_STM32_PORTC + def_bool y + +config GPIO_STM32_PORTD + def_bool n + +config GPIO_STM32_PORTE + def_bool n + +config GPIO_STM32_PORTF + def_bool n + +config GPIO_STM32_PORTG + def_bool n + +config GPIO_STM32_PORTH + def_bool n + +endif # GPIO + + +if SERIAL + +config UART_STM32_PORT_1 + def_bool y + +endif # SERIAL + + +if I2C + +config I2C_1 + def_bool n + +config I2C_2 + def_bool y + +if I2C_1 + +config I2C_1_DEFAULT_CFG + default 0x14 + +config I2C_1_IRQ_PRI + default 0 + +endif # I2C_1 + +if I2C_2 + +config I2C_2_DEFAULT_CFG + default 0x14 + +config I2C_2_IRQ_PRI + default 0 + +endif # I2C_2 + +endif # I2C + + +if PWM + +config PWM_STM32_1 + def_bool n + +config PWM_STM32_2 + def_bool y + +endif # PWM +endif # BOARD_DISCO_L475_IOT1 diff --git a/boards/arm/disco_l475_iot1/Makefile b/boards/arm/disco_l475_iot1/Makefile new file mode 100644 index 000000000..c925263c4 --- /dev/null +++ b/boards/arm/disco_l475_iot1/Makefile @@ -0,0 +1,2 @@ +# No C files (yet) +obj- += dummy.o diff --git a/boards/arm/disco_l475_iot1/board.h b/boards/arm/disco_l475_iot1/board.h new file mode 100644 index 000000000..3c40a6c30 --- /dev/null +++ b/boards/arm/disco_l475_iot1/board.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2017 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INC_BOARD_H +#define __INC_BOARD_H + +#include <soc.h> + +/* USER push button */ +#define USER_PB_GPIO_PORT "GPIOC" +#define USER_PB_GPIO_PIN 13 + +/* LD1 green LED */ +#define LD1_GPIO_PORT "GPIOA" +#define LD1_GPIO_PIN 5 + +/* LD2 green LED */ +#define LD2_GPIO_PORT "GPIOB" +#define LD2_GPIO_PIN 14 + +/* LD3 & LD4 are mounted on PC_9 */ +/* PC_9 output: 1: LD2 off, LD3 on */ +/* PC_9 output: 0: LD2 on, LD3 off */ +/* PC_9 input: LD3 off, LD3 off */ +/* LD3 yelllow: Wifi activity */ +#define LD3_GPIO_PORT "GPIOC" +#define LD3_GPIO_PIN 9 +/* LD4 blue: BT activity */ +#define LD4_GPIO_PORT "GPIOC" +#define LD4_GPIO_PIN 9 + +/* Create aliases to make the basic samples work */ +#define SW0_GPIO_NAME USER_PB_GPIO_PORT +#define SW0_GPIO_PIN USER_PB_GPIO_PIN +#define LED0_GPIO_PORT LD2_GPIO_PORT +#define LED0_GPIO_PIN LD2_GPIO_PIN + +#endif /* __INC_BOARD_H */ diff --git a/boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig b/boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig new file mode 100644 index 000000000..63e0d7409 --- /dev/null +++ b/boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_BOARD_DISCO_L475_IOT1=y +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32L4X=y +CONFIG_SOC_STM32L475XG=y +CONFIG_CORTEX_M_SYSTICK=y +# 80MHz system clock +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000 + +#enable DTS +CONFIG_HAS_DTS=y + +# enable uart driver +CONFIG_SERIAL=y +CONFIG_UART_STM32=y + +# enable pinmux +CONFIG_PINMUX=y +CONFIG_PINMUX_STM32=y + +# enable GPIOs +CONFIG_GPIO=y +CONFIG_GPIO_STM32=y + +# clock configuration +CONFIG_CLOCK_CONTROL=y +CONFIG_CLOCK_CONTROL_STM32_CUBE=y +# SYSCLK selection +CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y +# PLL configuration +CONFIG_CLOCK_STM32_PLL_SRC_HSI=y +# produce 80MHz clock at PLL output +CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1 +CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=20 +CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7 +CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2 +CONFIG_CLOCK_STM32_PLL_R_DIVISOR=4 +CONFIG_CLOCK_STM32_AHB_PRESCALER=1 +CONFIG_CLOCK_STM32_APB1_PRESCALER=1 +CONFIG_CLOCK_STM32_APB2_PRESCALER=1 + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_1" + +#enable pwm +CONFIG_PWM=y +CONFIG_PWM_STM32=y + +#enable I2C +CONFIG_I2C=y +CONFIG_I2C_STM32LX=y + +#configure HTS221 sensor +CONFIG_HTS221_I2C_MASTER_DEV_NAME="I2C_2" +CONFIG_HTS221_TRIGGER_NONE=y +CONFIG_HTS221_I2C_ADDR=0x5F diff --git a/boards/arm/disco_l475_iot1/doc/disco_l475_iot1.rst b/boards/arm/disco_l475_iot1/doc/disco_l475_iot1.rst new file mode 100644 index 000000000..44e982a1b --- /dev/null +++ b/boards/arm/disco_l475_iot1/doc/disco_l475_iot1.rst @@ -0,0 +1,245 @@ +.. _disco_l475_iot1_board: + +ST Disco L475 IOT01 +################### + +Overview +******** + +The B-L475E-IOT01A Discovery kit for IoT node allows users to develop +applications with direct connection to cloud servers. +The Discovery kit enables a wide diversity of applications by exploiting +low-power communication, multiway sensing and ARM® Cortex® -M4 core-based +STM32L4 Series features. + +This kit provides: + +- 64-Mbit Quad-SPI (Macronix) Flash memory +- Bluetooth® V4.1 module (SPBTLE-RF) +- Sub-GHz (868 or 915 MHz) low-power-programmable RF module (SPSGRF-868 or SPSGRF-915) +- Wi-Fi® module Inventek ISM43362-M3G-L44 (802.11 b/g/n compliant) +- Dynamic NFC tag based on M24SR with its printed NFC antenna +- 2 digital omni-directional microphones (MP34DT01) +- Capacitive digital sensor for relative humidity and temperature (HTS221) +- High-performance 3-axis magnetometer (LIS3MDL) +- 3D accelerometer and 3D gyroscope (LSM6DSL) +- 260-1260 hPa absolute digital output barometer (LPS22HB) +- Time-of-Flight and gesture-detection sensor (VL53L0X) +- 2 push-buttons (user and reset) +- USB OTG FS with Micro-AB connector +- Expansion connectors: + - Arduino™ Uno V3 + - PMOD +- Flexible power-supply options: + - ST LINK USB VBUS or external sources +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: + - mass storage, virtual COM port and debug port + + +.. image:: img/disco_l475_iot1.jpg + :width: 531px + :align: center + :height: 354px + :alt: Disco L475 IoT1 + +More information about the board can be found at the `Disco L475 IoT1 website`_. + +Hardware +******** + +The STM32L475RG SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 μA/MHz run mode) +- Core: ARM® 32-bit Cortex®-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (±1%) + - Internal low-power 32 kHz RC (±5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 μA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators +- 18x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ + + +More information about STM32L476RG can be found here: + - `STM32L475RG on www.st.com`_ + - `STM32L475 reference manual`_ + +Supported Features +================== + +The Zephyr Disco L475 IoT board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: + + ``boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig`` + + +Connections and IOs +=================== + +Disco L475 IoT Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- + +For detailed information about available pins please refer to `STM32 Disco L475 IoT1 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- I2C_2_SCL : PB10 +- I2C_2_SDA : PB11 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- PWM_2_CH1 : PA15 +- USER_PB : PC13 +- LD2 : PA5 + +System Clock +------------ + +Disco L475 IoT System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Disco L475 IoT board has 6 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +Disco L475 IoT board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is not supported by the openocd version 0.9 included by the Zephyr SDK v0.9. +Until we update the Zephyr SDK, use openocd v0.10.0 from the openocd-stm32 project on GitHub +to get the minimum set of scripts needed to flash and debug STM32 development boards. + +.. code-block:: console + + $ git clone https://github.com/erwango/openocd-stm32.git + +Then follow instructions in README.md + + +Flashing an application to Disco L475 IoT +----------------------------------------- + +The sample application :ref:`hello_world` is being used in this tutorial: + +To build the Zephyr kernel and application, enter: + +.. code-block:: console + + $ cd <zephyr_root_path> + $ source zephyr-env.sh + $ cd $ZEPHYR_BASE/samples/hello_world/ + $ make BOARD=disco_l475_iot1 + +Connect the Disco L475 IoT to your host computer using the USB port. +Then, enter the following command: + +.. code-block:: console + + $ cd <openocd-stm32_path> + $ stm32_flsh l4 $ZEPHYR_BASE/samples/hello_world/outdir/disco_l475_iot1/zephyr.bin + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message: + +.. code-block:: console + + $ Hello World! arm + + +Debugging +========= + +Access gdb with the following make command: + +.. code-block:: console + + $ cd <openocd-stm32_path> + $ stm32_dbg l4 $ZEPHYR_BASE/samples/hello_world/outdir/disco_l475_iot1/zephyr.elf + +.. _Disco L475 IoT1 website: + http://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-discovery-kits/b-l475e-iot01a.html + +.. _STM32 Disco L475 IoT1 board User Manual: + http://www.st.com/resource/en/user_manual/dm00347848.pdf + +.. _STM32L475RG on www.st.com: + http://www.st.com/en/microcontrollers/stm32l475rg.html + +.. _STM32L475 reference manual: + http://www.st.com/resource/en/reference_manual/DM00031020.pdf diff --git a/boards/arm/disco_l475_iot1/doc/img/disco_l475_iot1.jpg b/boards/arm/disco_l475_iot1/doc/img/disco_l475_iot1.jpg Binary files differnew file mode 100644 index 000000000..20b7f6e05 --- /dev/null +++ b/boards/arm/disco_l475_iot1/doc/img/disco_l475_iot1.jpg diff --git a/boards/arm/frdm_kl25z/Kconfig.board b/boards/arm/frdm_kl25z/Kconfig.board new file mode 100644 index 000000000..954cf64c7 --- /dev/null +++ b/boards/arm/frdm_kl25z/Kconfig.board @@ -0,0 +1,11 @@ +# Kconfig - FRDM-KL25Z board +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_FRDM_KL25Z + bool "NXP FRDM-KL25Z" + depends on SOC_SERIES_KINETIS_KL2X + select SOC_PART_NUMBER_MKL25Z128VLK4 diff --git a/boards/arm/frdm_kl25z/Kconfig.defconfig b/boards/arm/frdm_kl25z/Kconfig.defconfig new file mode 100644 index 000000000..5f8e2a005 --- /dev/null +++ b/boards/arm/frdm_kl25z/Kconfig.defconfig @@ -0,0 +1,108 @@ +# Kconfig - FRDM-KL25Z board +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_FRDM_KL25Z + +config BOARD + default frdm_kl25z + +config OSC_XTAL0_FREQ + default 8000000 + +config MCG_PRDIV0 + default 0x01 + +config MCG_VDIV0 + default 0x00 + +config MCG_FRDIV + default 5 + +config MCG_FCRDIV + default 0 + +config PINMUX + def_bool y + +if PINMUX_MCUX + +config PINMUX_MCUX_PORTA + def_bool y + +config PINMUX_MCUX_PORTB + def_bool y + +config PINMUX_MCUX_PORTC + def_bool y if SPI_0 + +config PINMUX_MCUX_PORTD + def_bool y + +config PINMUX_MCUX_PORTE + def_bool y if I2C_0 + +endif # PINMUX_MCUX + +if GPIO_MCUX + +config GPIO_MCUX_PORTA + def_bool y + +config GPIO_MCUX_PORTB + def_bool y + +config GPIO_MCUX_PORTC + def_bool n + +config GPIO_MCUX_PORTD + def_bool y + +config GPIO_MCUX_PORTE + def_bool n + +endif # GPIO_MCUX + +if UART_MCUX_LPSCI + +config UART_MCUX_LPSCI_0 + def_bool y if UART_CONSOLE + +endif # UART_MCUX_LPSCI + +if I2C + +config I2C_0 + def_bool y + +if I2C_0 + +config I2C_0_DEFAULT_CFG + default 0x12 + +config I2C_0_IRQ_PRI + default 0 + +endif # I2C_0 + +endif # I2C + +if SPI + +config SPI_0 + def_bool y + +if SPI_0 + +config SPI_0_IRQ_PRI + default 0 + +endif # SPI_0 + +endif # SPI + + +endif # BOARD_FRDM_KL25Z diff --git a/boards/arm/frdm_kl25z/Makefile b/boards/arm/frdm_kl25z/Makefile new file mode 100644 index 000000000..1e47c1fca --- /dev/null +++ b/boards/arm/frdm_kl25z/Makefile @@ -0,0 +1,10 @@ +# Makefile - FRDM-KL25Z board +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +ccflags-y +=-I$(srctree)/drivers + +obj-$(CONFIG_PINMUX_MCUX) += pinmux.o diff --git a/boards/arm/frdm_kl25z/board.h b/boards/arm/frdm_kl25z/board.h new file mode 100644 index 000000000..cde0e67b7 --- /dev/null +++ b/boards/arm/frdm_kl25z/board.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INC_BOARD_H +#define __INC_BOARD_H + +#include <soc.h> + +/* Push button switch for test purposes */ +#define SW0_TEST_GPIO_NAME CONFIG_GPIO_MCUX_PORTA_NAME +#define SW0_TEST_GPIO_PIN 16 + +/* Push button switch for test purposes */ +#define SW1_TEST_GPIO_NAME CONFIG_GPIO_MCUX_PORTA_NAME +#define SW1_TEST_GPIO_PIN 17 + +/* Red LED */ +#define RED_GPIO_NAME CONFIG_GPIO_MCUX_PORTB_NAME +#define RED_GPIO_PIN 18 + +/* Green LED */ +#define GREEN_GPIO_NAME CONFIG_GPIO_MCUX_PORTB_NAME +#define GREEN_GPIO_PIN 19 + +/* Blue LED */ +#define BLUE_GPIO_NAME CONFIG_GPIO_MCUX_PORTD_NAME +#define BLUE_GPIO_PIN 1 + +/* LED0. There is no physical LED on the board with this name, so create an + * alias to the green LED to make the basic blinky sample work. + */ +#define LED0_GPIO_PORT GREEN_GPIO_NAME +#define LED0_GPIO_PIN GREEN_GPIO_PIN + +/* Push button switch 0. There is no physical switch on the board, + * so an push button must be added to such pins for basic button sample work. + */ +#define SW0_GPIO_NAME SW0_TEST_GPIO_NAME +#define SW0_GPIO_PIN SW0_TEST_GPIO_PIN + +#endif /* __INC_BOARD_H */ diff --git a/boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg b/boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg Binary files differnew file mode 100644 index 000000000..29b9e2125 --- /dev/null +++ b/boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg diff --git a/boards/arm/frdm_kl25z/doc/frdm_kl25z.rst b/boards/arm/frdm_kl25z/doc/frdm_kl25z.rst new file mode 100644 index 000000000..b5e1b837d --- /dev/null +++ b/boards/arm/frdm_kl25z/doc/frdm_kl25z.rst @@ -0,0 +1,173 @@ +.. _frdm_kl25z: + +NXP FRDM-KL25Z +############## + +Overview +******** + +The Freedom KL25Z is an ultra-low-cost development platform for +Kinetis |reg| L Series KL1x (KL14/15) and KL2x (KL24/25) MCUs built +on ARM |reg| Cortex |reg|-M0+ processor. + +The FRDM-KL25Z features include easy access to MCU I/O, battery-ready, +low-power operation, a standard-based form factor with expansion board +options and a built-in debug interface for flash programming and run-control. + + +.. image:: frdm_kl25z.jpg + :width: 272px + :align: center + :alt: FRDM-KL25Z + +Hardware +******** + +- MKL25Z128VLK4 MCU @ 48 MHz, 128 KB flash, 16 KB SRAM, USB OTG (FS), 80LQFP +- On board capacitive touch "slider", MMA8451Q accelerometer, and tri-color LED +- OpenSDA debug interface + +For more information about the KL25Z SoC and FRDM-KL25Z board: + +- `KL25Z Website`_ +- `KL25Z Datasheet`_ +- `KL25Z Reference Manual`_ +- `FRDM-KL25Z Website`_ +- `FRDM-KL25Z User Guide`_ +- `FRDM-KL25Z Schematics`_ + +Supported Features +================== + +The frdm_kl25z board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + ``boards/arm/frdm_kl25z/frdm_kl25z_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The KL25Z SoC has five pairs of pinmux/gpio controllers, and all are currently enabled +(PORTA/GPIOA, PORTB/GPIOB, PORTC/GPIOC, PORTD/GPIOD, and PORTE/GPIOE) for the FRDM-KL25Z board. + ++-------+-------------+---------------------------+ +| Name | Function | Usage | ++=======+=============+===========================+ +| PTB18 | GPIO | Red LED | ++-------+-------------+---------------------------+ +| PTB19 | GPIO | Green LED | ++-------+-------------+---------------------------+ +| PTD1 | GPIO | Blue LED | ++-------+-------------+---------------------------+ +| PTA1 | UART0_RX | UART Console | ++-------+-------------+---------------------------+ +| PTA2 | UART0_TX | UART Console | ++-------+-------------+---------------------------+ +| PTE24 | I2C0_SCL | I2C | ++-------+-------------+---------------------------+ +| PTE25 | I2C0_SDA | I2C | ++-------+-------------+---------------------------+ +| PTC4 | SPI0_PSC0 | SPI | ++-------+-------------+---------------------------+ +| PTC5 | SPI0_SCK | SPI | ++-------+-------------+---------------------------+ +| PTC6 | SPI0_MOSI | SPI | ++-------+-------------+---------------------------+ +| PTC7 | SPI0_MISO | SPI | ++-------+-------------+---------------------------+ + + +System Clock +============ + +The KL25Z SoC is configured to use the 8 MHz external oscillator on the board +with the on-chip FLL to generate a 48 MHz system clock. + +Serial Port +=========== + +The KL25Z UART0 is used for the console. + +Programming and Debugging +************************* + +Flashing +======== + +The FRDM-KL25Z includes an `OpenSDA`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes on-board Mass Storage and a + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection, which is relayed over interface USB Serial port. + +Flashing an application to FRDM-KL25Z +------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. code-block:: console + + $ cd $ZEPHYR_BASE + $ . zephyr-env.sh + $ cd $ZEPHYR_BASE/samples/hello_world/ + $ make BOARD=frdm_kl25z + +Connect the FRDM-KL25Z to your host computer using the USB port and you should +see a USB connection which exposes on-board Mass Storage (FRDM-KL25ZJ) and a USB Serial +Port. Copy the generated zephyr.bin to the FRDM-KL25ZJ drive. + +Run a serial console app on your host computer. Reset the board and you'll see the +following message written to the serial port: + +.. code-block:: console + + Hello World! arm + + +.. _FRDM-KL25Z Website: + http://www.nxp.com/products/software-and-tools/hardware-development-tools/freedom-development-boards/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z?tid=vanFRDM-KL25Z + +.. _FRDM-KL25Z User Guide: + http://www.nxp.com/assets/documents/data/en/user-guides/FRDMKL25ZUM.zip + +.. _FRDM-KL25Z Schematics: + http://www.nxp.com/assets/downloads/data/en/schematics/FRDM-KL25Z_SCH_REV_E.pdf + +.. _OpenSDA: + http://www.nxp.com/assets/documents/data/en/user-guides/OPENSDAUG.pdf + +.. _KL25Z Website: + http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/kinetis-cortex-m-mcus/l-series-ultra-low-power-m0-plus/kinetis-kl2x-48-mhz-usb-ultra-low-power-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KL2x?lang_cd=en + +.. _KL25Z Datasheet: + http://www.nxp.com/assets/documents/data/en/data-sheets/KL25P80M48SF0.pdf + +.. _KL25Z Reference Manual: + http://www.nxp.com/assets/documents/data/en/reference-manuals/KL25P80M48SF0RM.pdf diff --git a/boards/arm/frdm_kl25z/frdm_kl25z_defconfig b/boards/arm/frdm_kl25z/frdm_kl25z_defconfig new file mode 100644 index 000000000..b79f99b9c --- /dev/null +++ b/boards/arm/frdm_kl25z/frdm_kl25z_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_SOC_MKL25Z=y +CONFIG_SOC_SERIES_KINETIS_KL2X=y +CONFIG_BOARD_FRDM_KL25Z=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 +CONFIG_OSC_LOW_POWER=y +CONFIG_HAS_DTS=y diff --git a/boards/arm/frdm_kl25z/pinmux.c b/boards/arm/frdm_kl25z/pinmux.c new file mode 100644 index 000000000..ed535e67a --- /dev/null +++ b/boards/arm/frdm_kl25z/pinmux.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <init.h> +#include <pinmux.h> +#include <fsl_port.h> + +static int frdm_kl25z_pinmux_init(struct device *dev) +{ + ARG_UNUSED(dev); + +#ifdef CONFIG_PINMUX_MCUX_PORTA + struct device *porta = + device_get_binding(CONFIG_PINMUX_MCUX_PORTA_NAME); +#endif +#ifdef CONFIG_PINMUX_MCUX_PORTB + struct device *portb = + device_get_binding(CONFIG_PINMUX_MCUX_PORTB_NAME); +#endif +#if defined(CONFIG_PINMUX_MCUX_PORTC) + struct device *portc = + device_get_binding(CONFIG_PINMUX_MCUX_PORTC_NAME); +#endif +#ifdef CONFIG_PINMUX_MCUX_PORTD + struct device *portd = + device_get_binding(CONFIG_PINMUX_MCUX_PORTD_NAME); +#endif +#if defined(CONFIG_PINMUX_MCUX_PORTE) + struct device *porte = + device_get_binding(CONFIG_PINMUX_MCUX_PORTE_NAME); +#endif + +#ifdef CONFIG_UART_MCUX_LPSCI_0 + /* UART0 RX, TX */ + pinmux_pin_set(porta, 1, PORT_PCR_MUX(kPORT_MuxAlt2)); + pinmux_pin_set(porta, 2, PORT_PCR_MUX(kPORT_MuxAlt2)); +#endif + + /* SW0 and SW1 */ + pinmux_pin_set(porta, 16, PORT_PCR_MUX(kPORT_MuxAsGpio)); + pinmux_pin_set(porta, 17, PORT_PCR_MUX(kPORT_MuxAsGpio)); + + /* Red, green, blue LEDs. */ + pinmux_pin_set(portd, 1, PORT_PCR_MUX(kPORT_MuxAsGpio)); + pinmux_pin_set(portb, 18, PORT_PCR_MUX(kPORT_MuxAsGpio)); + pinmux_pin_set(portb, 19, PORT_PCR_MUX(kPORT_MuxAsGpio)); + +#if defined(CONFIG_SPI_0) + /* SPI0 CLK, MOSI, MISO */ + pinmux_pin_set(portc, 4, PORT_PCR_MUX(kPORT_MuxAlt2)); + pinmux_pin_set(portc, 5, PORT_PCR_MUX(kPORT_MuxAlt2)); + pinmux_pin_set(portc, 6, PORT_PCR_MUX(kPORT_MuxAlt2)); + pinmux_pin_set(portc, 7, PORT_PCR_MUX(kPORT_MuxAlt2)); +#endif + +#if defined(CONFIG_I2C_0) + /* I2C0 SCL, SDA */ + pinmux_pin_set(porte, 24, PORT_PCR_MUX(kPORT_MuxAlt5) + | PORT_PCR_PS_MASK); + pinmux_pin_set(porte, 25, PORT_PCR_MUX(kPORT_MuxAlt5) + | PORT_PCR_PS_MASK); +#endif + + return 0; +} + +SYS_INIT(frdm_kl25z_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/nrf51_blenano/nrf51_blenano_defconfig b/boards/arm/nrf51_blenano/nrf51_blenano_defconfig index c7af5b93b..185a42810 100644 --- a/boards/arm/nrf51_blenano/nrf51_blenano_defconfig +++ b/boards/arm/nrf51_blenano/nrf51_blenano_defconfig @@ -15,3 +15,6 @@ CONFIG_UART_CONSOLE=y # bluetooth CONFIG_BLUETOOTH=y CONFIG_BLUETOOTH_CONTROLLER=y + +#enable DTS +CONFIG_HAS_DTS=y diff --git a/boards/arm/nrf51_pca10028/nrf51_pca10028_defconfig b/boards/arm/nrf51_pca10028/nrf51_pca10028_defconfig index 147a800f2..120e8430b 100644 --- a/boards/arm/nrf51_pca10028/nrf51_pca10028_defconfig +++ b/boards/arm/nrf51_pca10028/nrf51_pca10028_defconfig @@ -15,3 +15,6 @@ CONFIG_UART_CONSOLE=y # bluetooth CONFIG_BLUETOOTH=y CONFIG_BLUETOOTH_CONTROLLER=y + +#enable DTS +CONFIG_HAS_DTS=y diff --git a/boards/arm/nrf52840_pca10056/nrf52840_pca10056_defconfig b/boards/arm/nrf52840_pca10056/nrf52840_pca10056_defconfig index 9ae816a6e..daabd297e 100644 --- a/boards/arm/nrf52840_pca10056/nrf52840_pca10056_defconfig +++ b/boards/arm/nrf52840_pca10056/nrf52840_pca10056_defconfig @@ -18,3 +18,6 @@ CONFIG_GPIO_AS_PINRESET=y # bluetooth CONFIG_BLUETOOTH=y CONFIG_BLUETOOTH_CONTROLLER=y + +#enable DTS +CONFIG_HAS_DTS=y diff --git a/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig b/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig index 71fe9bd1a..f4bb1cc67 100644 --- a/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig +++ b/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig @@ -15,3 +15,6 @@ CONFIG_UART_CONSOLE=y # bluetooth CONFIG_BLUETOOTH=y CONFIG_BLUETOOTH_CONTROLLER=y + +#enable DTS +CONFIG_HAS_DTS=y diff --git a/boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig b/boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig index c8519fe92..c3e26a0df 100644 --- a/boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig +++ b/boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig @@ -18,3 +18,6 @@ CONFIG_GPIO_AS_PINRESET=y # bluetooth CONFIG_BLUETOOTH=y CONFIG_BLUETOOTH_CONTROLLER=y + +#enable DTS +CONFIG_HAS_DTS=y diff --git a/boards/arm/nucleo_f401re/nucleo_f401re_defconfig b/boards/arm/nucleo_f401re/nucleo_f401re_defconfig index 76e8b981f..f01e7c2f0 100644 --- a/boards/arm/nucleo_f401re/nucleo_f401re_defconfig +++ b/boards/arm/nucleo_f401re/nucleo_f401re_defconfig @@ -22,20 +22,24 @@ CONFIG_GPIO=y # clock configuration CONFIG_CLOCK_CONTROL=y -CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL=y + +# Clock configuration for Cube Clock control driver +CONFIG_CLOCK_STM32_HSE_CLOCK=8000000 +CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y # use HSE as PLL input -CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE=y +CONFIG_CLOCK_STM32_PLL_SRC_HSE=y # however, the board does not have an external oscillator, so just use # the 8MHz clock signal coming from integrated STLink -CONFIG_CLOCK_STM32F4X_HSE_BYPASS=y +CONFIG_CLOCK_STM32_HSE_BYPASS=y # produce 84MHz clock at PLL output -CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR=8 -CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER=336 -CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR=4 -CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR=7 -CONFIG_CLOCK_STM32F4X_AHB_PRESCALER=0 -CONFIG_CLOCK_STM32F4X_APB1_PRESCALER=2 -CONFIG_CLOCK_STM32F4X_APB2_PRESCALER=0 +CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8 +CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336 +CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4 +CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7 +CONFIG_CLOCK_STM32_AHB_PRESCALER=1 +CONFIG_CLOCK_STM32_APB1_PRESCALER=2 +CONFIG_CLOCK_STM32_APB2_PRESCALER=1 + #enable pwm CONFIG_PWM=y diff --git a/boards/arm/nucleo_f411re/nucleo_f411re_defconfig b/boards/arm/nucleo_f411re/nucleo_f411re_defconfig index a610e804d..215a77d79 100644 --- a/boards/arm/nucleo_f411re/nucleo_f411re_defconfig +++ b/boards/arm/nucleo_f411re/nucleo_f411re_defconfig @@ -22,20 +22,23 @@ CONFIG_GPIO=y # clock configuration CONFIG_CLOCK_CONTROL=y -CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL=y + +# Clock configuration for Cube Clock control driver +CONFIG_CLOCK_STM32_HSE_CLOCK=8000000 +CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y # use HSE as PLL input -CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE=y +CONFIG_CLOCK_STM32_PLL_SRC_HSE=y # however, the board does not have an external oscillator, so just use # the 8MHz clock signal coming from integrated STLink -CONFIG_CLOCK_STM32F4X_HSE_BYPASS=y -# produce 96MHz clock at PLL output -CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR=8 -CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER=384 -CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR=4 -CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR=8 -CONFIG_CLOCK_STM32F4X_AHB_PRESCALER=0 -CONFIG_CLOCK_STM32F4X_APB1_PRESCALER=2 -CONFIG_CLOCK_STM32F4X_APB2_PRESCALER=0 +CONFIG_CLOCK_STM32_HSE_BYPASS=y +# produce 84MHz clock at PLL output +CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8 +CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=384 +CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4 +CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=8 +CONFIG_CLOCK_STM32_AHB_PRESCALER=1 +CONFIG_CLOCK_STM32_APB1_PRESCALER=2 +CONFIG_CLOCK_STM32_APB2_PRESCALER=1 #enable DTS CONFIG_HAS_DTS=y diff --git a/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig b/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig index 3ca4c75b6..a1646590f 100644 --- a/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig +++ b/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig @@ -6,6 +6,5 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_CORTEX_M_SYSTICK=y -CONFIG_FLASH_SIZE=256 -CONFIG_SRAM_SIZE=64 CONFIG_UART_STELLARIS=y +CONFIG_HAS_DTS=y diff --git a/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble_defconfig b/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble_defconfig index 0f3a6e651..4f08c36f5 100644 --- a/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble_defconfig +++ b/boards/arm/quark_se_c1000_ble/quark_se_c1000_ble_defconfig @@ -11,3 +11,6 @@ CONFIG_UART_NRF5=y # bluetooth CONFIG_BLUETOOTH=y CONFIG_BLUETOOTH_CONTROLLER=y + +#enable DTS +CONFIG_HAS_DTS=y |
