diff options
Diffstat (limited to 'dts')
73 files changed, 795 insertions, 120 deletions
diff --git a/dts/arm/96b_carbon.dts b/dts/arm/96b_carbon.dts index 5e0f8b65a..18b97383d 100644 --- a/dts/arm/96b_carbon.dts +++ b/dts/arm/96b_carbon.dts @@ -19,11 +19,11 @@ }; &usart1 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; &usart2 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; diff --git a/dts/arm/96b_carbon.fixup b/dts/arm/96b_carbon.fixup index 197a9ac1f..f2ea618b4 100644 --- a/dts/arm/96b_carbon.fixup +++ b/dts/arm/96b_carbon.fixup @@ -8,12 +8,11 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40011000_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40011000_BAUD_RATE +#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40011000_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40011000_IRQ_0_PRIORITY #define PORT_1_IRQ ST_STM32_USART_40011000_IRQ_0 #define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY #define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 - diff --git a/dts/arm/96b_nitrogen.dts b/dts/arm/96b_nitrogen.dts new file mode 100644 index 000000000..927432a07 --- /dev/null +++ b/dts/arm/96b_nitrogen.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <nordic/nrf52832.dtsi> + +/ { + model = "Seeed Studio Nitrogen 96board"; + compatible = "seeed,nitrogen", "nordic,nrf52832-qfaa", + "nordic,nrf52832"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + compatible = "nordic,nrf-uart"; + current-speed = <115200>; + status = "ok"; +}; diff --git a/dts/arm/96b_nitrogen.fixup b/dts/arm/96b_nitrogen.fixup new file mode 100644 index 000000000..239d39e76 --- /dev/null +++ b/dts/arm/96b_nitrogen.fixup @@ -0,0 +1,3 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED diff --git a/dts/arm/Makefile b/dts/arm/Makefile index 88b47ae62..392b1ee74 100644 --- a/dts/arm/Makefile +++ b/dts/arm/Makefile @@ -1,9 +1,12 @@ ifeq ($(CONFIG_HAS_DTS),y) +dtb-$(CONFIG_BOARD_DISCO_L475_IOT1) = disco_l475_iot1.dts_compiled dtb-$(CONFIG_BOARD_FRDM_K64F) = frdm_k64f.dts_compiled dtb-$(CONFIG_BOARD_FRDM_KW41Z) = frdm_kw41z.dts_compiled +dtb-$(CONFIG_BOARD_FRDM_KL25Z) = frdm_kl25z.dts_compiled dtb-$(CONFIG_BOARD_HEXIWEAR_K64) = hexiwear_k64.dts_compiled dtb-$(CONFIG_BOARD_HEXIWEAR_KW40Z) = hexiwear_kw40z.dts_compiled dtb-$(CONFIG_BOARD_CC3200_LAUNCHXL) = cc3200_launchxl.dts_compiled +dtb-$(CONFIG_BOARD_CC3220SF_LAUNCHXL) = cc3220sf_launchxl.dts_compiled dtb-$(CONFIG_BOARD_NUCLEO_L476RG) = nucleo_l476rg.dts_compiled dtb-$(CONFIG_BOARD_V2M_BEETLE) = v2m_beetle.dts_compiled dtb-$(CONFIG_BOARD_OLIMEXINO_STM32) = olimexino_stm32.dts_compiled @@ -15,6 +18,17 @@ dtb-$(CONFIG_BOARD_STM3210C_EVAL) = stm3210c_eval.dts_compiled dtb-$(CONFIG_BOARD_STM32_MINI_A15) = stm32_mini_a15.dts_compiled dtb-$(CONFIG_BOARD_NUCLEO_F334R8) = nucleo_f334r8.dts_compiled dtb-$(CONFIG_BOARD_STM32373C_EVAL) = stm32373c_eval.dts_compiled +dtb-$(CONFIG_BOARD_96B_NITROGEN) = 96b_nitrogen.dts_compiled +dtb-$(CONFIG_BOARD_NRF52_PCA10040) = nrf52_pca10040.dts_compiled +dtb-$(CONFIG_BOARD_NRF52_BLENANO2) = nrf52_blenano2.dts_compiled +dtb-$(CONFIG_BOARD_NRF52840_PCA10056) = nrf52840_pca10056.dts_compiled +dtb-$(CONFIG_BOARD_ARDUINO_101_BLE) = arduino_101_ble.dts_compiled +dtb-$(CONFIG_BOARD_BBC_MICROBIT) = bbc_microbit.dts_compiled +dtb-$(CONFIG_BOARD_CURIE_BLE) = curie_ble.dts_compiled +dtb-$(CONFIG_BOARD_NRF51_BLENANO) = nrf51_blenano.dts_compiled +dtb-$(CONFIG_BOARD_NRF51_PCA10028) = nrf51_pca10028.dts_compiled +dtb-$(CONFIG_BOARD_QUARK_SE_C1000_BLE) = quark_se_c1000_ble.dts_compiled +dtb-$(CONFIG_BOARD_QEMU_CORTEX_M3) = qemu_cortex_m3.dts_compiled always := $(dtb-y) endif diff --git a/dts/arm/arduino_101_ble.dts b/dts/arm/arduino_101_ble.dts new file mode 100644 index 000000000..89c722f87 --- /dev/null +++ b/dts/arm/arduino_101_ble.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <nordic/nrf51822.dtsi> + +/ { + model = "Arduino 101-BLE"; + compatible = "arduino,101-ble", "nordic,nrf51822-qfaa", + "nordic,nrf51822"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + current-speed = <1000000>; + status = "ok"; +}; diff --git a/dts/arm/arduino_101_ble.fixup b/dts/arm/arduino_101_ble.fixup new file mode 100644 index 000000000..afcf87a74 --- /dev/null +++ b/dts/arm/arduino_101_ble.fixup @@ -0,0 +1,3 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED diff --git a/dts/arm/bbc_microbit.dts b/dts/arm/bbc_microbit.dts new file mode 100644 index 000000000..672ee3a13 --- /dev/null +++ b/dts/arm/bbc_microbit.dts @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <nordic/nrf51822.dtsi> + +/ { + model = "BBC Micro:bit"; + compatible = "bbc,microbit", "nordic,nrf51822-qfaa", "nordic,nrf51822"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + status = "ok"; + current-speed = <115200>; +}; diff --git a/dts/arm/bbc_microbit.fixup b/dts/arm/bbc_microbit.fixup new file mode 100644 index 000000000..afcf87a74 --- /dev/null +++ b/dts/arm/bbc_microbit.fixup @@ -0,0 +1,3 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED diff --git a/dts/arm/cc3200_launchxl.dts b/dts/arm/cc3200_launchxl.dts index af4c6aee8..199122a14 100644 --- a/dts/arm/cc3200_launchxl.dts +++ b/dts/arm/cc3200_launchxl.dts @@ -1,10 +1,10 @@ /dts-v1/; -#include <ti/cc32xx_launchxl.dtsi> +#include <ti/cc32xx.dtsi> / { model = "TI CC3200 LaunchXL"; - compatible = "ti,cc32xx"; + compatible = "ti,cc3200-launchxl","ti,cc3200","ti,cc32xx"; aliases { uart_0 = &uart0; @@ -19,4 +19,5 @@ &uart0 { status = "ok"; + current-speed = <115200>; }; diff --git a/dts/arm/cc3220sf_launchxl.dts b/dts/arm/cc3220sf_launchxl.dts new file mode 100644 index 000000000..7093d2739 --- /dev/null +++ b/dts/arm/cc3220sf_launchxl.dts @@ -0,0 +1,23 @@ +/dts-v1/; + +#include <ti/cc32xx.dtsi> + +/ { + model = "TI CC3220SF LaunchXL"; + compatible = "ti,cc3220sf-launchxl", "ti,cc3220sf", "ti,cc32xx"; + + aliases { + uart_0 = &uart0; + uart_1 = &uart1; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash1; + }; +}; + +&uart0 { + status = "ok"; + current-speed = <115200>; +}; diff --git a/dts/arm/cc3220sf_launchxl.fixup b/dts/arm/cc3220sf_launchxl.fixup new file mode 100644 index 000000000..af1312e9d --- /dev/null +++ b/dts/arm/cc3220sf_launchxl.fixup @@ -0,0 +1 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS diff --git a/dts/arm/curie_ble.dts b/dts/arm/curie_ble.dts new file mode 100644 index 000000000..2df9fff47 --- /dev/null +++ b/dts/arm/curie_ble.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <nordic/nrf51822.dtsi> + +/ { + model = "Intel Curie BLE"; + compatible = "intel,curie-ble", "nordic,nrf51822-qfaa", + "nordic,nrf51822"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + current-speed = <1000000>; + status = "ok"; +}; diff --git a/dts/arm/curie_ble.fixup b/dts/arm/curie_ble.fixup new file mode 100644 index 000000000..afcf87a74 --- /dev/null +++ b/dts/arm/curie_ble.fixup @@ -0,0 +1,3 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED diff --git a/dts/arm/disco_l475_iot1.dts b/dts/arm/disco_l475_iot1.dts new file mode 100644 index 000000000..843f32c62 --- /dev/null +++ b/dts/arm/disco_l475_iot1.dts @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <st/stm32l475.dtsi> + +/ { + model = "STMicroelectronics B-L475E-IOT01Ax board"; + compatible = "st,stm32l475-disco-iot", "st,stm32l475"; + + chosen { + zephyr,console = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&usart1 { + current-speed = <115200>; + status = "ok"; +}; diff --git a/dts/arm/disco_l475_iot1.fixup b/dts/arm/disco_l475_iot1.fixup new file mode 100644 index 000000000..ac9af9a76 --- /dev/null +++ b/dts/arm/disco_l475_iot1.fixup @@ -0,0 +1,32 @@ +/* This file is a temporary workaround for mapping of the generated information + * to the current driver definitions. This will be removed when the drivers + * are modified to handle the generated information, or the mapping of + * generated data matches the driver definitions. + */ + +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS + +#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS +#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_CURRENT_SPEED +#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY +#define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0 + +#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED +#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 + +#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS +#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_CURRENT_SPEED +#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY +#define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0 + +#define CONFIG_UART_STM32_PORT_4_BASE_ADDRESS ST_STM32_USART_40004C00_BASE_ADDRESS +#define CONFIG_UART_STM32_PORT_4_BAUD_RATE ST_STM32_USART_40004C00_CURRENT_SPEED +#define CONFIG_UART_STM32_PORT_4_IRQ_PRI ST_STM32_USART_40004C00_IRQ_0_PRIORITY +#define PORT_4_IRQ ST_STM32_USART_40004C00_IRQ_0 + +#define CONFIG_UART_STM32_PORT_5_BASE_ADDRESS ST_STM32_USART_40005000_BASE_ADDRESS +#define CONFIG_UART_STM32_PORT_5_BAUD_RATE ST_STM32_USART_40005000_CURRENT_SPEED +#define CONFIG_UART_STM32_PORT_5_IRQ_PRI ST_STM32_USART_40005000_IRQ_0_PRIORITY +#define PORT_5_IRQ ST_STM32_USART_40005000_IRQ_0 diff --git a/dts/arm/frdm_k64f.dts b/dts/arm/frdm_k64f.dts index 8e0c7f9d8..1578fb981 100644 --- a/dts/arm/frdm_k64f.dts +++ b/dts/arm/frdm_k64f.dts @@ -30,12 +30,12 @@ &uart0 { status = "ok"; - baud-rate = <115200>; + current-speed = <115200>; }; #ifdef CONFIG_BLUETOOTH &uart3 { status = "ok"; - baud-rate = <115200>; + current-speed = <115200>; }; #endif diff --git a/dts/arm/frdm_k64f.fixup b/dts/arm/frdm_k64f.fixup index d2e90c53c..469af0493 100644 --- a/dts/arm/frdm_k64f.fixup +++ b/dts/arm/frdm_k64f.fixup @@ -1,19 +1,19 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE +#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_CURRENT_SPEED #define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_K64F_UART_4006B000_BAUD_RATE +#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_K64F_UART_4006B000_CURRENT_SPEED #define CONFIG_UART_MCUX_1_IRQ_PRI NXP_K64F_UART_4006B000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_K64F_UART_4006C000_BAUD_RATE +#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_K64F_UART_4006C000_CURRENT_SPEED #define CONFIG_UART_MCUX_2_IRQ_PRI NXP_K64F_UART_4006C000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_K64F_UART_4006D000_BAUD_RATE +#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_K64F_UART_4006D000_CURRENT_SPEED #define CONFIG_UART_MCUX_3_IRQ_PRI NXP_K64F_UART_4006D000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_4_BAUD_RATE NXP_K64F_UART_400EA000_BAUD_RATE +#define CONFIG_UART_MCUX_4_BAUD_RATE NXP_K64F_UART_400EA000_CURRENT_SPEED #define CONFIG_UART_MCUX_4_IRQ_PRI NXP_K64F_UART_400EA000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_5_BAUD_RATE NXP_K64F_UART_400EB000_BAUD_RATE +#define CONFIG_UART_MCUX_5_BAUD_RATE NXP_K64F_UART_400EB000_CURRENT_SPEED #define CONFIG_UART_MCUX_5_IRQ_PRI NXP_K64F_UART_400EB000_IRQ_0_PRIORITY diff --git a/dts/arm/frdm_kl25z.dts b/dts/arm/frdm_kl25z.dts new file mode 100644 index 000000000..d8f358fdd --- /dev/null +++ b/dts/arm/frdm_kl25z.dts @@ -0,0 +1,23 @@ +/dts-v1/; + +#include <nxp/nxp_kl25z.dtsi> + +/ { + model = "NXP Freedom KL25Z board"; + compatible = "nxp,frdm-kl25z", "nxp,kl25z", "nxp,mkl25z4"; + + aliases { + uart_0 = &uart0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + }; +}; + +&uart0 { + status = "ok"; + current-speed = <115200>; +}; diff --git a/dts/arm/frdm_kl25z.fixup b/dts/arm/frdm_kl25z.fixup new file mode 100644 index 000000000..1627806ea --- /dev/null +++ b/dts/arm/frdm_kl25z.fixup @@ -0,0 +1 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS diff --git a/dts/arm/frdm_kw41z.dts b/dts/arm/frdm_kw41z.dts index ed1450495..ff0e8f9c8 100644 --- a/dts/arm/frdm_kw41z.dts +++ b/dts/arm/frdm_kw41z.dts @@ -25,4 +25,5 @@ &lpuart0 { status = "ok"; + current-speed = <115200>; }; diff --git a/dts/arm/frdm_kw41z.fixup b/dts/arm/frdm_kw41z.fixup index 337f5f424..229a60fdf 100644 --- a/dts/arm/frdm_kw41z.fixup +++ b/dts/arm/frdm_kw41z.fixup @@ -1,4 +1,4 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_BAUD_RATE +#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_CURRENT_SPEED #define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KW41Z_LPUART_40054000_IRQ_0_PRIORITY diff --git a/dts/arm/hexiwear_k64.dts b/dts/arm/hexiwear_k64.dts index f4230eb81..b03db7490 100644 --- a/dts/arm/hexiwear_k64.dts +++ b/dts/arm/hexiwear_k64.dts @@ -31,12 +31,12 @@ &uart0 { status = "ok"; - baud-rate = <115200>; + current-speed = <115200>; }; #ifdef CONFIG_BLUETOOTH &uart4 { status = "ok"; - baud-rate = <115200>; + current-speed = <115200>; }; #endif diff --git a/dts/arm/hexiwear_k64.fixup b/dts/arm/hexiwear_k64.fixup index d2e90c53c..469af0493 100644 --- a/dts/arm/hexiwear_k64.fixup +++ b/dts/arm/hexiwear_k64.fixup @@ -1,19 +1,19 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE +#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_CURRENT_SPEED #define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_K64F_UART_4006B000_BAUD_RATE +#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_K64F_UART_4006B000_CURRENT_SPEED #define CONFIG_UART_MCUX_1_IRQ_PRI NXP_K64F_UART_4006B000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_K64F_UART_4006C000_BAUD_RATE +#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_K64F_UART_4006C000_CURRENT_SPEED #define CONFIG_UART_MCUX_2_IRQ_PRI NXP_K64F_UART_4006C000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_K64F_UART_4006D000_BAUD_RATE +#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_K64F_UART_4006D000_CURRENT_SPEED #define CONFIG_UART_MCUX_3_IRQ_PRI NXP_K64F_UART_4006D000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_4_BAUD_RATE NXP_K64F_UART_400EA000_BAUD_RATE +#define CONFIG_UART_MCUX_4_BAUD_RATE NXP_K64F_UART_400EA000_CURRENT_SPEED #define CONFIG_UART_MCUX_4_IRQ_PRI NXP_K64F_UART_400EA000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_5_BAUD_RATE NXP_K64F_UART_400EB000_BAUD_RATE +#define CONFIG_UART_MCUX_5_BAUD_RATE NXP_K64F_UART_400EB000_CURRENT_SPEED #define CONFIG_UART_MCUX_5_IRQ_PRI NXP_K64F_UART_400EB000_IRQ_0_PRIORITY diff --git a/dts/arm/hexiwear_kw40z.dts b/dts/arm/hexiwear_kw40z.dts index abe803481..23964e826 100644 --- a/dts/arm/hexiwear_kw40z.dts +++ b/dts/arm/hexiwear_kw40z.dts @@ -24,5 +24,5 @@ &lpuart0 { status = "ok"; - baud-rate = <115200>; + current-speed = <115200>; }; diff --git a/dts/arm/hexiwear_kw40z.fixup b/dts/arm/hexiwear_kw40z.fixup index 337f5f424..229a60fdf 100644 --- a/dts/arm/hexiwear_kw40z.fixup +++ b/dts/arm/hexiwear_kw40z.fixup @@ -1,4 +1,4 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_BAUD_RATE +#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_CURRENT_SPEED #define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KW41Z_LPUART_40054000_IRQ_0_PRIORITY diff --git a/dts/arm/nordic/nrf51822.dtsi b/dts/arm/nordic/nrf51822.dtsi new file mode 100644 index 000000000..f7445e5a8 --- /dev/null +++ b/dts/arm/nordic/nrf51822.dtsi @@ -0,0 +1,31 @@ +#include <arm/armv6-m.dtsi> +#include <nordic/mem.h> + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-m0"; + }; + }; + + flash0: flash { + reg = <0x00000000 DT_FLASH_SIZE>; + }; + + sram0: memory { + reg = <0x20000000 DT_SRAM_SIZE>; + }; + + soc { + uart0: uart@40002000 { + compatible = "nordic,nrf-uart"; + reg = <0x40002000 0x1000>; + interrupts = <2 1>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; diff --git a/dts/arm/nordic/nrf52840.dtsi b/dts/arm/nordic/nrf52840.dtsi new file mode 100644 index 000000000..fa13f3c5c --- /dev/null +++ b/dts/arm/nordic/nrf52840.dtsi @@ -0,0 +1,38 @@ +#include <arm/armv7-m.dtsi> +#include <nordic/mem.h> + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-m4f"; + }; + }; + + flash0: flash { + reg = <0x00000000 DT_FLASH_SIZE>; + }; + + sram0: memory { + reg = <0x20000000 DT_SRAM_SIZE>; + }; + + soc { + uart0: uart@40002000 { + compatible = "nordic,nrf-uarte", "nordic,nrf-uart"; + reg = <0x40002000 0x1000>; + interrupts = <2 1>; + status = "disabled"; + }; + + uart1: uart@40028000 { + compatible = "nordic,nrf-uarte"; + reg = <0x40028000 0x1000>; + interrupts = <40 1>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/nrf51_blenano.dts b/dts/arm/nrf51_blenano.dts new file mode 100644 index 000000000..c756d584b --- /dev/null +++ b/dts/arm/nrf51_blenano.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <nordic/nrf51822.dtsi> + +/ { + model = "Redbear BLE Nano"; + compatible = "redbear,blenano", "nordic,nrf51822-qfaa", + "nordic,nrf51822"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + current-speed = <115200>; + status = "ok"; +}; diff --git a/dts/arm/nrf51_blenano.fixup b/dts/arm/nrf51_blenano.fixup new file mode 100644 index 000000000..afcf87a74 --- /dev/null +++ b/dts/arm/nrf51_blenano.fixup @@ -0,0 +1,3 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED diff --git a/dts/arm/nrf51_pca10028.dts b/dts/arm/nrf51_pca10028.dts new file mode 100644 index 000000000..90a9b2d63 --- /dev/null +++ b/dts/arm/nrf51_pca10028.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <nordic/nrf51822.dtsi> + +/ { + model = "Nordic PCA10028 Dev Kit"; + compatible = "nordic,pca10028-dk", "nordic,nrf51822-qfac", + "nordic,nrf51822"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + current-speed = <115200>; + status = "ok"; +}; diff --git a/dts/arm/nrf51_pca10028.fixup b/dts/arm/nrf51_pca10028.fixup new file mode 100644 index 000000000..afcf87a74 --- /dev/null +++ b/dts/arm/nrf51_pca10028.fixup @@ -0,0 +1,3 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED diff --git a/dts/arm/nrf52840_pca10056.dts b/dts/arm/nrf52840_pca10056.dts new file mode 100644 index 000000000..20a9e8316 --- /dev/null +++ b/dts/arm/nrf52840_pca10056.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <nordic/nrf52840.dtsi> + +/ { + model = "Nordic PCA10056 Dev Kit"; + compatible = "nordic,pca10056-dk", "nordic,nrf52840-qiaa", + "nordic,nrf52840"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + compatible = "nordic,nrf-uart"; + current-speed = <115200>; + status = "ok"; +}; diff --git a/dts/arm/nrf52840_pca10056.fixup b/dts/arm/nrf52840_pca10056.fixup new file mode 100644 index 000000000..239d39e76 --- /dev/null +++ b/dts/arm/nrf52840_pca10056.fixup @@ -0,0 +1,3 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED diff --git a/dts/arm/nrf52_blenano2.dts b/dts/arm/nrf52_blenano2.dts new file mode 100644 index 000000000..c58a85e48 --- /dev/null +++ b/dts/arm/nrf52_blenano2.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <nordic/nrf52832.dtsi> + +/ { + model = "Redbear BLE Nano 2"; + compatible = "redbear,blenano2", "nordic,nrf52832-qfaa", + "nordic,nrf52832"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + compatible = "nordic,nrf-uart"; + current-speed = <115200>; + status = "ok"; +}; diff --git a/dts/arm/nrf52_blenano2.fixup b/dts/arm/nrf52_blenano2.fixup new file mode 100644 index 000000000..239d39e76 --- /dev/null +++ b/dts/arm/nrf52_blenano2.fixup @@ -0,0 +1,3 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED diff --git a/dts/arm/nrf52_pca10040.dts b/dts/arm/nrf52_pca10040.dts new file mode 100644 index 000000000..80e147361 --- /dev/null +++ b/dts/arm/nrf52_pca10040.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <nordic/nrf52832.dtsi> + +/ { + model = "Nordic PCA10040 Dev Kit"; + compatible = "nordic,pca10040-dk", "nordic,nrf52832-qfaa", + "nordic,nrf52832"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + status = "ok"; + compatible = "nordic,nrf-uart"; + current-speed = <115200>; +}; diff --git a/dts/arm/nrf52_pca10040.fixup b/dts/arm/nrf52_pca10040.fixup new file mode 100644 index 000000000..239d39e76 --- /dev/null +++ b/dts/arm/nrf52_pca10040.fixup @@ -0,0 +1,3 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED diff --git a/dts/arm/nucleo_f103rb.dts b/dts/arm/nucleo_f103rb.dts index b98bc107b..f40da9dec 100644 --- a/dts/arm/nucleo_f103rb.dts +++ b/dts/arm/nucleo_f103rb.dts @@ -19,6 +19,6 @@ }; &usart2 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; diff --git a/dts/arm/nucleo_f103rb.fixup b/dts/arm/nucleo_f103rb.fixup index 4b3ec44ea..ff2881d88 100644 --- a/dts/arm/nucleo_f103rb.fixup +++ b/dts/arm/nucleo_f103rb.fixup @@ -8,6 +8,6 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY #define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 diff --git a/dts/arm/nucleo_f334r8.dts b/dts/arm/nucleo_f334r8.dts index 9c5035082..8878ed8c1 100644 --- a/dts/arm/nucleo_f334r8.dts +++ b/dts/arm/nucleo_f334r8.dts @@ -19,6 +19,6 @@ }; &usart2 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; diff --git a/dts/arm/nucleo_f334r8.fixup b/dts/arm/nucleo_f334r8.fixup index 4b3ec44ea..ff2881d88 100644 --- a/dts/arm/nucleo_f334r8.fixup +++ b/dts/arm/nucleo_f334r8.fixup @@ -8,6 +8,6 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY #define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 diff --git a/dts/arm/nucleo_f401re.dts b/dts/arm/nucleo_f401re.dts index 997ade256..dfef02613 100644 --- a/dts/arm/nucleo_f401re.dts +++ b/dts/arm/nucleo_f401re.dts @@ -19,11 +19,11 @@ }; &usart1 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; &usart2 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; diff --git a/dts/arm/nucleo_f401re.fixup b/dts/arm/nucleo_f401re.fixup index 197a9ac1f..f2ea618b4 100644 --- a/dts/arm/nucleo_f401re.fixup +++ b/dts/arm/nucleo_f401re.fixup @@ -8,12 +8,11 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40011000_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40011000_BAUD_RATE +#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40011000_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40011000_IRQ_0_PRIORITY #define PORT_1_IRQ ST_STM32_USART_40011000_IRQ_0 #define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY #define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 - diff --git a/dts/arm/nucleo_f411re.dts b/dts/arm/nucleo_f411re.dts index cdf3f4c45..ca237541b 100644 --- a/dts/arm/nucleo_f411re.dts +++ b/dts/arm/nucleo_f411re.dts @@ -19,11 +19,11 @@ }; &usart1 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; &usart2 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; diff --git a/dts/arm/nucleo_f411re.fixup b/dts/arm/nucleo_f411re.fixup index 197a9ac1f..f2ea618b4 100644 --- a/dts/arm/nucleo_f411re.fixup +++ b/dts/arm/nucleo_f411re.fixup @@ -8,12 +8,11 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40011000_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40011000_BAUD_RATE +#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40011000_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40011000_IRQ_0_PRIORITY #define PORT_1_IRQ ST_STM32_USART_40011000_IRQ_0 #define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY #define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 - diff --git a/dts/arm/nucleo_l476rg.dts b/dts/arm/nucleo_l476rg.dts index 04aff092a..2df09d911 100644 --- a/dts/arm/nucleo_l476rg.dts +++ b/dts/arm/nucleo_l476rg.dts @@ -19,6 +19,6 @@ }; &usart2 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; diff --git a/dts/arm/nucleo_l476rg.fixup b/dts/arm/nucleo_l476rg.fixup index 410a78c5b..ac9af9a76 100644 --- a/dts/arm/nucleo_l476rg.fixup +++ b/dts/arm/nucleo_l476rg.fixup @@ -7,26 +7,26 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE +#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY #define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0 #define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY #define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 #define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_BAUD_RATE +#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY #define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0 #define CONFIG_UART_STM32_PORT_4_BASE_ADDRESS ST_STM32_USART_40004C00_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_4_BAUD_RATE ST_STM32_USART_40004C00_BAUD_RATE +#define CONFIG_UART_STM32_PORT_4_BAUD_RATE ST_STM32_USART_40004C00_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_4_IRQ_PRI ST_STM32_USART_40004C00_IRQ_0_PRIORITY #define PORT_4_IRQ ST_STM32_USART_40004C00_IRQ_0 #define CONFIG_UART_STM32_PORT_5_BASE_ADDRESS ST_STM32_USART_40005000_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_5_BAUD_RATE ST_STM32_USART_40005000_BAUD_RATE +#define CONFIG_UART_STM32_PORT_5_BAUD_RATE ST_STM32_USART_40005000_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_5_IRQ_PRI ST_STM32_USART_40005000_IRQ_0_PRIORITY #define PORT_5_IRQ ST_STM32_USART_40005000_IRQ_0 diff --git a/dts/arm/nxp/nxp_kl25z.dtsi b/dts/arm/nxp/nxp_kl25z.dtsi new file mode 100644 index 000000000..e43895f68 --- /dev/null +++ b/dts/arm/nxp/nxp_kl25z.dtsi @@ -0,0 +1,32 @@ +#include "armv6-m.dtsi" + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-m0+"; + }; + }; + + sram0: memory { + compatible = "mmio-sram"; + reg = <0x1FFFF000 0x4000>; + }; + + soc { + flash0: flash@0 { + reg = <0 0x20000>; + }; + + uart0: uart@4006A000 { + compatible = "nxp,kinetis-lpsci"; + reg = <0x4006A000 0xc>; + interrupts = <12 0>; + + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; diff --git a/dts/arm/nxp/nxp_kw41z.dtsi b/dts/arm/nxp/nxp_kw41z.dtsi index e6aff70ba..5ea7850b3 100644 --- a/dts/arm/nxp/nxp_kw41z.dtsi +++ b/dts/arm/nxp/nxp_kw41z.dtsi @@ -49,7 +49,6 @@ reg = <0x40054000 0x18>; interrupts = <12 0>; - baud-rate = <115200>; pinctrl-0 = <&lpuart0_default>; pinctrl-names = "default"; diff --git a/dts/arm/olimexino_stm32.dts b/dts/arm/olimexino_stm32.dts index b0a0383ba..ce819f91f 100644 --- a/dts/arm/olimexino_stm32.dts +++ b/dts/arm/olimexino_stm32.dts @@ -19,6 +19,6 @@ }; &usart1 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; diff --git a/dts/arm/olimexino_stm32.fixup b/dts/arm/olimexino_stm32.fixup index b3ac22140..61065ddeb 100644 --- a/dts/arm/olimexino_stm32.fixup +++ b/dts/arm/olimexino_stm32.fixup @@ -8,16 +8,16 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE +#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY #define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0 #define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY #define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 #define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_BAUD_RATE +#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY #define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0 diff --git a/dts/arm/qemu_cortex_m3.dts b/dts/arm/qemu_cortex_m3.dts new file mode 100644 index 000000000..ad2cb626a --- /dev/null +++ b/dts/arm/qemu_cortex_m3.dts @@ -0,0 +1,34 @@ +/dts-v1/; + +#include <ti/lm3s6965.dtsi> + +/ { + model = "QEMU Cortex-M3"; + compatible = "ti,lm3s6965evb-qemu", "ti,lm3s6965"; + + aliases { + uart_0 = &uart0; + uart_1 = &uart1; + uart_2 = &uart2; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + status = "ok"; + current-speed = <115200>; +}; + +&uart1 { + status = "ok"; + current-speed = <115200>; +}; + +&uart2 { + status = "ok"; + current-speed = <115200>; +}; diff --git a/dts/arm/qemu_cortex_m3.fixup b/dts/arm/qemu_cortex_m3.fixup new file mode 100644 index 000000000..af1312e9d --- /dev/null +++ b/dts/arm/qemu_cortex_m3.fixup @@ -0,0 +1 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS diff --git a/dts/arm/quark_se_c1000_ble.dts b/dts/arm/quark_se_c1000_ble.dts new file mode 100644 index 000000000..54d7b158a --- /dev/null +++ b/dts/arm/quark_se_c1000_ble.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include <nordic/nrf51822.dtsi> + +/ { + model = "Intel Quark SE C1000 BLE"; + compatible = "intel,quark-se-c1000-ble", "nordic,nrf51822-qfaa", + "nordic,nrf51822"; + + chosen { + zephyr,console = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + status = "ok"; + current-speed = <1000000>; +}; diff --git a/dts/arm/quark_se_c1000_ble.fixup b/dts/arm/quark_se_c1000_ble.fixup new file mode 100644 index 000000000..afcf87a74 --- /dev/null +++ b/dts/arm/quark_se_c1000_ble.fixup @@ -0,0 +1,3 @@ +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_NRF5_IRQ_PRI NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define CONFIG_UART_NRF5_BAUD_RATE NORDIC_NRF_UART_40002000_CURRENT_SPEED diff --git a/dts/arm/st/mem.h b/dts/arm/st/mem.h index b4bb13ff4..b9628bafe 100644 --- a/dts/arm/st/mem.h +++ b/dts/arm/st/mem.h @@ -33,6 +33,9 @@ #elif defined(CONFIG_SOC_STM32F429XX) #define DT_FLASH_SIZE __SIZE_K(2048) #define DT_SRAM_SIZE __SIZE_K(256) +#elif defined(CONFIG_SOC_STM32L475XG) +#define DT_FLASH_SIZE __SIZE_K(1024) +#define DT_SRAM_SIZE __SIZE_K(96) #elif defined(CONFIG_SOC_STM32L476XX) #define DT_FLASH_SIZE __SIZE_K(1024) #define DT_SRAM_SIZE __SIZE_K(96) diff --git a/dts/arm/st/stm32l475.dtsi b/dts/arm/st/stm32l475.dtsi new file mode 100644 index 000000000..19329faaf --- /dev/null +++ b/dts/arm/st/stm32l475.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <arm/armv7-m.dtsi> +#include <st/mem.h> + +/ { + flash0: flash { + reg = <0x08000000 DT_FLASH_SIZE>; + }; + + sram0: memory { + reg = <0x20000000 DT_SRAM_SIZE>; + }; + + soc { + usart1: uart@40013800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40013800 0x400>; + interrupts = <37 0>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38 0>; + status = "disabled"; + }; + + usart3: uart@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + interrupts = <39 0>; + status = "disabled"; + }; + + uart4: uart@40004c00 { + compatible = "st,stm32-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52 0>; + status = "disabled"; + }; + + uart5: uart@40005000 { + compatible = "st,stm32-uart"; + reg = <0x40005000 0x400>; + interrupts = <53 0>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/st/stm32l476.dtsi b/dts/arm/st/stm32l476.dtsi index 19329faaf..7b336a2ac 100644 --- a/dts/arm/st/stm32l476.dtsi +++ b/dts/arm/st/stm32l476.dtsi @@ -4,56 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include <arm/armv7-m.dtsi> -#include <st/mem.h> - -/ { - flash0: flash { - reg = <0x08000000 DT_FLASH_SIZE>; - }; - - sram0: memory { - reg = <0x20000000 DT_SRAM_SIZE>; - }; - - soc { - usart1: uart@40013800 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40013800 0x400>; - interrupts = <37 0>; - status = "disabled"; - }; - - usart2: uart@40004400 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40004400 0x400>; - interrupts = <38 0>; - status = "disabled"; - }; - - usart3: uart@40004800 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40004800 0x400>; - interrupts = <39 0>; - status = "disabled"; - }; - - uart4: uart@40004c00 { - compatible = "st,stm32-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52 0>; - status = "disabled"; - }; - - uart5: uart@40005000 { - compatible = "st,stm32-uart"; - reg = <0x40005000 0x400>; - interrupts = <53 0>; - status = "disabled"; - }; - }; -}; - -&nvic { - arm,num-irq-priority-bits = <4>; -}; +#include <st/stm32l475.dtsi> diff --git a/dts/arm/stm3210c_eval.dts b/dts/arm/stm3210c_eval.dts index e3388e6a3..84ae83b12 100644 --- a/dts/arm/stm3210c_eval.dts +++ b/dts/arm/stm3210c_eval.dts @@ -19,6 +19,6 @@ }; &usart2 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; diff --git a/dts/arm/stm3210c_eval.fixup b/dts/arm/stm3210c_eval.fixup index 4b3ec44ea..ff2881d88 100644 --- a/dts/arm/stm3210c_eval.fixup +++ b/dts/arm/stm3210c_eval.fixup @@ -8,6 +8,6 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY #define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 diff --git a/dts/arm/stm32373c_eval.dts b/dts/arm/stm32373c_eval.dts index e649a3387..0392c2b5a 100644 --- a/dts/arm/stm32373c_eval.dts +++ b/dts/arm/stm32373c_eval.dts @@ -19,6 +19,6 @@ }; &usart2 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; diff --git a/dts/arm/stm32373c_eval.fixup b/dts/arm/stm32373c_eval.fixup index 4b3ec44ea..ff2881d88 100644 --- a/dts/arm/stm32373c_eval.fixup +++ b/dts/arm/stm32373c_eval.fixup @@ -8,6 +8,6 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY #define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 diff --git a/dts/arm/stm32_mini_a15.dts b/dts/arm/stm32_mini_a15.dts index 39ed05862..6f1de84a0 100644 --- a/dts/arm/stm32_mini_a15.dts +++ b/dts/arm/stm32_mini_a15.dts @@ -19,6 +19,6 @@ }; &usart1 { - baud-rate = <115200>; + current-speed = <115200>; status = "ok"; }; diff --git a/dts/arm/stm32_mini_a15.fixup b/dts/arm/stm32_mini_a15.fixup index cb4f5bfc1..101fe65a0 100644 --- a/dts/arm/stm32_mini_a15.fixup +++ b/dts/arm/stm32_mini_a15.fixup @@ -8,6 +8,6 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS -#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE +#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_CURRENT_SPEED #define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY #define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0 diff --git a/dts/arm/ti/cc32xx_launchxl.dtsi b/dts/arm/ti/cc32xx.dtsi index 0254f647d..c88db0e2e 100644 --- a/dts/arm/ti/cc32xx_launchxl.dtsi +++ b/dts/arm/ti/cc32xx.dtsi @@ -1,7 +1,8 @@ #include <arm/armv7-m.dtsi> #include <inc/hw_ints.h> +#include <ti/mem.h> -/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC3200 SDK */ +/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */ /* which are offset by 16: */ #define EXP_UARTA0 (INT_UARTA0 - 16) #define EXP_UARTA1 (INT_UARTA1 - 16) @@ -15,20 +16,25 @@ sram0: memory { compatible = "sram"; - reg = <0x20004000 0x3C000>; + reg = <DT_SRAM_START DT_SRAM_SIZE>; }; flash0: serial-flash { compatible = "serial-flash"; - reg = <0x0 0x80000>; + reg = <0x0 DT_SFLASH_SIZE>; }; +#if defined(CONFIG_SOC_CC3220SF) + flash1: flash { + reg = <0x01000000 DT_FLASH_SIZE>; + }; +#endif + soc { uart0: uart@4000C000 { compatible = "ti,cc32xx-uart"; reg = <0x4000C000 0x4c>; interrupts = <EXP_UARTA0 3>; - baud-rate = <115200>; status = "disabled"; }; @@ -36,7 +42,6 @@ compatible = "ti,cc32xx-uart"; reg = <0x4000D000 0x4c>; interrupts = <EXP_UARTA1 3>; - baud-rate = <115200>; status = "disabled"; }; diff --git a/dts/arm/ti/lm3s6965.dtsi b/dts/arm/ti/lm3s6965.dtsi new file mode 100644 index 000000000..007c6a26e --- /dev/null +++ b/dts/arm/ti/lm3s6965.dtsi @@ -0,0 +1,45 @@ +#include <arm/armv7-m.dtsi> + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-m3"; + }; + }; + + sram0: memory { + compatible = "sram"; + reg = <0x20000000 (64*1024)>; + }; + + flash0: flash { + reg = <0x00000000 (256*1024)>; + }; + + soc { + uart0: uart@4000C000 { + compatible = "ti,stellaris-uart"; + reg = <0x4000C000 0x4c>; + interrupts = <5 3>; + status = "disabled"; + }; + + uart1: uart@4000D000 { + compatible = "ti,stellaris-uart"; + reg = <0x4000D000 0x4c>; + interrupts = <6 3>; + status = "disabled"; + }; + + uart2: uart@4000E000 { + compatible = "ti,stellaris-uart"; + reg = <0x4000E000 0x4c>; + interrupts = <33 3>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/ti/mem.h b/dts/arm/ti/mem.h new file mode 100644 index 000000000..3f628f5fe --- /dev/null +++ b/dts/arm/ti/mem.h @@ -0,0 +1,19 @@ +#ifndef __DT_BINDING_TI_MEM_H +#define __DT_BINDING_TI_MEM_H + +#define __SIZE_K(x) (x * 1024) + +#if defined(CONFIG_SOC_CC3200) +#define DT_SFLASH_SIZE __SIZE_K(1024) +#define DT_SRAM_SIZE __SIZE_K(240) +#define DT_SRAM_START 0x20004000 +#elif defined(CONFIG_SOC_CC3220SF) +#define DT_SFLASH_SIZE __SIZE_K(1024) +#define DT_FLASH_SIZE __SIZE_K(1024) +#define DT_SRAM_SIZE __SIZE_K(256) +#define DT_SRAM_START 0x20000000 +#else +#error "Flash and RAM sizes not defined for this chip" +#endif + +#endif /* __DT_BINDING_TI_MEM_H */ diff --git a/dts/arm/v2m_beetle.dts b/dts/arm/v2m_beetle.dts index 6296de35a..13150cb66 100644 --- a/dts/arm/v2m_beetle.dts +++ b/dts/arm/v2m_beetle.dts @@ -34,14 +34,14 @@ compatible = "arm,cmsdk-uart"; reg = <0x40004000 0x14>; interrupts = <IRQ_UART0 3>; - baud-rate = <115200>; + current-speed = <115200>; }; uart1: uart@40005000 { compatible = "arm,cmsdk-uart"; reg = <0x40005000 0x14>; interrupts = <IRQ_UART1 3>; - baud-rate = <115200>; + current-speed = <115200>; }; }; }; diff --git a/dts/arm/v2m_beetle.fixup b/dts/arm/v2m_beetle.fixup index 44f0b70cf..4fa75f4e6 100644 --- a/dts/arm/v2m_beetle.fixup +++ b/dts/arm/v2m_beetle.fixup @@ -2,8 +2,8 @@ #define CMSDK_APB_UART_0_IRQ ARM_CMSDK_UART_40004000_IRQ_0 #define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY -#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE ARM_CMSDK_UART_40004000_BAUD_RATE +#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE ARM_CMSDK_UART_40004000_CURRENT_SPEED #define CMSDK_APB_UART_1_IRQ ARM_CMSDK_UART_40005000_IRQ_0 #define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY -#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE ARM_CMSDK_UART_40005000_BAUD_RATE +#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE ARM_CMSDK_UART_40005000_CURRENT_SPEED diff --git a/dts/arm/yaml/nxp,kinetis-lpsci.yaml b/dts/arm/yaml/nxp,kinetis-lpsci.yaml new file mode 100644 index 000000000..205afc705 --- /dev/null +++ b/dts/arm/yaml/nxp,kinetis-lpsci.yaml @@ -0,0 +1,31 @@ +--- +title: Kinetis LPSCI UART +id: nxp,kinetis-lpsci +version: 0.1 + +description: > + This binding gives a base representation of the LPSCI UART + +inherits: + - !include uart.yaml + +properties: + - compatible: + type: string + category: required + description: compatible strings + constraint: "nxp,kinetis-lpsci" + + - reg: + type: array + description: mmio register space + generation: define + category: required + + - interrupts: + type: array + category: required + description: required interrupts + generation: define + +... diff --git a/dts/arm/yaml/ti,stellaris-uart.yaml b/dts/arm/yaml/ti,stellaris-uart.yaml new file mode 100644 index 000000000..281a908e8 --- /dev/null +++ b/dts/arm/yaml/ti,stellaris-uart.yaml @@ -0,0 +1,30 @@ +--- +title: TI Stellaris UART +id: ti,stellaris-uart +version: 0.1 + +description: > + This binding gives a base representation of the TI Stellaris UART + +inherits: + - !include uart.yaml + +properties: + - compatible: + type: string + category: required + description: compatible strings + constraint: "ti,stellaris-uart" + + - reg: + type: array + description: mmio register space + generation: define + category: required + + - interrupts: + type: array + category: required + description: required interrupts + generation: define +... diff --git a/dts/common/yaml/uart.yaml b/dts/common/yaml/uart.yaml index 6622395c5..dfd4af355 100644 --- a/dts/common/yaml/uart.yaml +++ b/dts/common/yaml/uart.yaml @@ -12,7 +12,7 @@ properties: category: optional description: Clock frequency information for UART operation generation: define - - baud-rate: + - current-speed: type: int category: required description: Initial baud rate setting for UART |