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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-02-28 08:48:15 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-03-01 11:49:03 +0000 |
| commit | 1b54495d6608dbe2ee9c31840b9033878b01a430 (patch) | |
| tree | 87b15487ae7bf9bf7ccfc1e7141d1dbf2a871375 | |
| parent | ca94510e85dbad408a33a1004dbae7521034b4e2 (diff) | |
Add aa64 fcadd + fcmla
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | aarch64.risu | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/aarch64.risu b/aarch64.risu index 780ee6d..c4eda7a 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -2956,6 +2956,19 @@ SQRDMLSHse A64_V81 01111111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5 # SQRDMLSH (element, vector) SQRDMLSHve A64_V81 0 q:1 101111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5 +# +# AdvSIMD v8.3 extensions +# +@v8_3_compnum + +# FCADD (three registers of the same type) +FCADD A64_V83 0 q:1 101110 size:2 0 rm:5 111 rot:1 01 rn:5 rd:5 + +# FCMLA (three registers of the same type) +FCMLA A64_V83 0 q:1 101110 size:2 0 rm:5 110 rot:2 1 rn:5 rd:5 +# FCMLA (vector x indexed element) +FCMLA_idx A64_V83 0 q:1 101111 size:2 l:1 m:1 rm:4 0 rot:2 1 h:1 0 rn:5 rd:5 + @ # End of: # Data processing - SIMD and floating point |